1 /* $NetBSD: cpuregs.h,v 1.70 2006/05/15 02:26:54 simonb Exp $ */
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
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11 * modification, are permitted provided that the following conditions
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
38 * Machine dependent constants.
40 * Copyright (C) 1989 Digital Equipment Corporation.
41 * Permission to use, copy, modify, and distribute this software and
42 * its documentation for any purpose and without fee is hereby granted,
43 * provided that the above copyright notice appears in all copies.
44 * Digital Equipment Corporation makes no representations about the
45 * suitability of this software for any purpose. It is provided "as is"
46 * without express or implied warranty.
48 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
49 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
50 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
51 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
52 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
53 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
58 #ifndef _MIPS_CPUREGS_H_
59 #define _MIPS_CPUREGS_H_
63 * 32-bit mips CPUS partition their 32-bit address space into four segments:
65 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
66 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
67 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
68 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
70 * Caching of mapped addresses is controlled by bits in the TLB entry.
73 #define MIPS_KSEG0_LARGEST_PHYS (0x20000000)
74 #define MIPS_KSEG0_PHYS_MASK (0x1fffffff)
75 #define MIPS_XKPHYS_LARGEST_PHYS (0x10000000000) /* 40 bit PA */
76 #define MIPS_XKPHYS_PHYS_MASK (0x0ffffffffff)
79 #define MIPS_KUSEG_START 0x00000000
80 #define MIPS_KSEG0_START ((intptr_t)(int32_t)0x80000000)
81 #define MIPS_KSEG0_END ((intptr_t)(int32_t)0x9fffffff)
82 #define MIPS_KSEG1_START ((intptr_t)(int32_t)0xa0000000)
83 #define MIPS_KSEG1_END ((intptr_t)(int32_t)0xbfffffff)
84 #define MIPS_KSSEG_START ((intptr_t)(int32_t)0xc0000000)
85 #define MIPS_KSSEG_END ((intptr_t)(int32_t)0xdfffffff)
86 #define MIPS_KSEG3_START ((intptr_t)(int32_t)0xe0000000)
87 #define MIPS_KSEG3_END ((intptr_t)(int32_t)0xffffffff)
88 #define MIPS_KSEG2_START MIPS_KSSEG_START
89 #define MIPS_KSEG2_END MIPS_KSSEG_END
92 #define MIPS_PHYS_TO_KSEG0(x) ((uintptr_t)(x) | MIPS_KSEG0_START)
93 #define MIPS_PHYS_TO_KSEG1(x) ((uintptr_t)(x) | MIPS_KSEG1_START)
94 #define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
95 #define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_KSEG0_PHYS_MASK)
97 #define MIPS_IS_KSEG0_ADDR(x) \
98 (((vm_offset_t)(x) >= MIPS_KSEG0_START) && \
99 ((vm_offset_t)(x) <= MIPS_KSEG0_END))
100 #define MIPS_IS_KSEG1_ADDR(x) \
101 (((vm_offset_t)(x) >= MIPS_KSEG1_START) && \
102 ((vm_offset_t)(x) <= MIPS_KSEG1_END))
103 #define MIPS_IS_VALID_PTR(x) (MIPS_IS_KSEG0_ADDR(x) || \
104 MIPS_IS_KSEG1_ADDR(x))
107 * Cache Coherency Attributes:
109 * UA: Uncached accelerated.
110 * C: Cacheable, coherency unspecified.
111 * CNC: Cacheable non-coherent.
112 * CC: Cacheable coherent.
113 * CCS: Cacheable coherent, shared read.
114 * CCE: Cacheable coherent, exclusive read.
115 * CCEW: Cacheable coherent, exclusive write.
116 * CCUOW: Cacheable coherent, update on write.
118 * Note that some bits vary in meaning across implementations (and that the
119 * listing here is no doubt incomplete) and that the optimal cached mode varies
120 * between implementations. 0x02 is required to be UC and 0x03 is required to
123 * We define the following logical bits:
125 * The optimal uncached mode for the target CPU type. This must
126 * be suitable for use in accessing memory-mapped devices.
127 * CACHED: The optional cached mode for the target CPU type.
130 #define MIPS_CCA_UC 0x02 /* Uncached. */
131 #define MIPS_CCA_C 0x03 /* Cacheable, coherency unspecified. */
133 #if defined(CPU_R4000) || defined(CPU_R10000)
134 #define MIPS_CCA_CNC 0x03
135 #define MIPS_CCA_CCE 0x04
136 #define MIPS_CCA_CCEW 0x05
139 #define MIPS_CCA_CCUOW 0x06
143 #define MIPS_CCA_UA 0x07
146 #define MIPS_CCA_CACHED MIPS_CCA_CCEW
147 #endif /* defined(CPU_R4000) || defined(CPU_R10000) */
150 #define MIPS_CCA_CC 0x05 /* Cacheable Coherent. */
153 #if defined(CPU_MIPS74K)
154 #define MIPS_CCA_UNCACHED 0x02
155 #define MIPS_CCA_CACHED 0x03
159 * 1004K and 1074K cores, as well as interAptiv and proAptiv cores, support
160 * Cacheable Coherent CCAs 0x04 and 0x05, as well as Cacheable non-Coherent
161 * CCA 0x03 and Uncached Accelerated CCA 0x07
163 #if defined(CPU_MIPS1004K) || defined(CPU_MIPS1074K) || \
164 defined(CPU_INTERAPTIV) || defined(CPU_PROAPTIV)
165 #define MIPS_CCA_CNC 0x03
166 #define MIPS_CCA_CCE 0x04
167 #define MIPS_CCA_CCS 0x05
168 #define MIPS_CCA_UA 0x07
170 /* We use shared read CCA for CACHED CCA */
171 #define MIPS_CCA_CACHED MIPS_CCA_CCS
174 #if defined(CPU_XBURST)
175 #define MIPS_CCA_UA 0x01
176 #define MIPS_CCA_WC MIPS_CCA_UA
179 #ifndef MIPS_CCA_UNCACHED
180 #define MIPS_CCA_UNCACHED MIPS_CCA_UC
184 * If we don't know which cached mode to use and there is a cache coherent
185 * mode, use it. If there is not a cache coherent mode, use the required
188 #ifndef MIPS_CCA_CACHED
190 #define MIPS_CCA_CACHED MIPS_CCA_CC
192 #define MIPS_CCA_CACHED MIPS_CCA_C
196 #define MIPS_PHYS_TO_XKPHYS(cca,x) \
197 ((0x2ULL << 62) | ((unsigned long long)(cca) << 59) | (x))
198 #define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
199 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_CACHED) << 59) | (x))
200 #define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
201 ((0x2ULL << 62) | ((unsigned long long)(MIPS_CCA_UNCACHED) << 59) | (x))
203 #define MIPS_XKPHYS_TO_PHYS(x) ((uintptr_t)(x) & MIPS_XKPHYS_PHYS_MASK)
205 #define MIPS_XKPHYS_START 0x8000000000000000
206 #define MIPS_XKPHYS_END 0xbfffffffffffffff
207 #define MIPS_XUSEG_START 0x0000000000000000
208 #define MIPS_XUSEG_END 0x0000010000000000
209 #define MIPS_XKSEG_START 0xc000000000000000
210 #define MIPS_XKSEG_END 0xc00000ff80000000
211 #define MIPS_XKSEG_COMPAT32_START 0xffffffff80000000
212 #define MIPS_XKSEG_COMPAT32_END 0xffffffffffffffff
213 #define MIPS_XKSEG_TO_COMPAT32(va) ((va) & 0xffffffff)
216 #define MIPS_DIRECT_MAPPABLE(pa) 1
217 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_XKPHYS_CACHED(pa)
218 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_XKPHYS_UNCACHED(pa)
219 #define MIPS_DIRECT_TO_PHYS(va) MIPS_XKPHYS_TO_PHYS(va)
221 #define MIPS_DIRECT_MAPPABLE(pa) ((pa) < MIPS_KSEG0_LARGEST_PHYS)
222 #define MIPS_PHYS_TO_DIRECT(pa) MIPS_PHYS_TO_KSEG0(pa)
223 #define MIPS_PHYS_TO_DIRECT_UNCACHED(pa) MIPS_PHYS_TO_KSEG1(pa)
224 #define MIPS_DIRECT_TO_PHYS(va) MIPS_KSEG0_TO_PHYS(va)
227 /* CPU dependent mtc0 hazard hook */
228 #if defined(CPU_CNMIPS) || defined(CPU_RMI)
230 #elif defined(CPU_NLM)
231 #define COP0_SYNC .word 0xc0 /* ehb */
232 #elif defined(CPU_SB1)
233 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop; ssnop
234 #elif defined(CPU_MIPS24K) || defined(CPU_MIPS34K) || \
235 defined(CPU_MIPS74K) || defined(CPU_MIPS1004K) || \
236 defined(CPU_MIPS1074K) || defined(CPU_INTERAPTIV) || \
237 defined(CPU_PROAPTIV)
239 * According to MIPS32tm Architecture for Programmers, Vol.II, rev. 2.00:
240 * "As EHB becomes standard in MIPS implementations, the previous SSNOPs can be
241 * removed, leaving only the EHB".
242 * Also, all MIPS32 Release 2 implementations have the EHB instruction, which
243 * resolves all execution hazards. The same goes for MIPS32 Release 3.
245 #define COP0_SYNC .word 0xc0 /* ehb */
248 * Pick a reasonable default based on the "typical" spacing described in the
249 * "CP0 Hazards" chapter of MIPS Architecture Book Vol III.
251 #define COP0_SYNC ssnop; ssnop; ssnop; ssnop; .word 0xc0;
253 #define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
256 * The bits in the cause register.
258 * Bits common to r3000 and r4000:
260 * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
261 * MIPS_CR_COP_ERR Coprocessor error.
262 * MIPS_CR_IP Interrupt pending bits defined below.
263 * (same meaning as in CAUSE register).
264 * MIPS_CR_EXC_CODE The exception type (see exception codes below).
267 * r3k has 4 bits of execption type, r4k has 5 bits.
269 #define MIPS_CR_BR_DELAY 0x80000000
270 #define MIPS_CR_COP_ERR 0x30000000
271 #define MIPS_CR_EXC_CODE 0x0000007C /* five bits */
272 #define MIPS_CR_IP 0x0000FF00
273 #define MIPS_CR_EXC_CODE_SHIFT 2
274 #define MIPS_CR_COP_ERR_SHIFT 28
277 * The bits in the status register. All bits are active when set to 1.
279 * R3000 status register fields:
280 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
281 * MIPS_SR_TS TLB shutdown.
283 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
286 * r3k has cache control is via frobbing SR register bits, whereas the
287 * r4k cache control is via explicit instructions.
288 * r3k has a 3-entry stack of kernel/user bits, whereas the
289 * r4k has kernel/supervisor/user.
291 #define MIPS_SR_COP_USABILITY 0xf0000000
292 #define MIPS_SR_COP_0_BIT 0x10000000
293 #define MIPS_SR_COP_1_BIT 0x20000000
294 #define MIPS_SR_COP_2_BIT 0x40000000
296 /* r4k and r3k differences, see below */
298 #define MIPS_SR_MX 0x01000000 /* MIPS64 */
299 #define MIPS_SR_PX 0x00800000 /* MIPS64 */
300 #define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
301 #define MIPS_SR_TS 0x00200000
302 #define MIPS_SR_DE 0x00010000
304 #define MIPS_SR_INT_IE 0x00000001
305 /*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
306 #define MIPS_SR_INT_MASK 0x0000ff00
309 * R4000 status register bit definitons,
310 * where different from r2000/r3000.
312 #define MIPS_SR_XX 0x80000000
313 #define MIPS_SR_RP 0x08000000
314 #define MIPS_SR_FR 0x04000000
315 #define MIPS_SR_RE 0x02000000
317 #define MIPS_SR_DIAG_DL 0x01000000 /* QED 52xx */
318 #define MIPS_SR_DIAG_IL 0x00800000 /* QED 52xx */
319 #define MIPS_SR_SR 0x00100000
320 #define MIPS_SR_NMI 0x00080000 /* MIPS32/64 */
321 #define MIPS_SR_DIAG_CH 0x00040000
322 #define MIPS_SR_DIAG_CE 0x00020000
323 #define MIPS_SR_DIAG_PE 0x00010000
324 #define MIPS_SR_EIE 0x00010000 /* TX79/R5900 */
325 #define MIPS_SR_KX 0x00000080
326 #define MIPS_SR_SX 0x00000040
327 #define MIPS_SR_UX 0x00000020
328 #define MIPS_SR_KSU_MASK 0x00000018
329 #define MIPS_SR_KSU_USER 0x00000010
330 #define MIPS_SR_KSU_SUPER 0x00000008
331 #define MIPS_SR_KSU_KERNEL 0x00000000
332 #define MIPS_SR_ERL 0x00000004
333 #define MIPS_SR_EXL 0x00000002
336 * The interrupt masks.
337 * If a bit in the mask is 1 then the interrupt is enabled (or pending).
339 #define MIPS_INT_MASK 0xff00
340 #define MIPS_INT_MASK_5 0x8000
341 #define MIPS_INT_MASK_4 0x4000
342 #define MIPS_INT_MASK_3 0x2000
343 #define MIPS_INT_MASK_2 0x1000
344 #define MIPS_INT_MASK_1 0x0800
345 #define MIPS_INT_MASK_0 0x0400
346 #define MIPS_HARD_INT_MASK 0xfc00
347 #define MIPS_SOFT_INT_MASK_1 0x0200
348 #define MIPS_SOFT_INT_MASK_0 0x0100
351 * The bits in the MIPS3 config register.
353 * bit 0..5: R/W, Bit 6..31: R/O
356 /* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
357 #define MIPS_CONFIG_K0_MASK 0x00000007
360 * R/W Update on Store Conditional
361 * 0: Store Conditional uses coherency algorithm specified by TLB
362 * 1: Store Conditional uses cacheable coherent update on write
364 #define MIPS_CONFIG_CU 0x00000008
366 #define MIPS_CONFIG_DB 0x00000010 /* Primary D-cache line size */
367 #define MIPS_CONFIG_IB 0x00000020 /* Primary I-cache line size */
368 #define MIPS_CONFIG_CACHE_L1_LSIZE(config, bit) \
369 (((config) & (bit)) ? 32 : 16)
371 #define MIPS_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
372 #define MIPS_CONFIG_DC_SHIFT 6
373 #define MIPS_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
374 #define MIPS_CONFIG_IC_SHIFT 9
375 #define MIPS_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
377 /* Cache size mode indication: available only on Vr41xx CPUs */
378 #define MIPS_CONFIG_CS 0x00001000
379 #define MIPS_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
380 #define MIPS_CONFIG_CACHE_SIZE(config, mask, base, shift) \
381 ((base) << (((config) & (mask)) >> (shift)))
383 /* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
384 #define MIPS_CONFIG_SE 0x00001000
386 /* Block ordering: 0: sequential, 1: sub-block */
387 #define MIPS_CONFIG_EB 0x00002000
389 /* ECC mode - 0: ECC mode, 1: parity mode */
390 #define MIPS_CONFIG_EM 0x00004000
392 /* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
393 #define MIPS_CONFIG_BE 0x00008000
395 /* Dirty Shared coherency state - 0: enabled, 1: disabled */
396 #define MIPS_CONFIG_SM 0x00010000
398 /* Secondary Cache - 0: present, 1: not present */
399 #define MIPS_CONFIG_SC 0x00020000
401 /* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
402 #define MIPS_CONFIG_EW_MASK 0x000c0000
403 #define MIPS_CONFIG_EW_SHIFT 18
405 /* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
406 #define MIPS_CONFIG_SW 0x00100000
408 /* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
409 #define MIPS_CONFIG_SS 0x00200000
411 /* Secondary Cache line size */
412 #define MIPS_CONFIG_SB_MASK 0x00c00000
413 #define MIPS_CONFIG_SB_SHIFT 22
414 #define MIPS_CONFIG_CACHE_L2_LSIZE(config) \
415 (0x10 << (((config) & MIPS_CONFIG_SB_MASK) >> MIPS_CONFIG_SB_SHIFT))
417 /* Write back data rate */
418 #define MIPS_CONFIG_EP_MASK 0x0f000000
419 #define MIPS_CONFIG_EP_SHIFT 24
421 /* System clock ratio - this value is CPU dependent */
422 #define MIPS_CONFIG_EC_MASK 0x70000000
423 #define MIPS_CONFIG_EC_SHIFT 28
425 /* Master-Checker Mode - 1: enabled */
426 #define MIPS_CONFIG_CM 0x80000000
429 * The bits in the MIPS4 config register.
433 * Location of exception vectors.
435 * Common vectors: reset and UTLB miss.
437 #define MIPS_RESET_EXC_VEC ((intptr_t)(int32_t)0xBFC00000)
438 #define MIPS_UTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000000)
441 * MIPS-III exception vectors
443 #define MIPS_XTLB_MISS_EXC_VEC ((intptr_t)(int32_t)0x80000080)
444 #define MIPS_CACHE_ERR_EXC_VEC ((intptr_t)(int32_t)0x80000100)
445 #define MIPS_GEN_EXC_VEC ((intptr_t)(int32_t)0x80000180)
448 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
450 #define MIPS_INTR_EXC_VEC 0x80000200
453 * Coprocessor 0 registers:
455 * v--- width for mips I,III,32,64
456 * (3=32bit, 6=64bit, i=impl dep)
457 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
458 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
459 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
460 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
461 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
462 * 4/2 MIPS_COP_0_USERLOCAL ..36 UserLocal.
463 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
464 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
465 * 7 MIPS_COP_0_HWRENA ..33 rdHWR Enable.
466 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
467 * 9 MIPS_COP_0_COUNT .333 Count register.
468 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
469 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
470 * 12 MIPS_COP_0_STATUS 3333 Status register.
471 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
472 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
473 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
474 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
475 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
476 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
477 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
478 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 4.
479 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
480 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
481 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
482 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
483 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
484 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
485 * 25 MIPS_COP_0_PERFCNT ..36 Performance Counter register.
486 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
487 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
488 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
489 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
490 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
491 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
492 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
493 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
494 * 29/2 MIPS_COP_0_TAG_HI ..ii Cache TagHi register (data).
495 * 29/3 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (data).
496 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
497 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
500 /* Deal with inclusion from an assembly file. */
501 #if defined(_LOCORE) || defined(LOCORE)
508 #define MIPS_COP_0_TLB_INDEX _(0)
509 #define MIPS_COP_0_TLB_RANDOM _(1)
510 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
512 #define MIPS_COP_0_TLB_CONTEXT _(4)
513 /* $5 and $6 new with MIPS-III */
514 #define MIPS_COP_0_BAD_VADDR _(8)
515 #define MIPS_COP_0_TLB_HI _(10)
516 #define MIPS_COP_0_STATUS _(12)
517 #define MIPS_COP_0_CAUSE _(13)
518 #define MIPS_COP_0_EXC_PC _(14)
519 #define MIPS_COP_0_PRID _(15)
522 #define MIPS_COP_0_TLB_LO0 _(2)
523 #define MIPS_COP_0_TLB_LO1 _(3)
525 #define MIPS_COP_0_TLB_PG_MASK _(5)
526 #define MIPS_COP_0_TLB_WIRED _(6)
528 #define MIPS_COP_0_COUNT _(9)
529 #define MIPS_COP_0_COMPARE _(11)
531 #define MIPS_COP_0_XBURST_C12 _(12)
533 #define MIPS_COP_0_CONFIG _(16)
534 #define MIPS_COP_0_LLADDR _(17)
535 #define MIPS_COP_0_WATCH_LO _(18)
536 #define MIPS_COP_0_WATCH_HI _(19)
537 #define MIPS_COP_0_TLB_XCONTEXT _(20)
539 #define MIPS_COP_0_XBURST_MBOX _(20)
542 #define MIPS_COP_0_ECC _(26)
543 #define MIPS_COP_0_CACHE_ERR _(27)
544 #define MIPS_COP_0_TAG_LO _(28)
545 #define MIPS_COP_0_TAG_HI _(29)
546 #define MIPS_COP_0_ERROR_PC _(30)
549 #define MIPS_COP_0_USERLOCAL _(4) /* sel 2 is userlevel register */
550 #define MIPS_COP_0_HWRENA _(7)
551 #define MIPS_COP_0_DEBUG _(23)
552 #define MIPS_COP_0_DEPC _(24)
553 #define MIPS_COP_0_PERFCNT _(25)
554 #define MIPS_COP_0_DATA_LO _(28)
555 #define MIPS_COP_0_DATA_HI _(29)
556 #define MIPS_COP_0_DESAVE _(31)
558 /* MIPS32 Config register definitions */
559 #define MIPS_MMU_NONE 0x00 /* No MMU present */
560 #define MIPS_MMU_TLB 0x01 /* Standard TLB */
561 #define MIPS_MMU_BAT 0x02 /* Standard BAT */
562 #define MIPS_MMU_FIXED 0x03 /* Standard fixed mapping */
565 * Config Register Fields
566 * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.39)
568 #define MIPS_CONFIG0_M 0x80000000 /* Flag: Config1 is present. */
569 #define MIPS_CONFIG0_MT_MASK 0x00000380 /* bits 9..7 MMU Type */
570 #define MIPS_CONFIG0_MT_SHIFT 7
571 #define MIPS_CONFIG0_BE 0x00008000 /* data is big-endian */
572 #define MIPS_CONFIG0_VI 0x00000008 /* inst cache is virtual */
575 * Config1 Register Fields
576 * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9-1)
578 #define MIPS_CONFIG1_M 0x80000000 /* Flag: Config2 is present. */
579 #define MIPS_CONFIG1_TLBSZ_MASK 0x7E000000 /* bits 30..25 # tlb entries minus one */
580 #define MIPS_CONFIG1_TLBSZ_SHIFT 25
582 #define MIPS_CONFIG1_IS_MASK 0x01C00000 /* bits 24..22 icache sets per way */
583 #define MIPS_CONFIG1_IS_SHIFT 22
584 #define MIPS_CONFIG1_IL_MASK 0x00380000 /* bits 21..19 icache line size */
585 #define MIPS_CONFIG1_IL_SHIFT 19
586 #define MIPS_CONFIG1_IA_MASK 0x00070000 /* bits 18..16 icache associativity */
587 #define MIPS_CONFIG1_IA_SHIFT 16
588 #define MIPS_CONFIG1_DS_MASK 0x0000E000 /* bits 15..13 dcache sets per way */
589 #define MIPS_CONFIG1_DS_SHIFT 13
590 #define MIPS_CONFIG1_DL_MASK 0x00001C00 /* bits 12..10 dcache line size */
591 #define MIPS_CONFIG1_DL_SHIFT 10
592 #define MIPS_CONFIG1_DA_MASK 0x00000380 /* bits 9.. 7 dcache associativity */
593 #define MIPS_CONFIG1_DA_SHIFT 7
594 #define MIPS_CONFIG1_LOWBITS 0x0000007F
595 #define MIPS_CONFIG1_C2 0x00000040 /* Coprocessor 2 implemented */
596 #define MIPS_CONFIG1_MD 0x00000020 /* MDMX ASE implemented (MIPS64) */
597 #define MIPS_CONFIG1_PC 0x00000010 /* Performance counters implemented */
598 #define MIPS_CONFIG1_WR 0x00000008 /* Watch registers implemented */
599 #define MIPS_CONFIG1_CA 0x00000004 /* MIPS16e ISA implemented */
600 #define MIPS_CONFIG1_EP 0x00000002 /* EJTAG implemented */
601 #define MIPS_CONFIG1_FP 0x00000001 /* FPU implemented */
603 #define MIPS_CONFIG2_SA_SHIFT 0 /* Secondary cache associativity */
604 #define MIPS_CONFIG2_SA_MASK 0xf
605 #define MIPS_CONFIG2_SL_SHIFT 4 /* Secondary cache line size */
606 #define MIPS_CONFIG2_SL_MASK 0xf
607 #define MIPS_CONFIG2_SS_SHIFT 8 /* Secondary cache sets per way */
608 #define MIPS_CONFIG2_SS_MASK 0xf
610 #define MIPS_CONFIG3_CMGCR_MASK (1 << 29) /* Coherence manager present */
613 * Config2 Register Fields
614 * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.40)
616 #define MIPS_CONFIG2_M 0x80000000 /* Flag: Config3 is present. */
619 * Config3 Register Fields
620 * (See "MIPS Architecture for Programmers Volume III", MD00091, Table 9.41)
622 #define MIPS_CONFIG3_M 0x80000000 /* Flag: Config4 is present */
623 #define MIPS_CONFIG3_ULR 0x00002000 /* UserLocal reg implemented */
625 #define MIPS_CONFIG4_MMUSIZEEXT 0x000000FF /* bits 7.. 0 MMU Size Extension */
626 #define MIPS_CONFIG4_MMUEXTDEF 0x0000C000 /* bits 15.14 MMU Extension Definition */
627 #define MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT 0x00004000 /* This values denotes CONFIG4 bits */
630 * Values for the code field in a break instruction.
632 #define MIPS_BREAK_INSTR 0x0000000d
633 #define MIPS_BREAK_VAL_MASK 0x03ff0000
634 #define MIPS_BREAK_VAL_SHIFT 16
635 #define MIPS_BREAK_KDB_VAL 512
636 #define MIPS_BREAK_SSTEP_VAL 513
637 #define MIPS_BREAK_BRKPT_VAL 514
638 #define MIPS_BREAK_SOVER_VAL 515
639 #define MIPS_BREAK_DDB_VAL 516
640 #define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
641 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
642 #define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
643 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
644 #define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
645 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
646 #define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
647 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
648 #define MIPS_BREAK_DDB (MIPS_BREAK_INSTR | \
649 (MIPS_BREAK_DDB_VAL << MIPS_BREAK_VAL_SHIFT))
652 * Mininum and maximum cache sizes.
654 #define MIPS_MIN_CACHE_SIZE (16 * 1024)
655 #define MIPS_MAX_CACHE_SIZE (256 * 1024)
656 #define MIPS_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
659 * The floating point version and status registers.
661 #define MIPS_FPU_ID $0
662 #define MIPS_FPU_CSR $31
665 * The floating point coprocessor status register bits.
667 #define MIPS_FPU_ROUNDING_BITS 0x00000003
668 #define MIPS_FPU_ROUND_RN 0x00000000
669 #define MIPS_FPU_ROUND_RZ 0x00000001
670 #define MIPS_FPU_ROUND_RP 0x00000002
671 #define MIPS_FPU_ROUND_RM 0x00000003
672 #define MIPS_FPU_STICKY_BITS 0x0000007c
673 #define MIPS_FPU_STICKY_INEXACT 0x00000004
674 #define MIPS_FPU_STICKY_UNDERFLOW 0x00000008
675 #define MIPS_FPU_STICKY_OVERFLOW 0x00000010
676 #define MIPS_FPU_STICKY_DIV0 0x00000020
677 #define MIPS_FPU_STICKY_INVALID 0x00000040
678 #define MIPS_FPU_ENABLE_BITS 0x00000f80
679 #define MIPS_FPU_ENABLE_INEXACT 0x00000080
680 #define MIPS_FPU_ENABLE_UNDERFLOW 0x00000100
681 #define MIPS_FPU_ENABLE_OVERFLOW 0x00000200
682 #define MIPS_FPU_ENABLE_DIV0 0x00000400
683 #define MIPS_FPU_ENABLE_INVALID 0x00000800
684 #define MIPS_FPU_EXCEPTION_BITS 0x0003f000
685 #define MIPS_FPU_EXCEPTION_INEXACT 0x00001000
686 #define MIPS_FPU_EXCEPTION_UNDERFLOW 0x00002000
687 #define MIPS_FPU_EXCEPTION_OVERFLOW 0x00004000
688 #define MIPS_FPU_EXCEPTION_DIV0 0x00008000
689 #define MIPS_FPU_EXCEPTION_INVALID 0x00010000
690 #define MIPS_FPU_EXCEPTION_UNIMPL 0x00020000
691 #define MIPS_FPU_COND_BIT 0x00800000
692 #define MIPS_FPU_FLUSH_BIT 0x01000000 /* r4k, MBZ on r3k */
693 #define MIPS_FPC_MBZ_BITS 0xfe7c0000
697 * Constants to determine if have a floating point instruction.
699 #define MIPS_OPCODE_SHIFT 26
700 #define MIPS_OPCODE_C1 0x11
702 /* Coherence manager constants */
703 #define MIPS_CMGCRB_BASE 11
704 #define MIPS_CMGCRF_BASE (~((1 << MIPS_CMGCRB_BASE) - 1))
707 * Bits defined for for the HWREna (CP0 register 7, select 0).
709 #define MIPS_HWRENA_CPUNUM (1<<0) /* CPU number program is running on */
710 #define MIPS_HWRENA_SYNCI_STEP (1<<1) /* Address step sized used with SYNCI */
711 #define MIPS_HWRENA_CC (1<<2) /* Hi Res cycle counter */
712 #define MIPS_HWRENA_CCRES (1<<3) /* Cycle counter resolution */
713 #define MIPS_HWRENA_UL (1<<29) /* UserLocal Register */
714 #define MIPS_HWRENA_IMPL30 (1<<30) /* Implementation-dependent 30 */
715 #define MIPS_HWRENA_IMPL31 (1<<31) /* Implementation-dependent 31 */
717 #endif /* _MIPS_CPUREGS_H_ */