2 * Copyright 2015 Alexander Kabaev <kan@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Ingenic JZ4780 OTG PHY clock driver.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
40 #include <sys/mutex.h>
41 #include <sys/resource.h>
43 #include <machine/bus.h>
45 #include <mips/ingenic/jz4780_clk.h>
46 #include <mips/ingenic/jz4780_regs.h>
48 /* JZ4780 OTG PHY clock */
49 static int jz4780_clk_otg_init(struct clknode *clk, device_t dev);
50 static int jz4780_clk_otg_recalc_freq(struct clknode *clk, uint64_t *freq);
51 static int jz4780_clk_otg_set_freq(struct clknode *clk, uint64_t fin,
52 uint64_t *fout, int flags, int *stop);
54 struct jz4780_clk_otg_sc {
56 struct resource *clk_res;
60 * JZ4780 OTG PHY clock methods
62 static clknode_method_t jz4780_clk_otg_methods[] = {
63 CLKNODEMETHOD(clknode_init, jz4780_clk_otg_init),
64 CLKNODEMETHOD(clknode_recalc_freq, jz4780_clk_otg_recalc_freq),
65 CLKNODEMETHOD(clknode_set_freq, jz4780_clk_otg_set_freq),
69 DEFINE_CLASS_1(jz4780_clk_pll, jz4780_clk_otg_class, jz4780_clk_otg_methods,
70 sizeof(struct jz4780_clk_otg_sc), clknode_class);
73 jz4780_clk_otg_init(struct clknode *clk, device_t dev)
75 struct jz4780_clk_otg_sc *sc;
78 sc = clknode_get_softc(clk);
80 /* Force the use fo the core clock */
81 reg = CLK_RD_4(sc, JZ_USBPCR1);
83 reg |= PCR_REFCLK_CORE;
84 CLK_WR_4(sc, JZ_USBPCR1, reg);
87 clknode_init_parent_idx(clk, 0);
95 { PCR_CLK_12, 12000000 },
96 { PCR_CLK_192, 19200000 },
97 { PCR_CLK_24, 24000000 },
98 { PCR_CLK_48, 48000000 }
102 jz4780_clk_otg_recalc_freq(struct clknode *clk, uint64_t *freq)
104 struct jz4780_clk_otg_sc *sc;
108 sc = clknode_get_softc(clk);
109 reg = CLK_RD_4(sc, JZ_USBPCR1);
112 for (i = 0; i < nitems(otg_div_table); i++)
113 if (otg_div_table[i].div_val == reg)
114 *freq = otg_div_table[i].freq;
119 jz4780_clk_otg_set_freq(struct clknode *clk, uint64_t fin,
120 uint64_t *fout, int flags, int *stop)
122 struct jz4780_clk_otg_sc *sc;
126 sc = clknode_get_softc(clk);
128 for (i = 0; i < nitems(otg_div_table) - 1; i++) {
129 if (*fout < (otg_div_table[i].freq + otg_div_table[i + 1].freq) / 2)
133 *fout = otg_div_table[i].freq;
136 if (flags & CLK_SET_DRYRUN)
140 reg = CLK_RD_4(sc, JZ_USBPCR1);
141 /* Set the calculated values */
143 reg |= otg_div_table[i].div_val;
144 /* Initiate the change */
145 CLK_WR_4(sc, JZ_USBPCR1, reg);
151 int jz4780_clk_otg_register(struct clkdom *clkdom,
152 struct clknode_init_def *clkdef, struct mtx *dev_mtx,
153 struct resource *mem_res)
156 struct jz4780_clk_otg_sc *sc;
158 clk = clknode_create(clkdom, &jz4780_clk_otg_class, clkdef);
162 sc = clknode_get_softc(clk);
163 sc->clk_mtx = dev_mtx;
164 sc->clk_res = mem_res;
165 clknode_register(clkdom, clk);