2 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 #define CODEC_RGADW 0x00 /* Address, data in and write command */
34 #define RGADW_ICRST (1 << 31) /* Reset internal CODEC */
35 #define RGADW_RGWR (1 << 16) /* Issue a write command to CODEC */
36 #define RGADW_RGADDR_S 8 /* CODEC register's address. */
37 #define RGADW_RGADDR_M (0x7f << RGADW_RGADDR_S)
38 #define RGADW_RGDIN_S 0 /* CODEC register data to write */
39 #define RGADW_RGDIN_M (0xff << RGADW_RGDIN_S)
40 #define CODEC_RGDATA 0x04 /* The data read out */
42 #define SR 0x00 /* Status Register */
43 #define SR2 0x01 /* Status Register 2 */
44 #define MR 0x07 /* Mode status register */
45 #define AICR_DAC 0x08 /* DAC Audio Interface Control Register */
46 #define DAC_ADWL_S 6 /* Audio Data Word Length for DAC path. */
47 #define DAC_ADWL_M (0x3 << DAC_ADWL_S)
48 #define DAC_ADWL_16 (0 << DAC_ADWL_S)
49 #define AICR_DAC_SB (1 << 4) /* DAC audio interface in power-down mode */
51 #define AUDIOIF_M (0x3 << AUDIOIF_S)
52 #define AUDIOIF_I2S 0x3 /* I2S interface */
53 #define AUDIOIF_DSP 0x2 /* DSP interface */
54 #define AUDIOIF_LJ 0x1 /* Left-justified interface */
55 #define AUDIOIF_P 0x0 /* Parallel interface */
56 #define AICR_ADC 0x09 /* ADC Audio Interface Control Register */
57 #define CR_LO 0x0B /* Differential line-out Control Register */
58 #define CR_HP 0x0D /* HeadPhone Control Register */
59 #define HP_MUTE (1 << 7) /* no signal on headphone outputs */
60 #define HP_SB (1 << 4) /* power-down */
61 #define CR_DMIC 0x10 /* Digital Microphone register */
62 #define CR_MIC1 0x11 /* Microphone1 Control register */
63 #define CR_MIC2 0x12 /* Microphone2 Control register */
64 #define CR_LI1 0x13 /* Control Register for line1 inputs */
65 #define CR_LI2 0x14 /* Control Register for line2 inputs */
66 #define CR_DAC 0x17 /* DAC Control Register */
67 #define DAC_MUTE (1 << 7) /* puts the DAC in soft mute mode */
68 #define DAC_SB (1 << 4) /* power-down */
69 #define CR_ADC 0x18 /* ADC Control Register */
70 #define CR_MIX 0x19 /* Digital Mixer Control Register */
71 #define DR_MIX 0x1A /* Digital Mixer Data Register */
72 #define CR_VIC 0x1B /* Control Register for the ViC */
73 #define VIC_SB_SLEEP (1 << 1) /* sleep mode */
74 #define VIC_SB (1 << 0) /* complete power-down */
75 #define CR_CK 0x1C /* Clock Control Register */
76 #define FCR_DAC 0x1D /* DAC Frequency Control Register */
77 #define FCR_DAC_96 10 /* 96 kHz. */
78 #define FCR_ADC 0x20 /* ADC Frequency Control Register */
79 #define CR_TIMER_MSB 0x21 /* MSB of programmable counter */
80 #define CR_TIMER_LSB 0x22 /* LSB of programmable counter */
81 #define ICR 0x23 /* Interrupt Control Register */
82 #define IMR 0x24 /* Interrupt Mask Register */
83 #define IFR 0x25 /* Interrupt Flag Register */
84 #define IMR2 0x26 /* Interrupt Mask Register 2 */
85 #define IFR2 0x27 /* Interrupt Flag Register 2 */
86 #define GCR_HPL 0x28 /* Left channel headphone Control Gain Register */
87 #define GCR_HPR 0x29 /* Right channel headphone Control Gain Register */
88 #define GCR_LIBYL 0x2A /* Left channel bypass line Control Gain Register */
89 #define GCR_LIBYR 0x2B /* Right channel bypass line Control Gain Register */
90 #define GCR_DACL 0x2C /* Left channel DAC Gain Control Register */
91 #define GCR_DACR 0x2D /* Right channel DAC Gain Control Register */
92 #define GCR_MIC1 0x2E /* Microphone 1 Gain Control Register */
93 #define GCR_MIC2 0x2F /* Microphone 2 Gain Control Register */
94 #define GCR_ADCL 0x30 /* Left ADC Gain Control Register */
95 #define GCR_ADCR 0x31 /* Right ADC Gain Control Register */
96 #define GCR_MIXDACL 0x34 /* DAC Digital Mixer Control Register */
97 #define GCR_MIXDACR 0x35 /* DAC Digital Mixer Control Register */
98 #define GCR_MIXADCL 0x36 /* ADC Digital Mixer Control Register */
99 #define GCR_MIXADCR 0x37 /* ADC Digital Mixer Control Register */
100 #define CR_ADC_AGC 0x3A /* Automatic Gain Control Register */
101 #define DR_ADC_AGC 0x3B /* Automatic Gain Control Data Register */