2 * Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/systm.h>
33 #include <sys/kernel.h>
35 #include <sys/malloc.h>
36 #include <sys/module.h>
37 #include <sys/mutex.h>
38 #include <sys/resource.h>
40 #include <sys/sysctl.h>
42 #include <machine/bus.h>
44 #include <dev/extres/clk/clk.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
49 #include <dev/mmc/bridge.h>
50 #include <dev/mmc/mmcreg.h>
51 #include <dev/mmc/mmcbrvar.h>
53 #include <mips/ingenic/jz4780_regs.h>
57 #define JZ_MSC_MEMRES 0
58 #define JZ_MSC_IRQRES 1
59 #define JZ_MSC_RESSZ 2
60 #define JZ_MSC_DMA_SEGS 128
61 #define JZ_MSC_DMA_MAX_SIZE MAXPHYS
63 #define JZ_MSC_INT_ERR_BITS (JZ_INT_CRC_RES_ERR | JZ_INT_CRC_READ_ERR | \
64 JZ_INT_CRC_WRITE_ERR | JZ_INT_TIMEOUT_RES | \
66 static int jz4780_mmc_pio_mode = 0;
68 TUNABLE_INT("hw.jz.mmc.pio_mode", &jz4780_mmc_pio_mode);
70 struct jz4780_mmc_dma_desc {
77 struct jz4780_mmc_softc {
78 bus_space_handle_t sc_bsh;
79 bus_space_tag_t sc_bst;
85 struct callout sc_timeoutc;
86 struct mmc_host sc_host;
87 struct mmc_request * sc_req;
89 struct resource * sc_res[JZ_MSC_RESSZ];
90 uint32_t sc_intr_seen;
91 uint32_t sc_intr_mask;
92 uint32_t sc_intr_wait;
96 /* Fields required for DMA access. */
97 bus_addr_t sc_dma_desc_phys;
98 bus_dmamap_t sc_dma_map;
99 bus_dma_tag_t sc_dma_tag;
101 bus_dmamap_t sc_dma_buf_map;
102 bus_dma_tag_t sc_dma_buf_tag;
108 static struct resource_spec jz4780_mmc_res_spec[] = {
109 { SYS_RES_MEMORY, 0, RF_ACTIVE },
110 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
114 static int jz4780_mmc_probe(device_t);
115 static int jz4780_mmc_attach(device_t);
116 static int jz4780_mmc_detach(device_t);
117 static int jz4780_mmc_setup_dma(struct jz4780_mmc_softc *);
118 static int jz4780_mmc_reset(struct jz4780_mmc_softc *);
119 static void jz4780_mmc_intr(void *);
120 static int jz4780_mmc_enable_clock(struct jz4780_mmc_softc *);
121 static int jz4780_mmc_config_clock(struct jz4780_mmc_softc *, uint32_t);
123 static int jz4780_mmc_update_ios(device_t, device_t);
124 static int jz4780_mmc_request(device_t, device_t, struct mmc_request *);
125 static int jz4780_mmc_get_ro(device_t, device_t);
126 static int jz4780_mmc_acquire_host(device_t, device_t);
127 static int jz4780_mmc_release_host(device_t, device_t);
129 #define JZ_MMC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
130 #define JZ_MMC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
131 #define JZ_MMC_READ_2(_sc, _reg) \
132 bus_space_read_2((_sc)->sc_bst, (_sc)->sc_bsh, _reg)
133 #define JZ_MMC_WRITE_2(_sc, _reg, _value) \
134 bus_space_write_2((_sc)->sc_bst, (_sc)->sc_bsh, _reg, _value)
135 #define JZ_MMC_READ_4(_sc, _reg) \
136 bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _reg)
137 #define JZ_MMC_WRITE_4(_sc, _reg, _value) \
138 bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _reg, _value)
141 jz4780_mmc_probe(device_t dev)
144 if (!ofw_bus_status_okay(dev))
146 if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-mmc"))
148 if (device_get_unit(dev) > 0) /* XXXKAN */
150 device_set_desc(dev, "Ingenic JZ4780 Integrated MMC/SD controller");
152 return (BUS_PROBE_DEFAULT);
156 jz4780_mmc_attach(device_t dev)
158 struct jz4780_mmc_softc *sc;
159 struct sysctl_ctx_list *ctx;
160 struct sysctl_oid_list *tree;
166 sc = device_get_softc(dev);
169 if (bus_alloc_resources(dev, jz4780_mmc_res_spec, sc->sc_res) != 0) {
170 device_printf(dev, "cannot allocate device resources\n");
173 sc->sc_bst = rman_get_bustag(sc->sc_res[JZ_MSC_MEMRES]);
174 sc->sc_bsh = rman_get_bushandle(sc->sc_res[JZ_MSC_MEMRES]);
175 if (bus_setup_intr(dev, sc->sc_res[JZ_MSC_IRQRES],
176 INTR_TYPE_MISC | INTR_MPSAFE, NULL, jz4780_mmc_intr, sc,
178 bus_release_resources(dev, jz4780_mmc_res_spec, sc->sc_res);
179 device_printf(dev, "cannot setup interrupt handler\n");
183 ctx = device_get_sysctl_ctx(dev);
184 tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
185 SYSCTL_ADD_INT(ctx, tree, OID_AUTO, "req_timeout", CTLFLAG_RW,
186 &sc->sc_timeout, 0, "Request timeout in seconds");
187 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), "jz4780_mmc",
189 callout_init_mtx(&sc->sc_timeoutc, &sc->sc_mtx, 0);
191 /* Reset controller. */
192 if (jz4780_mmc_reset(sc) != 0) {
193 device_printf(dev, "cannot reset the controller\n");
196 if (jz4780_mmc_pio_mode == 0 && jz4780_mmc_setup_dma(sc) != 0) {
197 device_printf(sc->sc_dev, "Couldn't setup DMA!\n");
198 jz4780_mmc_pio_mode = 1;
201 device_printf(sc->sc_dev, "DMA status: %s\n",
202 jz4780_mmc_pio_mode ? "disabled" : "enabled");
204 node = ofw_bus_get_node(dev);
205 /* Determine max operating frequency */
206 sc->sc_host.f_max = 24000000;
207 len = OF_getencprop(node, "max-frequency", &prop, sizeof(prop));
208 if (len / sizeof(prop) == 1)
209 sc->sc_host.f_max = prop;
210 sc->sc_host.f_min = sc->sc_host.f_max / 128;
212 sc->sc_host.host_ocr = MMC_OCR_320_330 | MMC_OCR_330_340;
213 sc->sc_host.caps = MMC_CAP_HSPEED;
214 sc->sc_host.mode = mode_sd;
216 * Check for bus-width property, default to both 4 and 8 bit
217 * if no bus width is specified.
219 len = OF_getencprop(node, "bus-width", &prop, sizeof(prop));
220 if (len / sizeof(prop) != 1)
221 sc->sc_host.caps |= MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA;
223 sc->sc_host.caps |= MMC_CAP_8_BIT_DATA;
225 sc->sc_host.caps |= MMC_CAP_4_BIT_DATA;
226 /* Activate the module clock. */
227 if (jz4780_mmc_enable_clock(sc) != 0) {
228 device_printf(dev, "cannot activate mmc clock\n");
232 child = device_add_child(dev, "mmc", -1);
234 device_printf(dev, "attaching MMC bus failed!\n");
237 if (device_probe_and_attach(child) != 0) {
238 device_printf(dev, "attaching MMC child failed!\n");
239 device_delete_child(dev, child);
246 callout_drain(&sc->sc_timeoutc);
247 mtx_destroy(&sc->sc_mtx);
248 bus_teardown_intr(dev, sc->sc_res[JZ_MSC_IRQRES], sc->sc_intrhand);
249 bus_release_resources(dev, jz4780_mmc_res_spec, sc->sc_res);
250 if (sc->sc_clk != NULL)
251 clk_release(sc->sc_clk);
256 jz4780_mmc_detach(device_t dev)
263 jz4780_mmc_enable_clock(struct jz4780_mmc_softc *sc)
267 err = clk_get_by_ofw_name(sc->sc_dev, 0, "mmc", &sc->sc_clk);
269 err = clk_enable(sc->sc_clk);
271 err = clk_set_freq(sc->sc_clk, sc->sc_host.f_max, 0);
273 clk_release(sc->sc_clk);
278 jz4780_mmc_dma_desc_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
280 struct jz4780_mmc_softc *sc;
282 sc = (struct jz4780_mmc_softc *)arg;
284 sc->sc_dma_map_err = err;
287 sc->sc_dma_desc_phys = segs[0].ds_addr;
291 jz4780_mmc_setup_dma(struct jz4780_mmc_softc *sc)
293 int dma_desc_size, error;
295 /* Allocate the DMA descriptor memory. */
296 dma_desc_size = sizeof(struct jz4780_mmc_dma_desc) * JZ_MSC_DMA_SEGS;
297 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
298 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
299 dma_desc_size, 1, dma_desc_size, 0, NULL, NULL, &sc->sc_dma_tag);
302 error = bus_dmamem_alloc(sc->sc_dma_tag, &sc->sc_dma_desc,
303 BUS_DMA_WAITOK | BUS_DMA_ZERO, &sc->sc_dma_map);
307 error = bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map,
308 sc->sc_dma_desc, dma_desc_size, jz4780_mmc_dma_desc_cb, sc, 0);
311 if (sc->sc_dma_map_err)
312 return (sc->sc_dma_map_err);
314 /* Create the DMA map for data transfers. */
315 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
316 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL,
317 JZ_MSC_DMA_MAX_SIZE * JZ_MSC_DMA_SEGS, JZ_MSC_DMA_SEGS,
318 JZ_MSC_DMA_MAX_SIZE, BUS_DMA_ALLOCNOW, NULL, NULL,
319 &sc->sc_dma_buf_tag);
322 error = bus_dmamap_create(sc->sc_dma_buf_tag, 0,
323 &sc->sc_dma_buf_map);
331 jz4780_mmc_dma_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int err)
333 struct jz4780_mmc_dma_desc *dma_desc;
334 struct jz4780_mmc_softc *sc;
335 uint32_t dma_desc_phys;
338 sc = (struct jz4780_mmc_softc *)arg;
339 sc->sc_dma_map_err = err;
340 dma_desc = sc->sc_dma_desc;
341 dma_desc_phys = sc->sc_dma_desc_phys;
343 /* Note nsegs is guaranteed to be zero if err is non-zero. */
344 for (i = 0; i < nsegs; i++) {
345 dma_desc[i].dma_phys = segs[i].ds_addr;
346 dma_desc[i].dma_len = segs[i].ds_len;
347 if (i < (nsegs - 1)) {
348 dma_desc_phys += sizeof(struct jz4780_mmc_dma_desc);
349 dma_desc[i].dma_next = dma_desc_phys;
350 dma_desc[i].dma_cmd = (i << 16) | JZ_DMA_LINK;
352 dma_desc[i].dma_next = 0;
353 dma_desc[i].dma_cmd = (i << 16) | JZ_DMA_ENDI;
356 device_printf(sc->sc_dev, "%d: desc %#x phys %#x len %d next %#x cmd %#x\n",
357 i, dma_desc_phys - sizeof(struct jz4780_mmc_dma_desc),
358 dma_desc[i].dma_phys, dma_desc[i].dma_len,
359 dma_desc[i].dma_next, dma_desc[i].dma_cmd);
365 jz4780_mmc_prepare_dma(struct jz4780_mmc_softc *sc)
367 bus_dmasync_op_t sync_op;
369 struct mmc_command *cmd;
372 cmd = sc->sc_req->cmd;
373 if (cmd->data->len > JZ_MSC_DMA_MAX_SIZE * JZ_MSC_DMA_SEGS)
375 error = bus_dmamap_load(sc->sc_dma_buf_tag, sc->sc_dma_buf_map,
376 cmd->data->data, cmd->data->len, jz4780_mmc_dma_cb, sc,
380 if (sc->sc_dma_map_err)
381 return (sc->sc_dma_map_err);
383 sc->sc_dma_inuse = 1;
384 if (cmd->data->flags & MMC_DATA_WRITE)
385 sync_op = BUS_DMASYNC_PREWRITE;
387 sync_op = BUS_DMASYNC_PREREAD;
388 bus_dmamap_sync(sc->sc_dma_buf_tag, sc->sc_dma_buf_map, sync_op);
389 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, BUS_DMASYNC_PREWRITE);
391 /* Configure default DMA parameters */
392 sc->sc_dma_ctl = JZ_MODE_SEL | JZ_INCR_64 | JZ_DMAEN;
394 /* Enable unaligned buffer handling */
395 off = (uintptr_t)cmd->data->data & 3;
397 sc->sc_dma_ctl |= (off << JZ_AOFST_S) | JZ_ALIGNEN;
402 jz4780_mmc_start_dma(struct jz4780_mmc_softc *sc)
405 /* Set the address of the first descriptor */
406 JZ_MMC_WRITE_4(sc, JZ_MSC_DMANDA, sc->sc_dma_desc_phys);
407 /* Enable and start the dma engine */
408 JZ_MMC_WRITE_4(sc, JZ_MSC_DMAC, sc->sc_dma_ctl);
412 jz4780_mmc_reset(struct jz4780_mmc_softc *sc)
418 reg = JZ_MMC_READ_4(sc, JZ_MSC_CTRL);
419 reg &= ~(JZ_CLOCK_CTRL_M);
420 reg |= JZ_CLOCK_STOP;
421 JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, reg);
424 while (--timeout > 0) {
425 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_CLK_EN) == 0)
430 device_printf(sc->sc_dev, "Failed to stop clk.\n");
435 reg = JZ_MMC_READ_4(sc, JZ_MSC_CTRL);
437 JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, reg);
440 while (--timeout > 0) {
441 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_IS_RESETTING) == 0)
448 * X1000 never clears reseting bit.
453 /* Set the timeouts. */
454 JZ_MMC_WRITE_4(sc, JZ_MSC_RESTO, 0xffff);
455 JZ_MMC_WRITE_4(sc, JZ_MSC_RDTO, 0xffffffff);
457 /* Mask all interrupt initially */
458 JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, 0xffffffff);
459 /* Clear pending interrupts. */
460 JZ_MMC_WRITE_4(sc, JZ_MSC_IFLG, 0xffffffff);
462 /* Remember interrupts we always want */
463 sc->sc_intr_mask = JZ_MSC_INT_ERR_BITS;
469 jz4780_mmc_req_done(struct jz4780_mmc_softc *sc)
471 struct mmc_command *cmd;
472 struct mmc_request *req;
473 bus_dmasync_op_t sync_op;
475 cmd = sc->sc_req->cmd;
476 /* Reset the controller in case of errors */
477 if (cmd->error != MMC_ERR_NONE)
478 jz4780_mmc_reset(sc);
479 /* Unmap DMA if necessary */
480 if (sc->sc_dma_inuse == 1) {
481 if (cmd->data->flags & MMC_DATA_WRITE)
482 sync_op = BUS_DMASYNC_POSTWRITE;
484 sync_op = BUS_DMASYNC_POSTREAD;
485 bus_dmamap_sync(sc->sc_dma_buf_tag, sc->sc_dma_buf_map,
487 bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
488 BUS_DMASYNC_POSTWRITE);
489 bus_dmamap_unload(sc->sc_dma_buf_tag, sc->sc_dma_buf_map);
492 callout_stop(&sc->sc_timeoutc);
495 sc->sc_dma_inuse = 0;
496 sc->sc_dma_map_err = 0;
497 sc->sc_intr_wait = 0;
498 sc->sc_intr_seen = 0;
503 jz4780_mmc_read_response(struct jz4780_mmc_softc *sc)
505 struct mmc_command *cmd;
508 cmd = sc->sc_req->cmd;
509 if (cmd->flags & MMC_RSP_PRESENT) {
510 if (cmd->flags & MMC_RSP_136) {
513 val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
514 for (i = 0; i < 4; i++) {
515 cmd->resp[i] = val << 24;
516 val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
517 cmd->resp[i] |= val << 8;
518 val = JZ_MMC_READ_2(sc, JZ_MSC_RES);
519 cmd->resp[i] |= val >> 8;
522 cmd->resp[0] = JZ_MMC_READ_2(sc, JZ_MSC_RES) << 24;
523 cmd->resp[0] |= JZ_MMC_READ_2(sc, JZ_MSC_RES) << 8;
524 cmd->resp[0] |= JZ_MMC_READ_2(sc, JZ_MSC_RES) & 0xff;
530 jz4780_mmc_req_ok(struct jz4780_mmc_softc *sc)
532 struct mmc_command *cmd;
534 cmd = sc->sc_req->cmd;
535 /* All data has been transferred ? */
536 if (cmd->data != NULL && (sc->sc_resid << 2) < cmd->data->len)
537 cmd->error = MMC_ERR_FAILED;
538 jz4780_mmc_req_done(sc);
542 jz4780_mmc_timeout(void *arg)
544 struct jz4780_mmc_softc *sc;
546 sc = (struct jz4780_mmc_softc *)arg;
547 if (sc->sc_req != NULL) {
548 device_printf(sc->sc_dev, "controller timeout, rint %#x stat %#x\n",
549 JZ_MMC_READ_4(sc, JZ_MSC_IFLG), JZ_MMC_READ_4(sc, JZ_MSC_STAT));
550 sc->sc_req->cmd->error = MMC_ERR_TIMEOUT;
551 jz4780_mmc_req_done(sc);
553 device_printf(sc->sc_dev,
554 "Spurious timeout - no active request\n");
558 jz4780_mmc_pio_transfer(struct jz4780_mmc_softc *sc, struct mmc_data *data)
563 buf = (uint32_t *)data->data;
564 write = (data->flags & MMC_DATA_WRITE) ? 1 : 0;
565 mask = write ? JZ_DATA_FIFO_FULL : JZ_DATA_FIFO_EMPTY;
566 for (i = sc->sc_resid; i < (data->len >> 2); i++) {
567 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & mask))
570 JZ_MMC_WRITE_4(sc, JZ_MSC_TXFIFO, buf[i]);
572 buf[i] = JZ_MMC_READ_4(sc, JZ_MSC_RXFIFO);
573 sc->sc_resid = i + 1;
576 /* Done with pio transfer, shut FIFO interrupts down */
577 mask = JZ_MMC_READ_4(sc, JZ_MSC_IMASK);
578 mask |= (JZ_INT_TXFIFO_WR_REQ | JZ_INT_RXFIFO_RD_REQ);
579 JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, mask);
584 jz4780_mmc_intr(void *arg)
586 struct jz4780_mmc_softc *sc;
587 struct mmc_data *data;
590 sc = (struct jz4780_mmc_softc *)arg;
592 rint = JZ_MMC_READ_4(sc, JZ_MSC_IFLG);
593 #if defined(JZ_MMC_DEBUG)
594 device_printf(sc->sc_dev, "rint: %#x, stat: %#x\n",
595 rint, JZ_MMC_READ_4(sc, JZ_MSC_STAT));
596 if (sc->sc_dma_inuse == 1 && (sc->sc_intr_seen & JZ_INT_DMAEND) == 0)
597 device_printf(sc->sc_dev, "\tdmada %#x dmanext %#x dmac %#x"
598 " dmalen %d dmacmd %#x\n",
599 JZ_MMC_READ_4(sc, JZ_MSC_DMADA),
600 JZ_MMC_READ_4(sc, JZ_MSC_DMANDA),
601 JZ_MMC_READ_4(sc, JZ_MSC_DMAC),
602 JZ_MMC_READ_4(sc, JZ_MSC_DMALEN),
603 JZ_MMC_READ_4(sc, JZ_MSC_DMACMD));
605 if (sc->sc_req == NULL) {
606 device_printf(sc->sc_dev,
607 "Spurious interrupt - no active request, rint: 0x%08X\n",
611 if (rint & JZ_MSC_INT_ERR_BITS) {
612 #if defined(JZ_MMC_DEBUG)
613 device_printf(sc->sc_dev, "controller error, rint %#x stat %#x\n",
614 rint, JZ_MMC_READ_4(sc, JZ_MSC_STAT));
616 if (rint & (JZ_INT_TIMEOUT_RES | JZ_INT_TIMEOUT_READ))
617 sc->sc_req->cmd->error = MMC_ERR_TIMEOUT;
619 sc->sc_req->cmd->error = MMC_ERR_FAILED;
620 jz4780_mmc_req_done(sc);
623 data = sc->sc_req->cmd->data;
624 /* Check for command response */
625 if (rint & JZ_INT_END_CMD_RES) {
626 jz4780_mmc_read_response(sc);
627 if (sc->sc_dma_inuse == 1)
628 jz4780_mmc_start_dma(sc);
631 if (sc->sc_dma_inuse == 1 && (rint & JZ_INT_DMAEND))
632 sc->sc_resid = data->len >> 2;
633 else if (sc->sc_dma_inuse == 0 &&
634 (rint & (JZ_INT_TXFIFO_WR_REQ | JZ_INT_RXFIFO_RD_REQ)))
635 jz4780_mmc_pio_transfer(sc, data);
637 sc->sc_intr_seen |= rint;
638 if ((sc->sc_intr_seen & sc->sc_intr_wait) == sc->sc_intr_wait)
639 jz4780_mmc_req_ok(sc);
641 JZ_MMC_WRITE_4(sc, JZ_MSC_IFLG, rint);
646 jz4780_mmc_request(device_t bus, device_t child, struct mmc_request *req)
648 struct jz4780_mmc_softc *sc;
649 struct mmc_command *cmd;
650 uint32_t cmdat, ctrl, iwait;
653 sc = device_get_softc(bus);
655 if (sc->sc_req != NULL) {
659 /* Start with template value */
660 cmdat = sc->sc_cmdat;
661 iwait = JZ_INT_END_CMD_RES;
663 /* Configure response format */
665 switch (MMC_RSP(cmd->flags)) {
677 if (cmd->opcode == MMC_GO_IDLE_STATE)
679 if (cmd->flags & MMC_RSP_BUSY) {
681 iwait |= JZ_INT_PRG_DONE;
686 cmd->error = MMC_ERR_NONE;
688 if (cmd->data != NULL) {
690 if (cmd->data->flags & MMC_DATA_MULTI) {
691 cmdat |= JZ_AUTO_CMD12;
692 iwait |= JZ_INT_AUTO_CMD12_DONE;
694 if (cmd->data->flags & MMC_DATA_WRITE) {
696 iwait |= JZ_INT_PRG_DONE;
698 if (cmd->data->flags & MMC_DATA_STREAM)
701 iwait |= JZ_INT_DATA_TRAN_DONE;
703 blksz = min(cmd->data->len, MMC_SECTOR_SIZE);
704 JZ_MMC_WRITE_4(sc, JZ_MSC_BLKLEN, blksz);
705 JZ_MMC_WRITE_4(sc, JZ_MSC_NOB, cmd->data->len / blksz);
707 /* Attempt to setup DMA for this transaction */
708 if (jz4780_mmc_pio_mode == 0)
709 jz4780_mmc_prepare_dma(sc);
710 if (sc->sc_dma_inuse != 0) {
711 /* Wait for DMA completion interrupt */
712 iwait |= JZ_INT_DMAEND;
714 iwait |= (cmd->data->flags & MMC_DATA_WRITE) ?
715 JZ_INT_TXFIFO_WR_REQ : JZ_INT_RXFIFO_RD_REQ;
716 JZ_MMC_WRITE_4(sc, JZ_MSC_DMAC, 0);
720 sc->sc_intr_seen = 0;
721 sc->sc_intr_wait = iwait;
722 JZ_MMC_WRITE_4(sc, JZ_MSC_IMASK, ~(sc->sc_intr_mask | iwait));
724 #if defined(JZ_MMC_DEBUG)
725 device_printf(sc->sc_dev,
726 "REQUEST: CMD%u arg %#x flags %#x cmdat %#x sc_intr_wait = %#x\n",
727 cmd->opcode, cmd->arg, cmd->flags, cmdat, sc->sc_intr_wait);
730 JZ_MMC_WRITE_4(sc, JZ_MSC_ARG, cmd->arg);
731 JZ_MMC_WRITE_4(sc, JZ_MSC_CMD, cmd->opcode);
732 JZ_MMC_WRITE_4(sc, JZ_MSC_CMDAT, cmdat);
734 ctrl = JZ_MMC_READ_4(sc, JZ_MSC_CTRL);
735 ctrl |= JZ_START_OP | JZ_CLOCK_START;
736 JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL, ctrl);
738 callout_reset(&sc->sc_timeoutc, sc->sc_timeout * hz,
739 jz4780_mmc_timeout, sc);
746 jz4780_mmc_read_ivar(device_t bus, device_t child, int which,
749 struct jz4780_mmc_softc *sc;
751 sc = device_get_softc(bus);
755 case MMCBR_IVAR_BUS_MODE:
756 *(int *)result = sc->sc_host.ios.bus_mode;
758 case MMCBR_IVAR_BUS_WIDTH:
759 *(int *)result = sc->sc_host.ios.bus_width;
761 case MMCBR_IVAR_CHIP_SELECT:
762 *(int *)result = sc->sc_host.ios.chip_select;
764 case MMCBR_IVAR_CLOCK:
765 *(int *)result = sc->sc_host.ios.clock;
767 case MMCBR_IVAR_F_MIN:
768 *(int *)result = sc->sc_host.f_min;
770 case MMCBR_IVAR_F_MAX:
771 *(int *)result = sc->sc_host.f_max;
773 case MMCBR_IVAR_HOST_OCR:
774 *(int *)result = sc->sc_host.host_ocr;
776 case MMCBR_IVAR_MODE:
777 *(int *)result = sc->sc_host.mode;
780 *(int *)result = sc->sc_host.ocr;
782 case MMCBR_IVAR_POWER_MODE:
783 *(int *)result = sc->sc_host.ios.power_mode;
786 *(int *)result = sc->sc_host.ios.vdd;
788 case MMCBR_IVAR_CAPS:
789 *(int *)result = sc->sc_host.caps;
791 case MMCBR_IVAR_MAX_DATA:
792 *(int *)result = 65535;
794 case MMCBR_IVAR_TIMING:
795 *(int *)result = sc->sc_host.ios.timing;
803 jz4780_mmc_write_ivar(device_t bus, device_t child, int which,
806 struct jz4780_mmc_softc *sc;
808 sc = device_get_softc(bus);
812 case MMCBR_IVAR_BUS_MODE:
813 sc->sc_host.ios.bus_mode = value;
815 case MMCBR_IVAR_BUS_WIDTH:
816 sc->sc_host.ios.bus_width = value;
818 case MMCBR_IVAR_CHIP_SELECT:
819 sc->sc_host.ios.chip_select = value;
821 case MMCBR_IVAR_CLOCK:
822 sc->sc_host.ios.clock = value;
824 case MMCBR_IVAR_MODE:
825 sc->sc_host.mode = value;
828 sc->sc_host.ocr = value;
830 case MMCBR_IVAR_POWER_MODE:
831 sc->sc_host.ios.power_mode = value;
834 sc->sc_host.ios.vdd = value;
836 case MMCBR_IVAR_TIMING:
837 sc->sc_host.ios.timing = value;
839 /* These are read-only */
840 case MMCBR_IVAR_CAPS:
841 case MMCBR_IVAR_HOST_OCR:
842 case MMCBR_IVAR_F_MIN:
843 case MMCBR_IVAR_F_MAX:
844 case MMCBR_IVAR_MAX_DATA:
852 jz4780_mmc_disable_clock(struct jz4780_mmc_softc *sc)
856 JZ_MMC_WRITE_4(sc, JZ_MSC_CTRL,
857 JZ_MMC_READ_4(sc, JZ_MSC_CTRL) | JZ_CLOCK_STOP);
859 for (timeout = 1000; timeout > 0; timeout--)
860 if ((JZ_MMC_READ_4(sc, JZ_MSC_STAT) & JZ_CLK_EN) == 0)
866 jz4780_mmc_config_clock(struct jz4780_mmc_softc *sc, uint32_t freq)
872 err = jz4780_mmc_disable_clock(sc);
876 clk_get_freq(sc->sc_clk, &rate);
877 clk_freq = (uint32_t)rate;
880 while (clk_freq > freq) {
886 #if defined(JZ_MMC_DEBUG)
887 if (div != JZ_MMC_READ_4(sc, JZ_MSC_CLKRT))
888 device_printf(sc->sc_dev,
889 "UPDATE_IOS: clk -> %u\n", clk_freq);
891 JZ_MMC_WRITE_4(sc, JZ_MSC_CLKRT, div);
896 jz4780_mmc_update_ios(device_t bus, device_t child)
898 struct jz4780_mmc_softc *sc;
902 sc = device_get_softc(bus);
903 ios = &sc->sc_host.ios;
905 /* Set the MMC clock. */
906 error = jz4780_mmc_config_clock(sc, ios->clock);
911 /* Set the bus width. */
912 switch (ios->bus_width) {
914 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
915 sc->sc_cmdat |= JZ_BUS_1BIT;
918 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
919 sc->sc_cmdat |= JZ_BUS_4BIT;
922 sc->sc_cmdat &= ~(JZ_BUS_WIDTH_M);
923 sc->sc_cmdat |= JZ_BUS_8BIT;
930 jz4780_mmc_get_ro(device_t bus, device_t child)
937 jz4780_mmc_acquire_host(device_t bus, device_t child)
939 struct jz4780_mmc_softc *sc;
942 sc = device_get_softc(bus);
944 while (sc->sc_bus_busy) {
945 error = msleep(sc, &sc->sc_mtx, PCATCH, "mmchw", 0);
958 jz4780_mmc_release_host(device_t bus, device_t child)
960 struct jz4780_mmc_softc *sc;
962 sc = device_get_softc(bus);
971 static device_method_t jz4780_mmc_methods[] = {
972 /* Device interface */
973 DEVMETHOD(device_probe, jz4780_mmc_probe),
974 DEVMETHOD(device_attach, jz4780_mmc_attach),
975 DEVMETHOD(device_detach, jz4780_mmc_detach),
978 DEVMETHOD(bus_read_ivar, jz4780_mmc_read_ivar),
979 DEVMETHOD(bus_write_ivar, jz4780_mmc_write_ivar),
980 DEVMETHOD(bus_print_child, bus_generic_print_child),
982 /* MMC bridge interface */
983 DEVMETHOD(mmcbr_update_ios, jz4780_mmc_update_ios),
984 DEVMETHOD(mmcbr_request, jz4780_mmc_request),
985 DEVMETHOD(mmcbr_get_ro, jz4780_mmc_get_ro),
986 DEVMETHOD(mmcbr_acquire_host, jz4780_mmc_acquire_host),
987 DEVMETHOD(mmcbr_release_host, jz4780_mmc_release_host),
992 static devclass_t jz4780_mmc_devclass;
994 static driver_t jz4780_mmc_driver = {
997 sizeof(struct jz4780_mmc_softc),
1000 DRIVER_MODULE(jzmmc, simplebus, jz4780_mmc_driver, jz4780_mmc_devclass, 0, 0);
1001 DRIVER_MODULE(mmc, jzmmc, mmc_driver, mmc_devclass, NULL, NULL);
1002 MODULE_DEPEND(jzmmc, mmc, 1, 1, 1);