2 * Copyright (c) 2015 Alexander Kabaev <kan@FreeBSD.org>
3 * Copyright (c) 2004-2010 Juli Mallett <jmallett@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
34 #include <sys/kernel.h>
36 #include <sys/systm.h>
38 #include <machine/cpufunc.h>
39 #include <machine/hwfunc.h>
40 #include <machine/md_var.h>
41 #include <machine/smp.h>
43 #include <mips/ingenic/jz4780_regs.h>
44 #include <mips/ingenic/jz4780_cpuregs.h>
46 void jz4780_mpentry(void);
48 #define JZ4780_MAXCPU 2
51 platform_ipi_send(int cpuid)
55 mips_wr_xburst_mbox0(1);
57 mips_wr_xburst_mbox1(1);
61 platform_ipi_clear(void)
63 int cpuid = PCPU_GET(cpuid);
66 action = (cpuid == 0) ? mips_rd_xburst_mbox0() : mips_rd_xburst_mbox1();
67 KASSERT(action == 1, ("CPU %d: unexpected IPIs: %#x", cpuid, action));
68 mips_wr_xburst_core_sts(~(JZ_CORESTS_MIRQ0P << cpuid));
72 platform_processor_id(void)
75 return (mips_rd_ebase() & 7);
79 platform_ipi_hardintr_num(void)
86 platform_ipi_softintr_num(void)
93 platform_init_ap(int cpuid)
98 * Clear any pending IPIs.
100 mips_wr_xburst_core_sts(~(JZ_CORESTS_MIRQ0P << cpuid));
102 /* Allow IPI mbox for this core */
103 reg = mips_rd_xburst_reim();
104 reg |= (JZ_REIM_MIRQ0M << cpuid);
105 mips_wr_xburst_reim(reg);
108 * Unmask the ipi interrupts.
110 reg = hard_int_mask(platform_ipi_hardintr_num());
115 platform_cpu_mask(cpuset_t *mask)
120 for (i = 0, m = 1 ; i < JZ4780_MAXCPU; i++, m <<= 1)
125 platform_smp_topo(void)
127 return (smp_topo_none());
131 jz4780_core_powerup(void)
135 reg = readreg(JZ_CGU_BASE + JZ_LPCR);
136 reg &= ~LPCR_PD_SCPU;
137 writereg(JZ_CGU_BASE + JZ_LPCR, reg);
139 reg = readreg(JZ_CGU_BASE + JZ_LPCR);
140 } while ((reg & LPCR_SCPUS) != 0);
144 * Spin up the second code. The code is roughly modeled after
145 * similar routine in Linux.
148 platform_start_ap(int cpuid)
152 if (cpuid >= JZ4780_MAXCPU)
155 /* Figure out address of mpentry in KSEG1 */
156 addr = MIPS_PHYS_TO_KSEG1(MIPS_KSEG0_TO_PHYS(jz4780_mpentry));
157 KASSERT((addr & ~JZ_REIM_ENTRY_MASK) == 0,
158 ("Unaligned mpentry"));
160 /* Configure core alternative entry point */
161 reg = mips_rd_xburst_reim();
162 reg &= ~JZ_REIM_ENTRY_MASK;
163 reg |= addr & JZ_REIM_ENTRY_MASK;
165 /* Allow this core to get IPIs from one being started */
166 reg |= JZ_REIM_MIRQ0M;
167 mips_wr_xburst_reim(reg);
169 /* Force core into reset and enable use of alternate entry point */
170 reg = mips_rd_xburst_core_ctl();
171 reg |= (JZ_CORECTL_SWRST0 << cpuid) | (JZ_CORECTL_RPC0 << cpuid);
172 mips_wr_xburst_core_ctl(reg);
174 /* Power the core up */
175 jz4780_core_powerup();
177 /* Take the core out of reset */
178 reg &= ~(JZ_CORECTL_SWRST0 << cpuid);
179 mips_wr_xburst_core_ctl(reg);