sys/mips/ingenic/jz4780_pdma.c

   1 /*-
   2  * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
   3  * All rights reserved.
   4  *
   5  * This software was developed by SRI International and the University of
   6  * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
   7  * ("CTSRD"), as part of the DARPA CRASH research programme.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  19  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  22  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  23  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  24  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  25  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  26  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  27  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  28  * SUCH DAMAGE.
  29  */
  30
  31 /* Ingenic JZ4780 PDMA Controller. */
  32
  33 #include <sys/cdefs.h>
  34 __FBSDID("$FreeBSD$");
  35
  36 #include "opt_platform.h"
  37 #include <sys/param.h>
  38 #include <sys/systm.h>
  39 #include <sys/conf.h>
  40 #include <sys/bus.h>
  41 #include <sys/kernel.h>
  42 #include <sys/module.h>
  43 #include <sys/lock.h>
  44 #include <sys/mutex.h>
  45 #include <sys/resource.h>
  46 #include <sys/rman.h>
  47
  48 #include <machine/bus.h>
  49 #include <machine/cache.h>
  50
  51 #ifdef FDT
  52 #include <dev/fdt/fdt_common.h>
  53 #include <dev/ofw/ofw_bus.h>
  54 #include <dev/ofw/ofw_bus_subr.h>
  55 #endif
  56
  57 #include <dev/xdma/xdma.h>
  58
  59 #include <mips/ingenic/jz4780_common.h>
  60 #include <mips/ingenic/jz4780_pdma.h>
  61
  62 #include "xdma_if.h"
  63
  64 struct pdma_softc {
  65         device_t                dev;
  66         struct resource         *res[2];
  67         bus_space_tag_t         bst;
  68         bus_space_handle_t      bsh;
  69         void                    *ih;
  70 };
  71
  72 struct pdma_fdt_data {
  73         int tx;
  74         int rx;
  75         int chan;
  76 };
  77
  78 struct pdma_channel {
  79         xdma_channel_t          *xchan;
  80         struct pdma_fdt_data    data;
  81         int                     cur_desc;
  82         int                     used;
  83         int                     index;
  84         int                     flags;
  85 #define CHAN_DESCR_RELINK       (1 << 0)
  86 };
  87
  88 #define PDMA_NCHANNELS  32
  89 struct pdma_channel pdma_channels[PDMA_NCHANNELS];
  90
  91 static struct resource_spec pdma_spec[] = {
  92         { SYS_RES_MEMORY,       0,      RF_ACTIVE },
  93         { SYS_RES_IRQ,          0,      RF_ACTIVE },
  94         { -1, 0 }
  95 };
  96
  97 static int pdma_probe(device_t dev);
  98 static int pdma_attach(device_t dev);
  99 static int pdma_detach(device_t dev);
 100 static int chan_start(struct pdma_softc *sc, struct pdma_channel *chan);
 101
 102 static void
 103 pdma_intr(void *arg)
 104 {
 105         struct pdma_channel *chan;
 106         struct pdma_softc *sc;
 107         xdma_channel_t *xchan;
 108         xdma_config_t *conf;
 109         int pending;
 110         int i;
 111
 112         sc = arg;
 113
 114         pending = READ4(sc, PDMA_DIRQP);
 115
 116         /* Ack all the channels. */
 117         WRITE4(sc, PDMA_DIRQP, 0);
 118
 119         for (i = 0; i < PDMA_NCHANNELS; i++) {
 120                 if (pending & (1 << i)) {
 121                         chan = &pdma_channels[i];
 122                         xchan = chan->xchan;
 123                         conf = &xchan->conf;
 124
 125                         /* TODO: check for AR, HLT error bits here. */
 126
 127                         /* Disable channel */
 128                         WRITE4(sc, PDMA_DCS(chan->index), 0);
 129
 130                         if (chan->flags & CHAN_DESCR_RELINK) {
 131                                 /* Enable again */
 132                                 chan->cur_desc = (chan->cur_desc + 1) % \
 133                                     conf->block_num;
 134                                 chan_start(sc, chan);
 135                         }
 136
 137                         xdma_callback(chan->xchan);
 138                 }
 139         }
 140 }
 141
 142 static int
 143 pdma_probe(device_t dev)
 144 {
 145
 146         if (!ofw_bus_status_okay(dev))
 147                 return (ENXIO);
 148
 149         if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-dma"))
 150                 return (ENXIO);
 151
 152         device_set_desc(dev, "Ingenic JZ4780 PDMA Controller");
 153
 154         return (BUS_PROBE_DEFAULT);
 155 }
 156
 157 static int
 158 pdma_attach(device_t dev)
 159 {
 160         struct pdma_softc *sc;
 161         phandle_t xref, node;
 162         int err;
 163         int reg;
 164
 165         sc = device_get_softc(dev);
 166         sc->dev = dev;
 167
 168         if (bus_alloc_resources(dev, pdma_spec, sc->res)) {
 169                 device_printf(dev, "could not allocate resources for device\n");
 170                 return (ENXIO);
 171         }
 172
 173         /* Memory interface */
 174         sc->bst = rman_get_bustag(sc->res[0]);
 175         sc->bsh = rman_get_bushandle(sc->res[0]);
 176
 177         /* Setup interrupt handler */
 178         err = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
 179             NULL, pdma_intr, sc, &sc->ih);
 180         if (err) {
 181                 device_printf(dev, "Unable to alloc interrupt resource.\n");
 182                 return (ENXIO);
 183         }
 184
 185         node = ofw_bus_get_node(dev);
 186         xref = OF_xref_from_node(node);
 187         OF_device_register_xref(xref, dev);
 188
 189         reg = READ4(sc, PDMA_DMAC);
 190         reg &= ~(DMAC_HLT | DMAC_AR);
 191         reg |= (DMAC_DMAE);
 192         WRITE4(sc, PDMA_DMAC, reg);
 193
 194         WRITE4(sc, PDMA_DMACP, 0);
 195
 196         return (0);
 197 }
 198
 199 static int
 200 pdma_detach(device_t dev)
 201 {
 202         struct pdma_softc *sc;
 203
 204         sc = device_get_softc(dev);
 205
 206         bus_release_resources(dev, pdma_spec, sc->res);
 207
 208         return (0);
 209 }
 210
 211 static int
 212 chan_start(struct pdma_softc *sc, struct pdma_channel *chan)
 213 {
 214         struct xdma_channel *xchan;
 215
 216         xchan = chan->xchan;
 217
 218         /* 8 byte descriptor. */
 219         WRITE4(sc, PDMA_DCS(chan->index), DCS_DES8);
 220         WRITE4(sc, PDMA_DDA(chan->index), xchan->descs_phys[chan->cur_desc].ds_addr);
 221         WRITE4(sc, PDMA_DDS, (1 << chan->index));
 222
 223         /* Channel transfer enable. */
 224         WRITE4(sc, PDMA_DCS(chan->index), (DCS_DES8 | DCS_CTE));
 225
 226         return (0);
 227 }
 228
 229 static int
 230 chan_stop(struct pdma_softc *sc, struct pdma_channel *chan)
 231 {
 232         int timeout;
 233
 234         WRITE4(sc, PDMA_DCS(chan->index), 0);
 235
 236         timeout = 100;
 237
 238         do {
 239                 if ((READ4(sc, PDMA_DCS(chan->index)) & DCS_CTE) == 0) {
 240                         break;
 241                 }
 242         } while (timeout--);
 243
 244         if (timeout == 0) {
 245                 device_printf(sc->dev, "%s: Can't stop channel %d\n",
 246                     __func__, chan->index);
 247         }
 248
 249         return (0);
 250 }
 251
 252 static int
 253 pdma_channel_alloc(device_t dev, struct xdma_channel *xchan)
 254 {
 255         struct pdma_channel *chan;
 256         struct pdma_softc *sc;
 257         int i;
 258
 259         sc = device_get_softc(dev);
 260
 261         xdma_assert_locked();
 262
 263         for (i = 0; i < PDMA_NCHANNELS; i++) {
 264                 chan = &pdma_channels[i];
 265                 if (chan->used == 0) {
 266                         chan->xchan = xchan;
 267                         xchan->chan = (void *)chan;
 268                         chan->used = 1;
 269                         chan->index = i;
 270
 271                         return (0);
 272                 }
 273         }
 274
 275         return (-1);
 276 }
 277
 278 static int
 279 pdma_channel_free(device_t dev, struct xdma_channel *xchan)
 280 {
 281         struct pdma_channel *chan;
 282         struct pdma_softc *sc;
 283
 284         sc = device_get_softc(dev);
 285
 286         xdma_assert_locked();
 287
 288         chan = (struct pdma_channel *)xchan->chan;
 289         chan->used = 0;
 290
 291         return (0);
 292 }
 293
 294 static int
 295 pdma_channel_prep_memcpy(device_t dev, struct xdma_channel *xchan)
 296 {
 297         struct pdma_channel *chan;
 298         struct pdma_hwdesc *desc;
 299         struct pdma_softc *sc;
 300         xdma_config_t *conf;
 301         int ret;
 302
 303         sc = device_get_softc(dev);
 304
 305         chan = (struct pdma_channel *)xchan->chan;
 306         /* Ensure we are not in operation */
 307         chan_stop(sc, chan);
 308
 309         ret = xdma_desc_alloc(xchan, sizeof(struct pdma_hwdesc), 8);
 310         if (ret != 0) {
 311                 device_printf(sc->dev,
 312                     "%s: Can't allocate descriptors.\n", __func__);
 313                 return (-1);
 314         }
 315
 316         conf = &xchan->conf;
 317         desc = (struct pdma_hwdesc *)xchan->descs;
 318         desc[0].dsa = conf->src_addr;
 319         desc[0].dta = conf->dst_addr;
 320         desc[0].drt = DRT_AUTO;
 321         desc[0].dcm = DCM_SAI | DCM_DAI;
 322
 323         /* 4 byte copy for now. */
 324         desc[0].dtc = (conf->block_len / 4);
 325         desc[0].dcm |= DCM_SP_4 | DCM_DP_4 | DCM_TSZ_4;
 326         desc[0].dcm |= DCM_TIE;
 327
 328         return (0);
 329 }
 330
 331 static int
 332 access_width(xdma_config_t *conf, uint32_t *dcm, uint32_t *max_width)
 333 {
 334
 335         *dcm = 0;
 336         *max_width = max(conf->src_width, conf->dst_width);
 337
 338         switch (conf->src_width) {
 339         case 1:
 340                 *dcm |= DCM_SP_1;
 341                 break;
 342         case 2:
 343                 *dcm |= DCM_SP_2;
 344                 break;
 345         case 4:
 346                 *dcm |= DCM_SP_4;
 347                 break;
 348         default:
 349                 return (-1);
 350         }
 351
 352         switch (conf->dst_width) {
 353         case 1:
 354                 *dcm |= DCM_DP_1;
 355                 break;
 356         case 2:
 357                 *dcm |= DCM_DP_2;
 358                 break;
 359         case 4:
 360                 *dcm |= DCM_DP_4;
 361                 break;
 362         default:
 363                 return (-1);
 364         }
 365
 366         switch (*max_width) {
 367         case 1:
 368                 *dcm |= DCM_TSZ_1;
 369                 break;
 370         case 2:
 371                 *dcm |= DCM_TSZ_2;
 372                 break;
 373         case 4:
 374                 *dcm |= DCM_TSZ_4;
 375                 break;
 376         default:
 377                 return (-1);
 378         };
 379
 380         return (0);
 381 }
 382
 383 static int
 384 pdma_channel_prep_cyclic(device_t dev, struct xdma_channel *xchan)
 385 {
 386         struct pdma_fdt_data *data;
 387         struct pdma_channel *chan;
 388         struct pdma_hwdesc *desc;
 389         xdma_controller_t *xdma;
 390         struct pdma_softc *sc;
 391         xdma_config_t *conf;
 392         int max_width;
 393         uint32_t reg;
 394         uint32_t dcm;
 395         int ret;
 396         int i;
 397
 398         sc = device_get_softc(dev);
 399
 400         conf = &xchan->conf;
 401         xdma = xchan->xdma;
 402         data = (struct pdma_fdt_data *)xdma->data;
 403
 404         ret = xdma_desc_alloc(xchan, sizeof(struct pdma_hwdesc), 8);
 405         if (ret != 0) {
 406                 device_printf(sc->dev,
 407                     "%s: Can't allocate descriptors.\n", __func__);
 408                 return (-1);
 409         }
 410
 411         chan = (struct pdma_channel *)xchan->chan;
 412         /* Ensure we are not in operation */
 413         chan_stop(sc, chan);
 414         chan->flags = CHAN_DESCR_RELINK;
 415         chan->cur_desc = 0;
 416
 417         desc = (struct pdma_hwdesc *)xchan->descs;
 418
 419         for (i = 0; i < conf->block_num; i++) {
 420                 if (conf->direction == XDMA_MEM_TO_DEV) {
 421                         desc[i].dsa = conf->src_addr + (i * conf->block_len);
 422                         desc[i].dta = conf->dst_addr;
 423                         desc[i].drt = data->tx;
 424                         desc[i].dcm = DCM_SAI;
 425                 } else if (conf->direction == XDMA_DEV_TO_MEM) {
 426                         desc[i].dsa = conf->src_addr;
 427                         desc[i].dta = conf->dst_addr + (i * conf->block_len);
 428                         desc[i].drt = data->rx;
 429                         desc[i].dcm = DCM_DAI;
 430                 } else if (conf->direction == XDMA_MEM_TO_MEM) {
 431                         desc[i].dsa = conf->src_addr + (i * conf->block_len);
 432                         desc[i].dta = conf->dst_addr + (i * conf->block_len);
 433                         desc[i].drt = DRT_AUTO;
 434                         desc[i].dcm = DCM_SAI | DCM_DAI;
 435                 }
 436
 437                 if (access_width(conf, &dcm, &max_width) != 0) {
 438                         device_printf(dev,
 439                             "%s: can't configure access width\n", __func__);
 440                         return (-1);
 441                 }
 442
 443                 desc[i].dcm |= dcm | DCM_TIE;
 444                 desc[i].dtc = (conf->block_len / max_width);
 445
 446                 /*
 447                  * PDMA does not provide interrupt after processing each descriptor,
 448                  * but after processing all the chain only.
 449                  * As a workaround we do unlink descriptors here, so our chain will
 450                  * consists of single descriptor only. And then we reconfigure channel
 451                  * on each interrupt again.
 452                  */
 453                 if ((chan->flags & CHAN_DESCR_RELINK) == 0) {
 454                         if (i != (conf->block_num - 1)) {
 455                                 desc[i].dcm |= DCM_LINK;
 456                                 reg = ((i + 1) * sizeof(struct pdma_hwdesc));
 457                                 desc[i].dtc |= (reg >> 4) << 24;
 458                         }
 459                 }
 460         }
 461
 462         return (0);
 463 }
 464
 465 static int
 466 pdma_channel_control(device_t dev, xdma_channel_t *xchan, int cmd)
 467 {
 468         struct pdma_channel *chan;
 469         struct pdma_softc *sc;
 470
 471         sc = device_get_softc(dev);
 472
 473         chan = (struct pdma_channel *)xchan->chan;
 474
 475         switch (cmd) {
 476         case XDMA_CMD_BEGIN:
 477                 chan_start(sc, chan);
 478                 break;
 479         case XDMA_CMD_TERMINATE:
 480                 chan_stop(sc, chan);
 481                 break;
 482         case XDMA_CMD_PAUSE:
 483                 /* TODO: implement me */
 484                 return (-1);
 485         }
 486
 487         return (0);
 488 }
 489
 490 #ifdef FDT
 491 static int
 492 pdma_ofw_md_data(device_t dev, pcell_t *cells, int ncells, void **ptr)
 493 {
 494         struct pdma_fdt_data *data;
 495
 496         if (ncells != 3) {
 497                 return (-1);
 498         }
 499
 500         data = malloc(sizeof(struct pdma_fdt_data), M_DEVBUF, (M_WAITOK | M_ZERO));
 501         if (data == NULL) {
 502                 device_printf(dev, "%s: Cant allocate memory\n", __func__);
 503                 return (-1);
 504         }
 505
 506         data->tx = cells[0];
 507         data->rx = cells[1];
 508         data->chan = cells[2];
 509
 510         *ptr = data;
 511
 512         return (0);
 513 }
 514 #endif
 515
 516 static device_method_t pdma_methods[] = {
 517         /* Device interface */
 518         DEVMETHOD(device_probe,                 pdma_probe),
 519         DEVMETHOD(device_attach,                pdma_attach),
 520         DEVMETHOD(device_detach,                pdma_detach),
 521
 522         /* xDMA Interface */
 523         DEVMETHOD(xdma_channel_alloc,           pdma_channel_alloc),
 524         DEVMETHOD(xdma_channel_free,            pdma_channel_free),
 525         DEVMETHOD(xdma_channel_prep_cyclic,     pdma_channel_prep_cyclic),
 526         DEVMETHOD(xdma_channel_prep_memcpy,     pdma_channel_prep_memcpy),
 527         DEVMETHOD(xdma_channel_control,         pdma_channel_control),
 528 #ifdef FDT
 529         DEVMETHOD(xdma_ofw_md_data,             pdma_ofw_md_data),
 530 #endif
 531
 532         DEVMETHOD_END
 533 };
 534
 535 static driver_t pdma_driver = {
 536         "pdma",
 537         pdma_methods,
 538         sizeof(struct pdma_softc),
 539 };
 540
 541 static devclass_t pdma_devclass;
 542
 543 EARLY_DRIVER_MODULE(pdma, simplebus, pdma_driver, pdma_devclass, 0, 0,
 544     BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);