2 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
5 * This software was developed by SRI International and the University of
6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237
7 * ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 /* DMA Channel Registers */
34 #define PDMA_DSA(n) (0x00 + 0x20 * n) /* Channel n Source Address */
35 #define PDMA_DTA(n) (0x04 + 0x20 * n) /* Channel n Target Address */
36 #define PDMA_DTC(n) (0x08 + 0x20 * n) /* Channel n Transfer Count */
37 #define PDMA_DRT(n) (0x0C + 0x20 * n) /* Channel n Request Source */
38 #define DRT_AUTO (1 << 3) /* Auto-request. */
39 #define PDMA_DCS(n) (0x10 + 0x20 * n) /* Channel n Control/Status */
40 #define DCS_NDES (1 << 31) /* Non-descriptor mode. */
41 #define DCS_DES8 (1 << 30) /* Descriptor 8 Word. */
42 #define DCS_AR (1 << 4) /* Address Error. */
43 #define DCS_TT (1 << 3) /* Transfer Terminate. */
44 #define DCS_HLT (1 << 2) /* DMA halt. */
45 #define DCS_CTE (1 << 0) /* Channel transfer enable. */
46 #define PDMA_DCM(n) (0x14 + 0x20 * n) /* Channel n Command */
47 #define DCM_SAI (1 << 23) /* Source Address Increment. */
48 #define DCM_DAI (1 << 22) /* Destination Address Increment. */
49 #define DCM_SP_S 14 /* Source port width. */
50 #define DCM_SP_M (0x3 << DCM_SP_S)
51 #define DCM_SP_1 (0x1 << DCM_SP_S) /* 1 byte */
52 #define DCM_SP_2 (0x2 << DCM_SP_S) /* 2 bytes */
53 #define DCM_SP_4 (0x0 << DCM_SP_S) /* 4 bytes */
54 #define DCM_DP_S 12 /* Destination port width. */
55 #define DCM_DP_M (0x3 << DCM_DP_S)
56 #define DCM_DP_1 (0x1 << DCM_DP_S) /* 1 byte */
57 #define DCM_DP_2 (0x2 << DCM_DP_S) /* 2 bytes */
58 #define DCM_DP_4 (0x0 << DCM_DP_S) /* 4 bytes */
59 #define DCM_TSZ_S 8 /* Transfer Data Size of a data unit. */
60 #define DCM_TSZ_M (0x7 << DCM_TSZ_S)
61 #define DCM_TSZ_A (0x7 << DCM_TSZ_S) /* Autonomy */
62 #define DCM_TSZ_1 (0x1 << DCM_TSZ_S)
63 #define DCM_TSZ_2 (0x2 << DCM_TSZ_S)
64 #define DCM_TSZ_4 (0x0 << DCM_TSZ_S)
65 #define DCM_TSZ_16 (0x3 << DCM_TSZ_S)
66 #define DCM_TSZ_32 (0x4 << DCM_TSZ_S)
67 #define DCM_TSZ_64 (0x5 << DCM_TSZ_S)
68 #define DCM_TSZ_128 (0x6 << DCM_TSZ_S)
69 #define DCM_TIE (1 << 1) /* Transfer Interrupt Enable (TIE). */
70 #define DCM_LINK (1 << 0) /* Descriptor Link Enable. */
71 #define PDMA_DDA(n) (0x18 + 0x20 * n) /* Channel n Descriptor Address */
72 #define PDMA_DSD(n) (0x1C + 0x20 * n) /* Channel n Stride Difference */
74 /* Global Control Registers */
75 #define PDMA_DMAC 0x1000 /* DMA Control */
76 #define DMAC_FMSC (1 << 31)
77 #define DMAC_INTCC_S 17
78 #define DMAC_INTCC_M (0x1f << DMAC_INTCC_S)
79 #define DMAC_INTCE (1 << 16) /* Permit INTC_IRQ to be bound to one of programmable channel. */
80 #define DMAC_HLT (1 << 3) /* Global halt status */
81 #define DMAC_AR (1 << 2) /* Global address error status */
82 #define DMAC_DMAE (1 << 0) /* Enable DMA. */
83 #define PDMA_DIRQP 0x1004 /* DMA Interrupt Pending */
84 #define PDMA_DDB 0x1008 /* DMA Doorbell */
85 #define PDMA_DDS 0x100C /* DMA Doorbell Set */
86 #define PDMA_DIP 0x1010 /* Descriptor Interrupt Pending */
87 #define PDMA_DIC 0x1014 /* Descriptor Interrupt Clear */
88 #define PDMA_DMACP 0x101C /* DMA Channel Programmable */
89 #define PDMA_DSIRQP 0x1020 /* Channel soft IRQ to MCU */
90 #define PDMA_DSIRQM 0x1024 /* Channel soft IRQ mask */
91 #define PDMA_DCIRQP 0x1028 /* Channel IRQ to MCU */
92 #define PDMA_DCIRQM 0x102C /* Channel IRQ to MCU mask */
93 #define PDMA_DMCS 0x1030 /* MCU Control and Status */
94 #define PDMA_DMNMB 0x1034 /* MCU Normal Mailbox */
95 #define PDMA_DMSMB 0x1038 /* MCU Security Mailbox */
96 #define PDMA_DMINT 0x103C /* MCU Interrupt */
99 uint32_t dcm; /* DMA Channel Command */
100 uint32_t dsa; /* DMA Source Address */
101 uint32_t dta; /* DMA Target Address */
102 uint32_t dtc; /* DMA Transfer Counter */
103 uint32_t sd; /* Stride Address */
104 uint32_t drt; /* DMA Request Type */
105 uint32_t reserved[2];
108 #define CHAN_DESC_COUNT 4096
109 #define CHAN_DESC_SIZE (sizeof(struct pdma_hwdesc) * CHAN_DESC_COUNT)