2 * Copyright 2016 Alexander Kabaev <kan@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * Ingenic JZ4780 RTC driver
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <sys/param.h>
36 #include <sys/systm.h>
38 #include <sys/clock.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/resource.h>
44 #include <machine/bus.h>
46 #include <dev/ofw/ofw_bus.h>
47 #include <dev/ofw/ofw_bus_subr.h>
51 #define JZ_RTC_TIMEOUT 5000
54 # define JZ_RTCCR_WRDY (1u << 7)
58 # define JZ_WENR_PAT 0xa55a
59 # define JZ_WENR_WEN (1u <<31)
61 struct jz4780_rtc_softc {
63 struct resource *res[2];
66 static struct resource_spec jz4780_rtc_spec[] = {
67 { SYS_RES_MEMORY, 0, RF_ACTIVE },
68 { SYS_RES_IRQ, 0, RF_ACTIVE },
72 #define CSR_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
73 #define CSR_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
75 static int jz4780_rtc_probe(device_t dev);
76 static int jz4780_rtc_attach(device_t dev);
77 static int jz4780_rtc_detach(device_t dev);
80 jz4780_rtc_probe(device_t dev)
83 if (!ofw_bus_status_okay(dev))
86 if (!ofw_bus_is_compatible(dev, "ingenic,jz4780-rtc"))
89 device_set_desc(dev, "JZ4780 RTC");
91 return (BUS_PROBE_DEFAULT);
94 /* Poll control register until RTC is ready to accept register writes */
96 jz4780_rtc_wait(struct jz4780_rtc_softc *sc)
100 timeout = JZ_RTC_TIMEOUT;
101 while (timeout-- > 0) {
102 if (CSR_READ(sc, JZ_RTCCR) & JZ_RTCCR_WRDY)
109 * Write RTC register. It appears that RTC goes into read-only mode at random,
110 * which suggests something is up with how it is powered up, so do the pattern
111 * writing dance every time just in case.
114 jz4780_rtc_write(struct jz4780_rtc_softc *sc, uint32_t reg, uint32_t val)
118 ret = jz4780_rtc_wait(sc);
122 CSR_WRITE(sc, JZ_WENR, JZ_WENR_PAT);
124 ret = jz4780_rtc_wait(sc);
128 timeout = JZ_RTC_TIMEOUT;
129 while (timeout-- > 0) {
130 if (CSR_READ(sc, JZ_WENR) & JZ_WENR_WEN)
136 CSR_WRITE(sc, reg, val);
141 jz4780_rtc_attach(device_t dev)
143 struct jz4780_rtc_softc *sc = device_get_softc(dev);
149 if (bus_alloc_resources(dev, jz4780_rtc_spec, sc->res)) {
150 device_printf(dev, "could not allocate resources for device\n");
154 scratch = CSR_READ(sc, JZ_HSPR);
155 if (scratch != 0x12345678) {
156 ret = jz4780_rtc_write(sc, JZ_HSPR, 0x12345678);
158 ret = jz4780_rtc_write(sc, JZ_RTSR, 0);
160 device_printf(dev, "Unable to write RTC registers\n");
161 jz4780_rtc_detach(dev);
165 clock_register(dev, 1000000); /* Register 1 HZ clock */
170 jz4780_rtc_detach(device_t dev)
172 struct jz4780_rtc_softc *sc;
174 sc = device_get_softc(dev);
175 bus_release_resources(dev, jz4780_rtc_spec, sc->res);
180 jz4780_rtc_gettime(device_t dev, struct timespec *ts)
182 struct jz4780_rtc_softc *sc;
186 sc = device_get_softc(dev);
188 timeout = JZ_RTC_TIMEOUT;
189 val2 = CSR_READ(sc, JZ_RTSR);
192 val2 = CSR_READ(sc, JZ_RTSR);
193 } while (val1 != val2 && timeout-- >= 0);
198 /* Convert secs to timespec directly */
205 jz4780_rtc_settime(device_t dev, struct timespec *ts)
207 struct jz4780_rtc_softc *sc;
209 sc = device_get_softc(dev);
210 return jz4780_rtc_write(sc, JZ_RTSR, ts->tv_sec);
213 static device_method_t jz4780_rtc_methods[] = {
214 /* Device interface */
215 DEVMETHOD(device_probe, jz4780_rtc_probe),
216 DEVMETHOD(device_attach, jz4780_rtc_attach),
217 DEVMETHOD(device_detach, jz4780_rtc_detach),
219 DEVMETHOD(clock_gettime, jz4780_rtc_gettime),
220 DEVMETHOD(clock_settime, jz4780_rtc_settime),
225 static driver_t jz4780_rtc_driver = {
228 sizeof(struct jz4780_rtc_softc),
231 static devclass_t jz4780_rtc_devclass;
233 EARLY_DRIVER_MODULE(jz4780_rtc, simplebus, jz4780_rtc_driver,
234 jz4780_rtc_devclass, 0, 0, BUS_PASS_TIMER + BUS_PASS_ORDER_MIDDLE);