1 /* $NetBSD: gt_pci.c,v 1.4 2003/07/15 00:24:54 lukem Exp $ */
4 * SPDX-License-Identifier: BSD-4-Clause
6 * Copyright (c) 2001, 2002 Wasabi Systems, Inc.
9 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed for the NetBSD Project by
22 * Wasabi Systems, Inc.
23 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
24 * or promote products derived from this software without specific prior
27 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
37 * POSSIBILITY OF SUCH DAMAGE.
41 * PCI configuration support for gt I/O Processor chip.
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
47 #include <sys/param.h>
48 #include <sys/systm.h>
51 #include <sys/endian.h>
52 #include <sys/interrupt.h>
53 #include <sys/malloc.h>
54 #include <sys/kernel.h>
55 #include <sys/module.h>
60 #include <vm/vm_extern.h>
62 #include <machine/bus.h>
63 #include <machine/cpu.h>
65 #include <mips/malta/maltareg.h>
67 #include <mips/malta/gtreg.h>
68 #include <mips/malta/gtvar.h>
70 #include <isa/isareg.h>
71 #include <dev/ic/i8259.h>
73 #include <dev/pci/pcireg.h>
74 #include <dev/pci/pcivar.h>
76 #include <dev/pci/pcib_private.h>
79 #include <mips/malta/gt_pci_bus_space.h>
81 #define ICU_LEN 16 /* number of ISA IRQs */
84 * XXX: These defines are from NetBSD's <dev/ic/i8259reg.h>. Respective file
85 * from FreeBSD src tree <dev/ic/i8259.h> lacks some definitions.
92 #define OCW2_ILS(x) ((x) << 0) /* interrupt level select */
94 #define OCW3_POLL_IRQ(x) ((x) & 0x7f)
95 #define OCW3_POLL_PENDING (1U << 7)
98 * Galileo controller's registers are LE so convert to then
99 * to/from native byte order. We rely on boot loader or emulator
100 * to set "swap bytes" configuration correctly for us
102 #define GT_PCI_DATA(v) htole32((v))
103 #define GT_HOST_DATA(v) le32toh((v))
107 struct gt_pci_intr_cookie {
109 struct gt_pci_softc *sc;
112 struct gt_pci_softc {
114 bus_space_tag_t sc_st;
115 bus_space_handle_t sc_ioh_icu1;
116 bus_space_handle_t sc_ioh_icu2;
117 bus_space_handle_t sc_ioh_elcr;
120 struct rman sc_mem_rman;
121 struct rman sc_io_rman;
122 struct rman sc_irq_rman;
123 unsigned long sc_mem;
124 bus_space_handle_t sc_io;
126 struct resource *sc_irq;
127 struct intr_event *sc_eventstab[ICU_LEN];
128 struct gt_pci_intr_cookie sc_intr_cookies[ICU_LEN];
132 uint16_t sc_reserved;
137 static void gt_pci_set_icus(struct gt_pci_softc *);
138 static int gt_pci_intr(void *v);
139 static int gt_pci_probe(device_t);
140 static int gt_pci_attach(device_t);
141 static int gt_pci_activate_resource(device_t, device_t, int, int,
143 static int gt_pci_setup_intr(device_t, device_t, struct resource *,
144 int, driver_filter_t *, driver_intr_t *, void *, void **);
145 static int gt_pci_teardown_intr(device_t, device_t, struct resource *, void*);
146 static int gt_pci_maxslots(device_t );
147 static int gt_pci_conf_setup(struct gt_pci_softc *, int, int, int, int,
149 static uint32_t gt_pci_read_config(device_t, u_int, u_int, u_int, u_int, int);
150 static void gt_pci_write_config(device_t, u_int, u_int, u_int, u_int,
152 static int gt_pci_route_interrupt(device_t pcib, device_t dev, int pin);
153 static struct resource * gt_pci_alloc_resource(device_t, device_t, int,
154 int *, rman_res_t, rman_res_t, rman_res_t, u_int);
157 gt_pci_mask_irq(void *source)
159 struct gt_pci_intr_cookie *cookie = source;
160 struct gt_pci_softc *sc = cookie->sc;
161 int irq = cookie->irq;
163 sc->sc_imask |= (1 << irq);
164 sc->sc_elcr |= (1 << irq);
170 gt_pci_unmask_irq(void *source)
172 struct gt_pci_intr_cookie *cookie = source;
173 struct gt_pci_softc *sc = cookie->sc;
174 int irq = cookie->irq;
176 /* Enable it, set trigger mode. */
177 sc->sc_imask &= ~(1 << irq);
178 sc->sc_elcr &= ~(1 << irq);
184 gt_pci_set_icus(struct gt_pci_softc *sc)
186 /* Enable the cascade IRQ (2) if 8-15 is enabled. */
187 if ((sc->sc_imask & 0xff00) != 0xff00)
188 sc->sc_imask &= ~(1U << 2);
190 sc->sc_imask |= (1U << 2);
192 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW1,
193 sc->sc_imask & 0xff);
194 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, PIC_OCW1,
195 (sc->sc_imask >> 8) & 0xff);
197 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
199 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
200 (sc->sc_elcr >> 8) & 0xff);
206 struct gt_pci_softc *sc = v;
207 struct intr_event *event;
211 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3,
213 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW3);
214 if ((irq & OCW3_POLL_PENDING) == 0)
216 return FILTER_HANDLED;
219 irq = OCW3_POLL_IRQ(irq);
222 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
223 PIC_OCW3, OCW3_SEL | OCW3_P);
224 irq = bus_space_read_1(sc->sc_st, sc->sc_ioh_icu2,
226 if (irq & OCW3_POLL_PENDING)
227 irq = OCW3_POLL_IRQ(irq) + 8;
232 event = sc->sc_eventstab[irq];
234 if (!event || CK_SLIST_EMPTY(&event->ie_handlers))
237 /* TODO: frame instead of NULL? */
238 intr_event_handle(event, NULL);
239 /* XXX: Log stray IRQs */
241 /* Send a specific EOI to the 8259. */
243 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2,
244 PIC_OCW2, OCW2_SELECT | OCW2_EOI | OCW2_SL |
249 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, PIC_OCW2,
250 OCW2_SELECT | OCW2_EOI | OCW2_SL | OCW2_ILS(irq));
253 return FILTER_HANDLED;
257 gt_pci_probe(device_t dev)
259 device_set_desc(dev, "GT64120 PCI bridge");
264 gt_pci_attach(device_t dev)
268 struct gt_pci_softc *sc = device_get_softc(dev);
273 sc->sc_busno = busno;
274 sc->sc_st = mips_bus_space_generic;
276 /* Use KSEG1 to access IO ports for it is uncached */
277 sc->sc_io = MALTA_PCI0_IO_BASE;
278 sc->sc_io_rman.rm_type = RMAN_ARRAY;
279 sc->sc_io_rman.rm_descr = "GT64120 PCI I/O Ports";
281 * First 256 bytes are ISA's registers: e.g. i8259's
282 * So do not use them for general purpose PCI I/O window
284 if (rman_init(&sc->sc_io_rman) != 0 ||
285 rman_manage_region(&sc->sc_io_rman, 0x100, 0xffff) != 0) {
286 panic("gt_pci_attach: failed to set up I/O rman");
289 /* Use KSEG1 to access PCI memory for it is uncached */
290 sc->sc_mem = MALTA_PCIMEM1_BASE;
291 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
292 sc->sc_mem_rman.rm_descr = "GT64120 PCI Memory";
293 if (rman_init(&sc->sc_mem_rman) != 0 ||
294 rman_manage_region(&sc->sc_mem_rman,
295 sc->sc_mem, sc->sc_mem + MALTA_PCIMEM1_SIZE) != 0) {
296 panic("gt_pci_attach: failed to set up memory rman");
298 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
299 sc->sc_irq_rman.rm_descr = "GT64120 PCI IRQs";
300 if (rman_init(&sc->sc_irq_rman) != 0 ||
301 rman_manage_region(&sc->sc_irq_rman, 1, 31) != 0)
302 panic("gt_pci_attach: failed to set up IRQ rman");
305 * Map the PIC/ELCR registers.
308 if (bus_space_map(sc->sc_st, 0x4d0, 2, 0, &sc->sc_ioh_elcr) != 0)
309 device_printf(dev, "unable to map ELCR registers\n");
310 if (bus_space_map(sc->sc_st, IO_ICU1, 2, 0, &sc->sc_ioh_icu1) != 0)
311 device_printf(dev, "unable to map ICU1 registers\n");
312 if (bus_space_map(sc->sc_st, IO_ICU2, 2, 0, &sc->sc_ioh_icu2) != 0)
313 device_printf(dev, "unable to map ICU2 registers\n");
315 sc->sc_ioh_elcr = MIPS_PHYS_TO_KSEG1(sc->sc_io + 0x4d0);
316 sc->sc_ioh_icu1 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU1);
317 sc->sc_ioh_icu2 = MIPS_PHYS_TO_KSEG1(sc->sc_io + IO_ICU2);
321 /* All interrupts default to "masked off". */
322 sc->sc_imask = 0xffff;
324 /* All interrupts default to edge-triggered. */
328 * Initialize the 8259s.
330 /* reset, program device, 4 bytes */
331 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
332 ICW1_RESET | ICW1_IC4);
334 * XXX: values from NetBSD's <dev/ic/i8259reg.h>
336 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
338 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
340 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
343 /* mask all interrupts */
344 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 1,
345 sc->sc_imask & 0xff);
347 /* enable special mask mode */
348 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
349 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
351 /* read IRR by default */
352 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu1, 0,
355 /* reset, program device, 4 bytes */
356 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
357 ICW1_RESET | ICW1_IC4);
358 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
360 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
362 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
365 /* mask all interrupts */
366 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 1,
367 sc->sc_imask & 0xff);
369 /* enable special mask mode */
370 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
371 OCW3_SEL | OCW3_ESMM | OCW3_SMM);
373 /* read IRR by default */
374 bus_space_write_1(sc->sc_st, sc->sc_ioh_icu2, 0,
378 * Default all interrupts to edge-triggered.
380 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 0,
382 bus_space_write_1(sc->sc_st, sc->sc_ioh_elcr, 1,
383 (sc->sc_elcr >> 8) & 0xff);
386 * Some ISA interrupts are reserved for devices that
387 * we know are hard-wired to certain IRQs.
390 (1U << 0) | /* timer */
391 (1U << 1) | /* keyboard controller (keyboard) */
392 (1U << 2) | /* PIC cascade */
393 (1U << 3) | /* COM 2 */
394 (1U << 4) | /* COM 1 */
395 (1U << 6) | /* floppy */
396 (1U << 7) | /* centronics */
397 (1U << 8) | /* RTC */
398 (1U << 9) | /* I2C */
399 (1U << 12) | /* keyboard controller (mouse) */
400 (1U << 14) | /* IDE primary */
401 (1U << 15); /* IDE secondary */
403 /* Hook up our interrupt handler. */
404 if ((sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
405 MALTA_SOUTHBRIDGE_INTR, MALTA_SOUTHBRIDGE_INTR, 1,
406 RF_SHAREABLE | RF_ACTIVE)) == NULL) {
407 device_printf(dev, "unable to allocate IRQ resource\n");
411 if ((bus_setup_intr(dev, sc->sc_irq, INTR_TYPE_MISC,
412 gt_pci_intr, NULL, sc, &sc->sc_ih))) {
414 "WARNING: unable to register interrupt handler\n");
418 /* Initialize memory and i/o rmans. */
419 device_add_child(dev, "pci", -1);
420 return (bus_generic_attach(dev));
424 gt_pci_maxslots(device_t dev)
426 return (PCI_SLOTMAX);
430 gt_pci_conf_setup(struct gt_pci_softc *sc, int bus, int slot, int func,
431 int reg, uint32_t *addr)
433 *addr = (bus << 16) | (slot << 11) | (func << 8) | reg;
439 gt_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
442 struct gt_pci_softc *sc = device_get_softc(dev);
445 uint32_t shift, mask;
447 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
448 return (uint32_t)(-1);
450 /* Clear cause register bits. */
451 GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
452 GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
454 * Galileo system controller is special
456 if ((bus == 0) && (slot == 0))
457 data = GT_PCI_DATA(GT_REGVAL(GT_PCI0_CFG_DATA));
459 data = GT_REGVAL(GT_PCI0_CFG_DATA);
461 /* Check for master abort. */
462 if (GT_HOST_DATA(GT_REGVAL(GT_INTR_CAUSE)) & (GTIC_MASABORT0 | GTIC_TARABORT0))
463 data = (uint32_t) -1;
485 data = (data >> shift) & mask;
492 data = (data >> 16) & mask;
497 panic("gt_pci_readconfig: wrong bytes count");
501 printf("PCICONF_READ(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
502 bus, slot, func, reg, data, bytes);
509 gt_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func, u_int reg,
510 uint32_t data, int bytes)
512 struct gt_pci_softc *sc = device_get_softc(dev);
515 uint32_t shift, mask;
519 reg_data = gt_pci_read_config(dev, bus, slot, func, reg, 4);
521 shift = 8 * (reg & 3);
527 data = (reg_data & ~ (mask << shift)) | (data << shift);
532 data = (reg_data & ~mask) | data;
534 data = (reg_data & ~ (mask << shift)) |
540 panic("gt_pci_readconfig: wrong bytes count");
545 if (gt_pci_conf_setup(sc, bus, slot, func, reg & ~3, &addr))
548 /* The galileo has problems accessing device 31. */
549 if (bus == 0 && slot == 31)
552 /* XXX: no support for bus > 0 yet */
556 /* Clear cause register bits. */
557 GT_REGVAL(GT_INTR_CAUSE) = GT_PCI_DATA(0);
559 GT_REGVAL(GT_PCI0_CFG_ADDR) = GT_PCI_DATA((1U << 31) | addr);
562 * Galileo system controller is special
564 if ((bus == 0) && (slot == 0))
565 GT_REGVAL(GT_PCI0_CFG_DATA) = GT_PCI_DATA(data);
567 GT_REGVAL(GT_PCI0_CFG_DATA) = data;
570 printf("PCICONF_WRITE(%02x:%02x.%02x[%04x] -> %02x(%d)\n",
571 bus, slot, func, reg, data, bytes);
577 gt_pci_route_interrupt(device_t pcib, device_t dev, int pin)
582 /* struct gt_pci_softc *sc = device_get_softc(pcib); */
583 bus = pci_get_bus(dev);
584 device = pci_get_slot(dev);
585 func = pci_get_function(dev);
587 * XXXMIPS: We need routing logic. This is just a stub .
591 * PIIX4 IDE adapter. HW IRQ0
594 case 11: /* Ethernet */
597 device_printf(pcib, "no IRQ mapping for %d/%d/%d/%d\n", bus, device, func, pin);
605 gt_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
607 struct gt_pci_softc *sc = device_get_softc(dev);
609 case PCIB_IVAR_DOMAIN:
613 *result = sc->sc_busno;
621 gt_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
623 struct gt_pci_softc * sc = device_get_softc(dev);
627 sc->sc_busno = result;
633 static struct resource *
634 gt_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
635 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
637 struct gt_pci_softc *sc = device_get_softc(bus);
638 struct resource *rv = NULL;
640 bus_space_handle_t bh = 0;
644 rm = &sc->sc_irq_rman;
647 rm = &sc->sc_mem_rman;
651 rm = &sc->sc_io_rman;
658 rv = rman_reserve_resource(rm, start, end, count, flags, child);
661 rman_set_rid(rv, *rid);
662 if (type != SYS_RES_IRQ) {
663 bh += (rman_get_start(rv));
665 rman_set_bustag(rv, gt_pci_bus_space);
666 rman_set_bushandle(rv, bh);
667 if (flags & RF_ACTIVE) {
668 if (bus_activate_resource(child, type, *rid, rv)) {
669 rman_release_resource(rv);
678 gt_pci_activate_resource(device_t bus, device_t child, int type, int rid,
681 bus_space_handle_t p;
684 if ((type == SYS_RES_MEMORY) || (type == SYS_RES_IOPORT)) {
685 error = bus_space_map(rman_get_bustag(r),
686 rman_get_bushandle(r), rman_get_size(r), 0, &p);
689 rman_set_bushandle(r, p);
691 return (rman_activate_resource(r));
695 gt_pci_setup_intr(device_t dev, device_t child, struct resource *ires,
696 int flags, driver_filter_t *filt, driver_intr_t *handler,
697 void *arg, void **cookiep)
699 struct gt_pci_softc *sc = device_get_softc(dev);
700 struct intr_event *event;
703 irq = rman_get_start(ires);
704 if (irq >= ICU_LEN || irq == 2)
705 panic("%s: bad irq or type", __func__);
707 event = sc->sc_eventstab[irq];
708 sc->sc_intr_cookies[irq].irq = irq;
709 sc->sc_intr_cookies[irq].sc = sc;
711 error = intr_event_create(&event,
712 (void *)&sc->sc_intr_cookies[irq], 0, irq,
713 gt_pci_mask_irq, gt_pci_unmask_irq,
714 NULL, NULL, "gt_pci intr%d:", irq);
717 sc->sc_eventstab[irq] = event;
720 intr_event_add_handler(event, device_get_nameunit(child), filt,
721 handler, arg, intr_priority(flags), flags, cookiep);
723 gt_pci_unmask_irq((void *)&sc->sc_intr_cookies[irq]);
728 gt_pci_teardown_intr(device_t dev, device_t child, struct resource *res,
731 struct gt_pci_softc *sc = device_get_softc(dev);
734 irq = rman_get_start(res);
735 gt_pci_mask_irq((void *)&sc->sc_intr_cookies[irq]);
737 return (intr_event_remove_handler(cookie));
740 static device_method_t gt_pci_methods[] = {
741 /* Device interface */
742 DEVMETHOD(device_probe, gt_pci_probe),
743 DEVMETHOD(device_attach, gt_pci_attach),
744 DEVMETHOD(device_shutdown, bus_generic_shutdown),
745 DEVMETHOD(device_suspend, bus_generic_suspend),
746 DEVMETHOD(device_resume, bus_generic_resume),
749 DEVMETHOD(bus_read_ivar, gt_read_ivar),
750 DEVMETHOD(bus_write_ivar, gt_write_ivar),
751 DEVMETHOD(bus_alloc_resource, gt_pci_alloc_resource),
752 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
753 DEVMETHOD(bus_activate_resource, gt_pci_activate_resource),
754 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
755 DEVMETHOD(bus_setup_intr, gt_pci_setup_intr),
756 DEVMETHOD(bus_teardown_intr, gt_pci_teardown_intr),
759 DEVMETHOD(pcib_maxslots, gt_pci_maxslots),
760 DEVMETHOD(pcib_read_config, gt_pci_read_config),
761 DEVMETHOD(pcib_write_config, gt_pci_write_config),
762 DEVMETHOD(pcib_route_interrupt, gt_pci_route_interrupt),
763 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
768 static driver_t gt_pci_driver = {
771 sizeof(struct gt_pci_softc),
774 static devclass_t gt_pci_devclass;
776 DRIVER_MODULE(gt_pci, gt, gt_pci_driver, gt_pci_devclass, 0, 0);