1 /* $NetBSD: gtreg.h,v 1.2 2005/12/24 20:07:03 perry Exp $ */
4 * Copyright (c) 1997, 1998, 2001 The NetBSD Foundation, Inc.
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
9 * NASA Ames Research Center.
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12 * modification, are permitted provided that the following conditions
14 * 1. Redistributions of source code must retain the above copyright
15 * notice, this list of conditions and the following disclaimer.
16 * 2. Redistributions in binary form must reproduce the above copyright
17 * notice, this list of conditions and the following disclaimer in the
18 * documentation and/or other materials provided with the distribution.
19 * 3. All advertising materials mentioning features or use of this software
20 * must display the following acknowledgement:
21 * This product includes software developed by the NetBSD
22 * Foundation, Inc. and its contributors.
23 * 4. Neither the name of The NetBSD Foundation nor the names of its
24 * contributors may be used to endorse or promote products derived
25 * from this software without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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44 #define GT_REGVAL(x) *((volatile u_int32_t *) \
45 (MIPS_PHYS_TO_KSEG1(MALTA_CORECTRL_BASE + (x))))
47 /* CPU Configuration Register Map */
48 #define GT_CPU_INT 0x000
49 #define GT_MULTIGT 0x120
51 /* CPU Address Decode Register Map */
53 /* CPU Error Report Register Map */
55 /* CPU Sync Barrier Register Map */
57 /* SDRAM and Device Address Decode Register Map */
59 /* SDRAM Configuration Register Map */
61 /* SDRAM Parameters Register Map */
63 /* ECC Register Map */
65 /* Device Parameters Register Map */
67 /* DMA Record Register Map */
69 /* DMA Arbiter Register Map */
71 /* Timer/Counter Register Map */
72 //#define GT_TC_0 0x850
73 //#define GT_TC_1 0x854
74 //#define GT_TC_2 0x858
75 //#define GT_TC_3 0x85c
76 //#define GT_TC_CONTROL 0x864
78 /* PCI Internal Register Map */
79 #define GT_PCI0_CFG_ADDR 0xcf8
80 #define GT_PCI0_CFG_DATA 0xcfc
81 #define GT_PCI0_INTR_ACK 0xc34
83 /* Interrupts Register Map */
84 #define GT_INTR_CAUSE 0xc18
85 #define GTIC_INTSUM 0x00000001
86 #define GTIC_MEMOUT 0x00000002
87 #define GTIC_DMAOUT 0x00000004
88 #define GTIC_CPUOUT 0x00000008
89 #define GTIC_DMA0COMP 0x00000010
90 #define GTIC_DMA1COMP 0x00000020
91 #define GTIC_DMA2COMP 0x00000040
92 #define GTIC_DMA3COMP 0x00000080
93 #define GTIC_T0EXP 0x00000100
94 #define GTIC_T1EXP 0x00000200
95 #define GTIC_T2EXP 0x00000400
96 #define GTIC_T3EXP 0x00000800
97 #define GTIC_MASRDERR0 0x00001000
98 #define GTIC_SLVWRERR0 0x00002000
99 #define GTIC_MASWRERR0 0x00004000
100 #define GTIC_SLVRDERR0 0x00008000
101 #define GTIC_ADDRERR0 0x00010000
102 #define GTIC_MEMERR 0x00020000
103 #define GTIC_MASABORT0 0x00040000
104 #define GTIC_TARABORT0 0x00080000
105 #define GTIC_RETRYCNT0 0x00100000
106 #define GTIC_PMCINT_0 0x00200000
107 #define GTIC_CPUINT 0x0c300000
108 #define GTIC_PCINT 0xc3000000
109 #define GTIC_CPUINTSUM 0x40000000
110 #define GTIC_PCIINTSUM 0x80000000
112 /* PCI Configuration Register Map */
113 //#define GT_PCICONFIGBASE 0
114 //#define GT_PCIDID BONITO(GT_PCICONFIGBASE + 0x00)
115 //#define GT_PCICMD BONITO(GT_PCICONFIGBASE + 0x04)
116 //#define GT_PCICLASS BONITO(GT_PCICONFIGBASE + 0x08)
117 //#define GT_PCILTIMER BONITO(GT_PCICONFIGBASE + 0x0c)
118 //#define GT_PCIBASE0 BONITO(GT_PCICONFIGBASE + 0x10)
119 //#define GT_PCIBASE1 BONITO(GT_PCICONFIGBASE + 0x14)
120 //#define GT_PCIBASE2 BONITO(GT_PCICONFIGBASE + 0x18)
121 //#define GT_PCIEXPRBASE BONITO(GT_PCICONFIGBASE + 0x30)
122 //#define GT_PCIINT BONITO(GT_PCICONFIGBASE + 0x3c)
124 /* PCI Configuration, Function 1, Register Map */
126 /* I2O Support Register Map */