2 * Copyright (c) 2016 Ruslan Bukin <br@bsdpad.com>
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
42 #include <sys/kernel.h>
44 #include <sys/systm.h>
46 #include <machine/cpufunc.h>
47 #include <machine/hwfunc.h>
48 #include <machine/md_var.h>
49 #include <machine/smp.h>
51 #define MALTA_MAXCPU 2
52 #define VPECONF0_VPA (1 << 0)
53 #define MVPCONTROL_VPC (1 << 1)
54 #define TCSTATUS_A (1 << 13)
56 unsigned malta_ap_boot = ~0;
58 #define C_SW0 (1 << 8)
59 #define C_SW1 (1 << 9)
60 #define C_IRQ0 (1 << 10)
61 #define C_IRQ1 (1 << 11)
62 #define C_IRQ2 (1 << 12)
63 #define C_IRQ3 (1 << 13)
64 #define C_IRQ4 (1 << 14)
65 #define C_IRQ5 (1 << 15)
75 " .word 0x41600021 # evpe \n"
89 #define mttc0(rd, sel, val) \
96 " .word 0x41810000 | (" #rd " << 11) | " #sel " \n" \
101 #define mftc0(rt, sel) \
103 unsigned long __res; \
106 " .set mips32r2 \n" \
108 " .word 0x41000800 | (" #rt " << 16) | " #sel " \n" \
115 #define write_c0_register32(reg, sel, val) \
120 " mtc0 %0, $%1, %2 \n" \
122 :: "r" (val), "i" (reg), "i" (sel)); \
125 #define read_c0_register32(reg, sel) \
131 " mfc0 %0, $%1, %2 \n" \
133 : "=r" (__retval) : "i" (reg), "i" (sel)); \
138 set_thread_context(int cpuid)
142 reg = read_c0_register32(1, 1);
145 write_c0_register32(1, 1, reg);
151 platform_ipi_send(int cpuid)
155 set_thread_context(cpuid);
164 platform_ipi_clear(void)
168 reg = mips_rd_cause();
174 platform_ipi_hardintr_num(void)
181 platform_ipi_softintr_num(void)
188 platform_init_ap(int cpuid)
190 uint32_t clock_int_mask;
191 uint32_t ipi_intr_mask;
194 * Clear any pending IPIs.
196 platform_ipi_clear();
199 * Unmask the clock and ipi interrupts.
201 ipi_intr_mask = soft_int_mask(platform_ipi_softintr_num());
202 clock_int_mask = hard_int_mask(5);
203 set_intr_mask(ipi_intr_mask | clock_int_mask);
209 platform_cpu_mask(cpuset_t *mask)
214 for (i = 0, m = 1 ; i < MALTA_MAXCPU; i++, m <<= 1)
219 platform_smp_topo(void)
222 return (smp_topo_none());
226 platform_start_ap(int cpuid)
231 /* Enter into configuration */
232 reg = read_c0_register32(0, 1);
233 reg |= (MVPCONTROL_VPC);
234 write_c0_register32(0, 1, reg);
236 set_thread_context(cpuid);
239 * Hint: how to set entry point.
249 /* Unhalt CPU core */
254 reg |= (VPECONF0_VPA);
257 /* Out of configuration */
258 reg = read_c0_register32(0, 1);
259 reg &= ~(MVPCONTROL_VPC);
260 write_c0_register32(0, 1, reg);
264 if (atomic_cmpset_32(&malta_ap_boot, ~0, cpuid) == 0)
267 printf("Waiting for cpu%d to start\n", cpuid);
272 if (atomic_cmpset_32(&malta_ap_boot, 0, ~0) != 0) {
273 printf("CPU %d started\n", cpuid);
278 printf("CPU %d failed to start\n", cpuid);