2 * Copyright 2016 Stanislav Galabov
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include "opt_platform.h"
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/resource.h>
44 #include <machine/bus.h>
45 #include <machine/intr.h>
47 #include <mips/mediatek/mtk_soc.h>
49 #include <dev/gpio/gpiobusvar.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include <gnu/dts/include/dt-bindings/interrupt-controller/irq.h>
60 #define MTK_GPIO_PINS 32
62 struct mtk_gpio_pin_irqsrc {
63 struct intr_irqsrc isrc;
70 enum intr_trigger intr_trigger;
71 enum intr_polarity intr_polarity;
72 char pin_name[GPIOMAXNAME];
73 struct mtk_gpio_pin_irqsrc pin_irqsrc;
76 struct mtk_gpio_softc {
79 struct resource *res[2];
81 struct mtk_gpio_pin pins[MTK_GPIO_PINS];
88 #define PIC_INTR_ISRC(sc, irq) (&(sc)->pins[(irq)].pin_irqsrc.isrc)
90 static struct resource_spec mtk_gpio_spec[] = {
91 { SYS_RES_MEMORY, 0, RF_ACTIVE },
92 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
96 static int mtk_gpio_probe(device_t dev);
97 static int mtk_gpio_attach(device_t dev);
98 static int mtk_gpio_detach(device_t dev);
99 static int mtk_gpio_intr(void *arg);
101 #define MTK_GPIO_LOCK(sc) mtx_lock_spin(&(sc)->mtx)
102 #define MTK_GPIO_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx)
103 #define MTK_GPIO_LOCK_INIT(sc) \
104 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
105 "mtk_gpio", MTX_SPIN)
106 #define MTK_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
108 #define MTK_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
109 #define MTK_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
111 /* Register definitions */
112 #define GPIO_PIOINT(_sc) 0x0000
113 #define GPIO_PIOEDGE(_sc) 0x0004
114 #define GPIO_PIORENA(_sc) 0x0008
115 #define GPIO_PIOFENA(_sc) 0x000C
116 #define GPIO_PIODATA(_sc) ((_sc)->do_remap ? 0x0020 : 0x0010)
117 #define GPIO_PIODIR(_sc) ((_sc)->do_remap ? 0x0024 : 0x0014)
118 #define GPIO_PIOPOL(_sc) ((_sc)->do_remap ? 0x0028 : 0x0018)
119 #define GPIO_PIOSET(_sc) ((_sc)->do_remap ? 0x002C : 0x001C)
120 #define GPIO_PIORESET(_sc) ((_sc)->do_remap ? 0x0030 : 0x0020)
121 #define GPIO_PIOTOG(_sc) ((_sc)->do_remap ? 0x0034 : 0x0024)
123 static struct ofw_compat_data compat_data[] = {
124 { "ralink,rt2880-gpio", 1 },
125 { "ralink,rt3050-gpio", 1 },
126 { "ralink,rt3352-gpio", 1 },
127 { "ralink,rt3883-gpio", 1 },
128 { "ralink,rt5350-gpio", 1 },
129 { "ralink,mt7620a-gpio", 1 },
134 mtk_gpio_probe(device_t dev)
138 if (!ofw_bus_status_okay(dev))
141 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
144 node = ofw_bus_get_node(dev);
145 if (!OF_hasprop(node, "gpio-controller"))
148 device_set_desc(dev, "MTK GPIO Controller (v1)");
150 return (BUS_PROBE_DEFAULT);
154 mtk_pic_register_isrcs(struct mtk_gpio_softc *sc)
158 struct intr_irqsrc *isrc;
161 name = device_get_nameunit(sc->dev);
162 for (irq = 0; irq < sc->num_pins; irq++) {
163 sc->pins[irq].pin_irqsrc.irq = irq;
164 isrc = PIC_INTR_ISRC(sc, irq);
165 error = intr_isrc_register(isrc, sc->dev, 0, "%s", name);
167 /* XXX call intr_isrc_deregister */
168 device_printf(sc->dev, "%s failed", __func__);
177 mtk_gpio_pin_set_direction(struct mtk_gpio_softc *sc, uint32_t pin,
180 uint32_t regval, mask = (1u << pin);
182 if (!(sc->pins[pin].pin_caps & dir))
185 regval = MTK_READ_4(sc, GPIO_PIODIR(sc));
186 if (dir == GPIO_PIN_INPUT)
190 MTK_WRITE_4(sc, GPIO_PIODIR(sc), regval);
192 sc->pins[pin].pin_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
193 sc->pins[pin].pin_flags |= dir;
199 mtk_gpio_pin_set_invert(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t val)
201 uint32_t regval, mask = (1u << pin);
203 regval = MTK_READ_4(sc, GPIO_PIOPOL(sc));
208 MTK_WRITE_4(sc, GPIO_PIOPOL(sc), regval);
209 sc->pins[pin].pin_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
210 sc->pins[pin].pin_flags |= val;
216 mtk_gpio_pin_probe(struct mtk_gpio_softc *sc, uint32_t pin)
218 uint32_t mask = (1u << pin);
221 /* Clear cached gpio config */
222 sc->pins[pin].pin_flags = 0;
224 val = MTK_READ_4(sc, GPIO_PIORENA(sc)) |
225 MTK_READ_4(sc, GPIO_PIOFENA(sc));
227 /* Pin is in interrupt mode */
228 sc->pins[pin].intr_trigger = INTR_TRIGGER_EDGE;
229 val = MTK_READ_4(sc, GPIO_PIORENA(sc));
231 sc->pins[pin].intr_polarity = INTR_POLARITY_HIGH;
233 sc->pins[pin].intr_polarity = INTR_POLARITY_LOW;
236 val = MTK_READ_4(sc, GPIO_PIODIR(sc));
238 sc->pins[pin].pin_flags |= GPIO_PIN_OUTPUT;
240 sc->pins[pin].pin_flags |= GPIO_PIN_INPUT;
242 val = MTK_READ_4(sc, GPIO_PIOPOL(sc));
244 if (sc->pins[pin].pin_flags & GPIO_PIN_INPUT) {
245 sc->pins[pin].pin_flags |= GPIO_PIN_INVIN;
247 sc->pins[pin].pin_flags |= GPIO_PIN_INVOUT;
253 mtk_gpio_attach(device_t dev)
255 struct mtk_gpio_softc *sc;
257 uint32_t i, num_pins;
259 sc = device_get_softc(dev);
262 if (bus_alloc_resources(dev, mtk_gpio_spec, sc->res)) {
263 device_printf(dev, "could not allocate resources for device\n");
267 MTK_GPIO_LOCK_INIT(sc);
269 node = ofw_bus_get_node(dev);
271 if (OF_hasprop(node, "clocks"))
272 mtk_soc_start_clock(dev);
273 if (OF_hasprop(node, "resets"))
274 mtk_soc_reset_device(dev);
276 if (OF_hasprop(node, "mtk,register-gap")) {
277 device_printf(dev, "<register gap>\n");
280 device_printf(dev, "<no register gap>\n");
284 if (OF_hasprop(node, "ralink,num-gpios") && (OF_getencprop(node,
285 "ralink,num-gpios", &num_pins, sizeof(num_pins)) >= 0))
286 sc->num_pins = num_pins;
288 sc->num_pins = MTK_GPIO_PINS;
290 for (i = 0; i < num_pins; i++) {
291 sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
292 GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
293 sc->pins[i].intr_polarity = INTR_POLARITY_HIGH;
294 sc->pins[i].intr_trigger = INTR_TRIGGER_EDGE;
296 snprintf(sc->pins[i].pin_name, GPIOMAXNAME - 1, "gpio%c%d",
297 device_get_unit(dev) + 'a', i);
298 sc->pins[i].pin_name[GPIOMAXNAME - 1] = '\0';
300 mtk_gpio_pin_probe(sc, i);
303 if (mtk_pic_register_isrcs(sc) != 0) {
304 device_printf(dev, "could not register PIC ISRCs\n");
308 if (intr_pic_register(dev, OF_xref_from_node(node)) != 0) {
309 device_printf(dev, "could not register PIC\n");
313 if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
314 mtk_gpio_intr, NULL, sc, &sc->intrhand) != 0)
317 sc->busdev = gpiobus_attach_bus(dev);
318 if (sc->busdev == NULL)
323 intr_pic_deregister(dev, OF_xref_from_node(node));
325 if(sc->intrhand != NULL)
326 bus_teardown_intr(dev, sc->res[1], sc->intrhand);
327 bus_release_resources(dev, mtk_gpio_spec, sc->res);
328 MTK_GPIO_LOCK_DESTROY(sc);
333 mtk_gpio_detach(device_t dev)
335 struct mtk_gpio_softc *sc = device_get_softc(dev);
338 node = ofw_bus_get_node(dev);
339 intr_pic_deregister(dev, OF_xref_from_node(node));
340 if (sc->intrhand != NULL)
341 bus_teardown_intr(dev, sc->res[1], sc->intrhand);
342 bus_release_resources(dev, mtk_gpio_spec, sc->res);
343 MTK_GPIO_LOCK_DESTROY(sc);
348 mtk_gpio_get_bus(device_t dev)
350 struct mtk_gpio_softc *sc = device_get_softc(dev);
356 mtk_gpio_pin_max(device_t dev, int *maxpin)
358 struct mtk_gpio_softc *sc = device_get_softc(dev);
360 *maxpin = sc->num_pins - 1;
366 mtk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
368 struct mtk_gpio_softc *sc = device_get_softc(dev);
370 if (pin >= sc->num_pins)
374 *caps = sc->pins[pin].pin_caps;
381 mtk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
383 struct mtk_gpio_softc *sc = device_get_softc(dev);
385 if (pin >= sc->num_pins)
389 *flags = sc->pins[pin].pin_flags;
396 mtk_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
398 struct mtk_gpio_softc *sc = device_get_softc(dev);
400 if (pin >= sc->num_pins)
403 strncpy(name, sc->pins[pin].pin_name, GPIOMAXNAME - 1);
404 name[GPIOMAXNAME - 1] = '\0';
410 mtk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
412 struct mtk_gpio_softc *sc;
415 sc = device_get_softc(dev);
417 if (pin >= sc->num_pins)
421 retval = mtk_gpio_pin_set_direction(sc, pin,
422 flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT));
424 retval = mtk_gpio_pin_set_invert(sc, pin,
425 flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT));
432 mtk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
434 struct mtk_gpio_softc *sc;
437 sc = device_get_softc(dev);
440 if (pin >= sc->num_pins)
444 if(!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) {
450 MTK_WRITE_4(sc, GPIO_PIOSET(sc), (1u << pin));
452 MTK_WRITE_4(sc, GPIO_PIORESET(sc), (1u << pin));
460 mtk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
462 struct mtk_gpio_softc *sc;
466 sc = device_get_softc(dev);
469 if (pin >= sc->num_pins)
473 if(!(sc->pins[pin].pin_flags & GPIO_PIN_INPUT)) {
477 data = MTK_READ_4(sc, GPIO_PIODATA(sc));
478 *val = (data & (1u << pin)) ? 1 : 0;
486 mtk_gpio_pin_toggle(device_t dev, uint32_t pin)
488 struct mtk_gpio_softc *sc;
491 if (pin >= sc->num_pins)
494 sc = device_get_softc(dev);
498 if (!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) {
502 MTK_WRITE_4(sc, GPIO_PIOTOG(sc), (1u << pin));
511 mtk_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
512 struct intr_irqsrc **isrcp)
514 struct mtk_gpio_softc *sc;
516 sc = device_get_softc(dev);
518 if (data == NULL || data->type != INTR_MAP_DATA_FDT ||
519 data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->num_pins)
522 *isrcp = PIC_INTR_ISRC(sc, data->fdt.cells[0]);
527 mtk_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
529 struct mtk_gpio_softc *sc;
530 struct mtk_gpio_pin_irqsrc *pisrc;
531 uint32_t pin, mask, val;
533 sc = device_get_softc(dev);
535 pisrc = (struct mtk_gpio_pin_irqsrc *)isrc;
541 if (sc->pins[pin].intr_polarity == INTR_POLARITY_LOW) {
542 val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask;
543 MTK_WRITE_4(sc, GPIO_PIORENA(sc), val);
544 val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) | mask;
545 MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val);
547 val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask;
548 MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val);
549 val = MTK_READ_4(sc, GPIO_PIORENA(sc)) | mask;
550 MTK_WRITE_4(sc, GPIO_PIORENA(sc), val);
557 mtk_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
559 struct mtk_gpio_softc *sc;
560 struct mtk_gpio_pin_irqsrc *pisrc;
561 uint32_t pin, mask, val;
563 sc = device_get_softc(dev);
565 pisrc = (struct mtk_gpio_pin_irqsrc *)isrc;
571 val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask;
572 MTK_WRITE_4(sc, GPIO_PIORENA(sc), val);
573 val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask;
574 MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val);
580 mtk_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
583 mtk_gpio_pic_disable_intr(dev, isrc);
587 mtk_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
590 mtk_gpio_pic_enable_intr(dev, isrc);
594 mtk_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
596 struct mtk_gpio_softc *sc;
597 struct mtk_gpio_pin_irqsrc *pisrc;
599 pisrc = (struct mtk_gpio_pin_irqsrc *)isrc;
600 sc = device_get_softc(dev);
602 MTK_WRITE_4(sc, GPIO_PIOINT(sc), 1u << pisrc->irq);
607 mtk_gpio_intr(void *arg)
609 struct mtk_gpio_softc *sc;
610 uint32_t i, interrupts;
613 interrupts = MTK_READ_4(sc, GPIO_PIOINT(sc));
615 for (i = 0; interrupts != 0; i++, interrupts >>= 1) {
616 if ((interrupts & 0x1) == 0)
618 if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
619 curthread->td_intr_frame) != 0) {
620 device_printf(sc->dev, "spurious interrupt %d\n", i);
624 return (FILTER_HANDLED);
628 mtk_gpio_get_node(device_t bus, device_t dev)
631 /* We only have one child, the GPIO bus, which needs our own node. */
632 return (ofw_bus_get_node(bus));
635 static device_method_t mtk_gpio_methods[] = {
636 /* Device interface */
637 DEVMETHOD(device_probe, mtk_gpio_probe),
638 DEVMETHOD(device_attach, mtk_gpio_attach),
639 DEVMETHOD(device_detach, mtk_gpio_detach),
642 DEVMETHOD(gpio_get_bus, mtk_gpio_get_bus),
643 DEVMETHOD(gpio_pin_max, mtk_gpio_pin_max),
644 DEVMETHOD(gpio_pin_getname, mtk_gpio_pin_getname),
645 DEVMETHOD(gpio_pin_getflags, mtk_gpio_pin_getflags),
646 DEVMETHOD(gpio_pin_getcaps, mtk_gpio_pin_getcaps),
647 DEVMETHOD(gpio_pin_setflags, mtk_gpio_pin_setflags),
648 DEVMETHOD(gpio_pin_get, mtk_gpio_pin_get),
649 DEVMETHOD(gpio_pin_set, mtk_gpio_pin_set),
650 DEVMETHOD(gpio_pin_toggle, mtk_gpio_pin_toggle),
652 /* Interrupt controller interface */
653 DEVMETHOD(pic_disable_intr, mtk_gpio_pic_disable_intr),
654 DEVMETHOD(pic_enable_intr, mtk_gpio_pic_enable_intr),
655 DEVMETHOD(pic_map_intr, mtk_gpio_pic_map_intr),
656 DEVMETHOD(pic_post_filter, mtk_gpio_pic_post_filter),
657 DEVMETHOD(pic_post_ithread, mtk_gpio_pic_post_ithread),
658 DEVMETHOD(pic_pre_ithread, mtk_gpio_pic_pre_ithread),
660 /* ofw_bus interface */
661 DEVMETHOD(ofw_bus_get_node, mtk_gpio_get_node),
666 static driver_t mtk_gpio_driver = {
669 sizeof(struct mtk_gpio_softc),
672 static devclass_t mtk_gpio_devclass;
674 EARLY_DRIVER_MODULE(mtk_gpio_v1, simplebus, mtk_gpio_driver,
675 mtk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);