2 * Copyright 2016 Stanislav Galabov
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include "opt_platform.h"
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
39 #include <sys/mutex.h>
41 #include <sys/resource.h>
44 #include <machine/bus.h>
45 #include <machine/intr.h>
47 #include <mips/mediatek/mtk_soc.h>
49 #include <dev/gpio/gpiobusvar.h>
51 #include <dev/fdt/fdt_common.h>
52 #include <dev/ofw/ofw_bus.h>
53 #include <dev/ofw/ofw_bus_subr.h>
55 #include <gnu/dts/include/dt-bindings/interrupt-controller/irq.h>
60 #define MTK_GPIO_PINS 32
62 struct mtk_gpio_pin_irqsrc {
63 struct intr_irqsrc isrc;
70 enum intr_trigger intr_trigger;
71 enum intr_polarity intr_polarity;
72 char pin_name[GPIOMAXNAME];
73 struct mtk_gpio_pin_irqsrc pin_irqsrc;
76 struct mtk_gpio_softc {
79 struct resource *res[2];
81 struct mtk_gpio_pin pins[MTK_GPIO_PINS];
88 #define PIC_INTR_ISRC(sc, irq) (&(sc)->pins[(irq)].pin_irqsrc.isrc)
90 static struct resource_spec mtk_gpio_spec[] = {
91 { SYS_RES_MEMORY, 0, RF_ACTIVE | RF_SHAREABLE },
92 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
96 static int mtk_gpio_probe(device_t dev);
97 static int mtk_gpio_attach(device_t dev);
98 static int mtk_gpio_detach(device_t dev);
99 static int mtk_gpio_intr(void *arg);
101 #define MTK_GPIO_LOCK(sc) mtx_lock_spin(&(sc)->mtx)
102 #define MTK_GPIO_UNLOCK(sc) mtx_unlock_spin(&(sc)->mtx)
103 #define MTK_GPIO_LOCK_INIT(sc) \
104 mtx_init(&(sc)->mtx, device_get_nameunit((sc)->dev), \
105 "mtk_gpio", MTX_SPIN)
106 #define MTK_GPIO_LOCK_DESTROY(sc) mtx_destroy(&(sc)->mtx)
108 #define MTK_WRITE_4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
109 #define MTK_READ_4(sc, reg) bus_read_4((sc)->res[0], (reg))
111 /* Register definitions */
112 #define GPIO_REG(_sc, _reg) ((_reg) + (_sc)->bank_id * 0x4)
113 #define GPIO_PIOINT(_sc) GPIO_REG((_sc), 0x0090)
114 #define GPIO_PIOEDGE(_sc) GPIO_REG((_sc), 0x00A0)
115 #define GPIO_PIORENA(_sc) GPIO_REG((_sc), 0x0050)
116 #define GPIO_PIOFENA(_sc) GPIO_REG((_sc), 0x0060)
117 #define GPIO_PIODATA(_sc) GPIO_REG((_sc), 0x0020)
118 #define GPIO_PIODIR(_sc) GPIO_REG((_sc), 0x0000)
119 #define GPIO_PIOPOL(_sc) GPIO_REG((_sc), 0x0010)
120 #define GPIO_PIOSET(_sc) GPIO_REG((_sc), 0x0030)
121 #define GPIO_PIORESET(_sc) GPIO_REG((_sc), 0x0040)
123 static struct ofw_compat_data compat_data[] = {
124 { "mtk,mt7621-gpio-bank", 1 },
125 { "mtk,mt7628-gpio-bank", 1 },
130 mtk_gpio_probe(device_t dev)
134 if (!ofw_bus_status_okay(dev))
137 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
140 node = ofw_bus_get_node(dev);
141 if (!OF_hasprop(node, "gpio-controller"))
144 device_set_desc(dev, "MTK GPIO Controller (v2)");
146 return (BUS_PROBE_DEFAULT);
150 mtk_pic_register_isrcs(struct mtk_gpio_softc *sc)
154 struct intr_irqsrc *isrc;
157 name = device_get_nameunit(sc->dev);
158 for (irq = 0; irq < sc->num_pins; irq++) {
159 sc->pins[irq].pin_irqsrc.irq = irq;
160 isrc = PIC_INTR_ISRC(sc, irq);
161 error = intr_isrc_register(isrc, sc->dev, 0, "%s", name);
163 /* XXX call intr_isrc_deregister */
164 device_printf(sc->dev, "%s failed", __func__);
173 mtk_gpio_pin_set_direction(struct mtk_gpio_softc *sc, uint32_t pin,
176 uint32_t regval, mask = (1u << pin);
178 if (!(sc->pins[pin].pin_caps & dir))
181 regval = MTK_READ_4(sc, GPIO_PIODIR(sc));
182 if (dir == GPIO_PIN_INPUT)
186 MTK_WRITE_4(sc, GPIO_PIODIR(sc), regval);
188 sc->pins[pin].pin_flags &= ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT);
189 sc->pins[pin].pin_flags |= dir;
195 mtk_gpio_pin_set_invert(struct mtk_gpio_softc *sc, uint32_t pin, uint32_t val)
197 uint32_t regval, mask = (1u << pin);
199 regval = MTK_READ_4(sc, GPIO_PIOPOL(sc));
204 MTK_WRITE_4(sc, GPIO_PIOPOL(sc), regval);
205 sc->pins[pin].pin_flags &= ~(GPIO_PIN_INVIN | GPIO_PIN_INVOUT);
206 sc->pins[pin].pin_flags |= val;
212 mtk_gpio_pin_probe(struct mtk_gpio_softc *sc, uint32_t pin)
214 uint32_t mask = (1u << pin);
217 /* Clear cached gpio config */
218 sc->pins[pin].pin_flags = 0;
220 val = MTK_READ_4(sc, GPIO_PIORENA(sc)) |
221 MTK_READ_4(sc, GPIO_PIOFENA(sc));
223 /* Pin is in interrupt mode */
224 sc->pins[pin].intr_trigger = INTR_TRIGGER_EDGE;
225 val = MTK_READ_4(sc, GPIO_PIORENA(sc));
227 sc->pins[pin].intr_polarity = INTR_POLARITY_HIGH;
229 sc->pins[pin].intr_polarity = INTR_POLARITY_LOW;
232 val = MTK_READ_4(sc, GPIO_PIODIR(sc));
234 sc->pins[pin].pin_flags |= GPIO_PIN_OUTPUT;
236 sc->pins[pin].pin_flags |= GPIO_PIN_INPUT;
238 val = MTK_READ_4(sc, GPIO_PIOPOL(sc));
240 if (sc->pins[pin].pin_flags & GPIO_PIN_INPUT) {
241 sc->pins[pin].pin_flags |= GPIO_PIN_INVIN;
243 sc->pins[pin].pin_flags |= GPIO_PIN_INVOUT;
249 mtk_gpio_attach(device_t dev)
251 struct mtk_gpio_softc *sc;
253 uint32_t i, num_pins, bank_id;
255 sc = device_get_softc(dev);
258 if (bus_alloc_resources(dev, mtk_gpio_spec, sc->res)) {
259 device_printf(dev, "could not allocate resources for device\n");
263 MTK_GPIO_LOCK_INIT(sc);
265 node = ofw_bus_get_node(dev);
267 if (OF_hasprop(node, "clocks"))
268 mtk_soc_start_clock(dev);
269 if (OF_hasprop(node, "resets"))
270 mtk_soc_reset_device(dev);
272 if (OF_hasprop(node, "mtk,bank-id") && (OF_getencprop(node,
273 "mtk,bank-id", &bank_id, sizeof(bank_id)) >= 0))
274 sc->bank_id = bank_id;
276 sc->bank_id = device_get_unit(dev);
278 if (OF_hasprop(node, "mtk,num-pins") && (OF_getencprop(node,
279 "mtk,num-pins", &num_pins, sizeof(num_pins)) >= 0))
280 sc->num_pins = num_pins;
282 sc->num_pins = MTK_GPIO_PINS;
284 for (i = 0; i < sc->num_pins; i++) {
285 sc->pins[i].pin_caps |= GPIO_PIN_INPUT | GPIO_PIN_OUTPUT |
286 GPIO_PIN_INVIN | GPIO_PIN_INVOUT;
287 sc->pins[i].intr_polarity = INTR_POLARITY_HIGH;
288 sc->pins[i].intr_trigger = INTR_TRIGGER_EDGE;
290 snprintf(sc->pins[i].pin_name, GPIOMAXNAME - 1, "gpio%c%d",
291 device_get_unit(dev) + 'a', i);
292 sc->pins[i].pin_name[GPIOMAXNAME - 1] = '\0';
294 mtk_gpio_pin_probe(sc, i);
297 if (mtk_pic_register_isrcs(sc) != 0) {
298 device_printf(dev, "could not register PIC ISRCs\n");
302 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) {
303 device_printf(dev, "could not register PIC\n");
307 if (bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
308 mtk_gpio_intr, NULL, sc, &sc->intrhand) != 0)
311 sc->busdev = gpiobus_attach_bus(dev);
312 if (sc->busdev == NULL)
317 intr_pic_deregister(dev, OF_xref_from_node(node));
319 if(sc->intrhand != NULL)
320 bus_teardown_intr(dev, sc->res[1], sc->intrhand);
321 bus_release_resources(dev, mtk_gpio_spec, sc->res);
322 MTK_GPIO_LOCK_DESTROY(sc);
327 mtk_gpio_detach(device_t dev)
329 struct mtk_gpio_softc *sc = device_get_softc(dev);
332 node = ofw_bus_get_node(dev);
333 intr_pic_deregister(dev, OF_xref_from_node(node));
334 if (sc->intrhand != NULL)
335 bus_teardown_intr(dev, sc->res[1], sc->intrhand);
336 bus_release_resources(dev, mtk_gpio_spec, sc->res);
337 MTK_GPIO_LOCK_DESTROY(sc);
342 mtk_gpio_get_bus(device_t dev)
344 struct mtk_gpio_softc *sc = device_get_softc(dev);
350 mtk_gpio_pin_max(device_t dev, int *maxpin)
352 struct mtk_gpio_softc *sc = device_get_softc(dev);
354 *maxpin = sc->num_pins - 1;
360 mtk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
362 struct mtk_gpio_softc *sc = device_get_softc(dev);
364 if (pin >= sc->num_pins)
368 *caps = sc->pins[pin].pin_caps;
375 mtk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
377 struct mtk_gpio_softc *sc = device_get_softc(dev);
379 if (pin >= sc->num_pins)
383 *flags = sc->pins[pin].pin_flags;
390 mtk_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
392 struct mtk_gpio_softc *sc = device_get_softc(dev);
394 if (pin >= sc->num_pins)
397 strncpy(name, sc->pins[pin].pin_name, GPIOMAXNAME - 1);
398 name[GPIOMAXNAME - 1] = '\0';
404 mtk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
406 struct mtk_gpio_softc *sc;
409 sc = device_get_softc(dev);
411 if (pin >= sc->num_pins)
415 retval = mtk_gpio_pin_set_direction(sc, pin,
416 flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT));
418 retval = mtk_gpio_pin_set_invert(sc, pin,
419 flags & (GPIO_PIN_INVIN | GPIO_PIN_INVOUT));
426 mtk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
428 struct mtk_gpio_softc *sc;
431 sc = device_get_softc(dev);
434 if (pin >= sc->num_pins)
439 MTK_WRITE_4(sc, GPIO_PIOSET(sc), (1u << pin));
441 MTK_WRITE_4(sc, GPIO_PIORESET(sc), (1u << pin));
448 mtk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
450 struct mtk_gpio_softc *sc;
454 sc = device_get_softc(dev);
457 if (pin >= sc->num_pins)
461 data = MTK_READ_4(sc, GPIO_PIODATA(sc));
462 *val = (data & (1u << pin)) ? 1 : 0;
469 mtk_gpio_pin_toggle(device_t dev, uint32_t pin)
471 struct mtk_gpio_softc *sc;
475 sc = device_get_softc(dev);
478 if (pin >= sc->num_pins)
482 if(!(sc->pins[pin].pin_flags & GPIO_PIN_OUTPUT)) {
486 val = MTK_READ_4(sc, GPIO_PIODATA(sc));
489 MTK_WRITE_4(sc, GPIO_PIORESET(sc), (1u << pin));
491 MTK_WRITE_4(sc, GPIO_PIOSET(sc), (1u << pin));
500 mtk_gpio_pic_map_intr(device_t dev, struct intr_map_data *data,
501 struct intr_irqsrc **isrcp)
503 struct intr_map_data_fdt *daf;
504 struct mtk_gpio_softc *sc;
506 if (data->type != INTR_MAP_DATA_FDT)
509 sc = device_get_softc(dev);
510 daf = (struct intr_map_data_fdt *)data;
512 if (daf->ncells != 1 || daf->cells[0] >= sc->num_pins)
515 *isrcp = PIC_INTR_ISRC(sc, daf->cells[0]);
520 mtk_gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
522 struct mtk_gpio_softc *sc;
523 struct mtk_gpio_pin_irqsrc *pisrc;
524 uint32_t pin, mask, val;
526 sc = device_get_softc(dev);
528 pisrc = (struct mtk_gpio_pin_irqsrc *)isrc;
534 if (sc->pins[pin].intr_polarity == INTR_POLARITY_LOW) {
535 val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask;
536 MTK_WRITE_4(sc, GPIO_PIORENA(sc), val);
537 val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) | mask;
538 MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val);
540 val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask;
541 MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val);
542 val = MTK_READ_4(sc, GPIO_PIORENA(sc)) | mask;
543 MTK_WRITE_4(sc, GPIO_PIORENA(sc), val);
550 mtk_gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
552 struct mtk_gpio_softc *sc;
553 struct mtk_gpio_pin_irqsrc *pisrc;
554 uint32_t pin, mask, val;
556 sc = device_get_softc(dev);
558 pisrc = (struct mtk_gpio_pin_irqsrc *)isrc;
564 val = MTK_READ_4(sc, GPIO_PIORENA(sc)) & ~mask;
565 MTK_WRITE_4(sc, GPIO_PIORENA(sc), val);
566 val = MTK_READ_4(sc, GPIO_PIOFENA(sc)) & ~mask;
567 MTK_WRITE_4(sc, GPIO_PIOFENA(sc), val);
573 mtk_gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
576 mtk_gpio_pic_disable_intr(dev, isrc);
580 mtk_gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
583 mtk_gpio_pic_enable_intr(dev, isrc);
587 mtk_gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
589 struct mtk_gpio_softc *sc;
590 struct mtk_gpio_pin_irqsrc *pisrc;
592 pisrc = (struct mtk_gpio_pin_irqsrc *)isrc;
593 sc = device_get_softc(dev);
595 MTK_WRITE_4(sc, GPIO_PIOINT(sc), 1u << pisrc->irq);
600 mtk_gpio_intr(void *arg)
602 struct mtk_gpio_softc *sc;
603 uint32_t i, interrupts;
606 interrupts = MTK_READ_4(sc, GPIO_PIOINT(sc));
608 for (i = 0; interrupts != 0; i++, interrupts >>= 1) {
609 if ((interrupts & 0x1) == 0)
611 if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
612 curthread->td_intr_frame) != 0) {
613 device_printf(sc->dev, "spurious interrupt %d\n", i);
617 return (FILTER_HANDLED);
621 mtk_gpio_get_node(device_t bus, device_t dev)
624 /* We only have one child, the GPIO bus, which needs our own node. */
625 return (ofw_bus_get_node(bus));
628 static device_method_t mtk_gpio_methods[] = {
629 /* Device interface */
630 DEVMETHOD(device_probe, mtk_gpio_probe),
631 DEVMETHOD(device_attach, mtk_gpio_attach),
632 DEVMETHOD(device_detach, mtk_gpio_detach),
635 DEVMETHOD(gpio_get_bus, mtk_gpio_get_bus),
636 DEVMETHOD(gpio_pin_max, mtk_gpio_pin_max),
637 DEVMETHOD(gpio_pin_getname, mtk_gpio_pin_getname),
638 DEVMETHOD(gpio_pin_getflags, mtk_gpio_pin_getflags),
639 DEVMETHOD(gpio_pin_getcaps, mtk_gpio_pin_getcaps),
640 DEVMETHOD(gpio_pin_setflags, mtk_gpio_pin_setflags),
641 DEVMETHOD(gpio_pin_get, mtk_gpio_pin_get),
642 DEVMETHOD(gpio_pin_set, mtk_gpio_pin_set),
643 DEVMETHOD(gpio_pin_toggle, mtk_gpio_pin_toggle),
645 /* Interrupt controller interface */
646 DEVMETHOD(pic_disable_intr, mtk_gpio_pic_disable_intr),
647 DEVMETHOD(pic_enable_intr, mtk_gpio_pic_enable_intr),
648 DEVMETHOD(pic_map_intr, mtk_gpio_pic_map_intr),
649 DEVMETHOD(pic_post_filter, mtk_gpio_pic_post_filter),
650 DEVMETHOD(pic_post_ithread, mtk_gpio_pic_post_ithread),
651 DEVMETHOD(pic_pre_ithread, mtk_gpio_pic_pre_ithread),
653 /* ofw_bus interface */
654 DEVMETHOD(ofw_bus_get_node, mtk_gpio_get_node),
659 static driver_t mtk_gpio_driver = {
662 sizeof(struct mtk_gpio_softc),
665 static devclass_t mtk_gpio_devclass;
667 EARLY_DRIVER_MODULE(mtk_gpio_v2, simplebus, mtk_gpio_driver,
668 mtk_gpio_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);