2 * Copyright (c) 2004 Juli Mallett. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/kernel.h>
32 #include <sys/module.h>
33 #include <sys/stdint.h>
37 #include <sys/sysctl.h>
38 #include <sys/systm.h>
41 #include <vm/vm_page.h>
43 #include <machine/cache.h>
44 #include <machine/cpufunc.h>
45 #include <machine/cpuinfo.h>
46 #include <machine/cpuregs.h>
47 #include <machine/intr_machdep.h>
48 #include <machine/locore.h>
49 #include <machine/pte.h>
50 #include <machine/tlb.h>
51 #include <machine/hwfunc.h>
53 #if defined(CPU_CNMIPS)
54 #include <contrib/octeon-sdk/cvmx.h>
55 #include <contrib/octeon-sdk/octeon-model.h>
58 static void cpu_identify(void);
60 struct mips_cpuinfo cpuinfo;
63 * Attempt to identify the MIPS CPU as much as possible.
65 * XXX: Assumes the CPU is MIPS{32,64}{,r2} compliant.
66 * XXX: For now, skip config register selections 2 and 3
67 * as we don't currently use L2/L3 cache or additional
68 * MIPS32 processor features.
71 mips_get_identity(struct mips_cpuinfo *cpuinfo)
76 #if defined(CPU_CNMIPS)
81 memset(cpuinfo, 0, sizeof(struct mips_cpuinfo));
83 /* Read and store the PrID ID for CPU identification. */
84 prid = mips_rd_prid();
85 cpuinfo->cpu_vendor = MIPS_PRID_CID(prid);
86 cpuinfo->cpu_rev = MIPS_PRID_REV(prid);
87 cpuinfo->cpu_impl = MIPS_PRID_IMPL(prid);
89 /* Read config register selection 0 to learn TLB type. */
90 cfg0 = mips_rd_config();
93 ((cfg0 & MIPS_CONFIG0_MT_MASK) >> MIPS_CONFIG0_MT_SHIFT);
94 cpuinfo->icache_virtual = cfg0 & MIPS_CONFIG0_VI;
96 /* If config register selection 1 does not exist, exit. */
97 if (!(cfg0 & MIPS_CONFIG_CM))
100 /* Learn TLB size and L1 cache geometry. */
101 cfg1 = mips_rd_config1();
104 /* Account for Extended TLB entries in XLP */
105 tmp = mips_rd_config6();
106 cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1;
107 #elif defined(BERI_LARGE_TLB)
108 /* Check if we support extended TLB entries and if so activate. */
109 tmp = mips_rd_config5();
110 #define BERI_CP5_LTLB_SUPPORTED 0x1
111 if (tmp & BERI_CP5_LTLB_SUPPORTED) {
112 /* See how many extra TLB entries we have. */
113 tmp = mips_rd_config6();
114 cpuinfo->tlb_nentries = (tmp >> 16) + 1;
115 /* Activate the extended entries. */
116 mips_wr_config6(tmp|0x4);
119 #if !defined(CPU_NLM)
120 cpuinfo->tlb_nentries =
121 ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1;
123 #if defined(CPU_CNMIPS)
124 /* Add extended TLB size information from config4. */
125 cfg4 = mips_rd_config4();
126 if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT)
127 cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40;
130 /* L1 instruction cache. */
131 tmp = (cfg1 & MIPS_CONFIG1_IL_MASK) >> MIPS_CONFIG1_IL_SHIFT;
133 cpuinfo->l1.ic_linesize = 1 << (tmp + 1);
134 cpuinfo->l1.ic_nways = (((cfg1 & MIPS_CONFIG1_IA_MASK) >> MIPS_CONFIG1_IA_SHIFT)) + 1;
135 cpuinfo->l1.ic_nsets =
136 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6);
141 tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT;
143 cpuinfo->l1.dc_linesize = 1 << (tmp + 1);
144 cpuinfo->l1.dc_nways =
145 (((cfg1 & MIPS_CONFIG1_DA_MASK) >> MIPS_CONFIG1_DA_SHIFT)) + 1;
146 cpuinfo->l1.dc_nsets =
147 1 << (((cfg1 & MIPS_CONFIG1_DS_MASK) >> MIPS_CONFIG1_DS_SHIFT) + 6);
151 * Some Octeon cache configuration parameters are by model family, not
154 if (OCTEON_IS_MODEL(OCTEON_CN3XXX)) {
155 /* Octeon and Octeon XL. */
156 cpuinfo->l1.dc_nsets = 1;
157 cpuinfo->l1.dc_nways = 64;
158 } else if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
160 cpuinfo->l1.dc_nsets = 2;
161 cpuinfo->l1.dc_nways = 64;
162 } else if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
164 cpuinfo->l1.dc_nsets = 8;
165 cpuinfo->l1.dc_nways = 32;
167 cpuinfo->l1.ic_nsets = 8;
168 cpuinfo->l1.ic_nways = 37;
170 panic("%s: unsupported Cavium Networks CPU.", __func__);
173 /* All Octeon models use 128 byte line size. */
174 cpuinfo->l1.dc_linesize = 128;
177 cpuinfo->l1.ic_size = cpuinfo->l1.ic_linesize
178 * cpuinfo->l1.ic_nsets * cpuinfo->l1.ic_nways;
179 cpuinfo->l1.dc_size = cpuinfo->l1.dc_linesize
180 * cpuinfo->l1.dc_nsets * cpuinfo->l1.dc_nways;
187 mips_get_identity(&cpuinfo);
188 num_tlbentries = cpuinfo.tlb_nentries;
190 tlb_invalidate_all();
191 mips_wr_wired(VMWIRED_ENTRIES);
192 mips_config_cache(&cpuinfo);
195 mips_icache_sync_all();
196 mips_dcache_wbinv_all();
197 /* Print some info about CPU */
204 uint32_t cfg0, cfg1, cfg2, cfg3;
205 printf("cpu%d: ", 0); /* XXX per-cpu */
206 switch (cpuinfo.cpu_vendor) {
207 case MIPS_PRID_CID_MTI:
208 printf("MIPS Technologies");
210 case MIPS_PRID_CID_BROADCOM:
211 case MIPS_PRID_CID_SIBYTE:
214 case MIPS_PRID_CID_ALCHEMY:
217 case MIPS_PRID_CID_SANDCRAFT:
220 case MIPS_PRID_CID_PHILIPS:
223 case MIPS_PRID_CID_TOSHIBA:
226 case MIPS_PRID_CID_LSI:
229 case MIPS_PRID_CID_LEXRA:
232 case MIPS_PRID_CID_RMI:
235 case MIPS_PRID_CID_CAVIUM:
238 case MIPS_PRID_CID_PREHISTORIC:
240 printf("Unknown cid %#x", cpuinfo.cpu_vendor);
243 printf(" processor v%d.%d\n", cpuinfo.cpu_rev, cpuinfo.cpu_impl);
246 if (cpuinfo.tlb_type == MIPS_MMU_NONE) {
247 printf("none present\n");
249 if (cpuinfo.tlb_type == MIPS_MMU_TLB) {
250 printf("Standard TLB");
251 } else if (cpuinfo.tlb_type == MIPS_MMU_BAT) {
252 printf("Standard BAT");
253 } else if (cpuinfo.tlb_type == MIPS_MMU_FIXED) {
254 printf("Fixed mapping");
256 printf(", %d entries\n", cpuinfo.tlb_nentries);
259 printf(" L1 i-cache: ");
260 if (cpuinfo.l1.ic_linesize == 0) {
263 if (cpuinfo.l1.ic_nways == 1) {
264 printf("direct-mapped with");
266 printf ("%d ways of", cpuinfo.l1.ic_nways);
268 printf(" %d sets, %d bytes per line\n",
269 cpuinfo.l1.ic_nsets, cpuinfo.l1.ic_linesize);
272 printf(" L1 d-cache: ");
273 if (cpuinfo.l1.dc_linesize == 0) {
276 if (cpuinfo.l1.dc_nways == 1) {
277 printf("direct-mapped with");
279 printf ("%d ways of", cpuinfo.l1.dc_nways);
281 printf(" %d sets, %d bytes per line\n",
282 cpuinfo.l1.dc_nsets, cpuinfo.l1.dc_linesize);
285 cfg0 = mips_rd_config();
286 /* If config register selection 1 does not exist, exit. */
287 if (!(cfg0 & MIPS_CONFIG_CM))
290 cfg1 = mips_rd_config1();
291 printf(" Config1=0x%b\n", cfg1,
292 "\20\7COP2\6MDMX\5PerfCount\4WatchRegs\3MIPS16\2EJTAG\1FPU");
294 /* If config register selection 2 does not exist, exit. */
295 if (!(cfg1 & MIPS_CONFIG_CM))
297 cfg2 = mips_rd_config2();
299 * Config2 contains no useful information other then Config3
303 /* If config register selection 3 does not exist, exit. */
304 if (!(cfg2 & MIPS_CONFIG_CM))
306 cfg3 = mips_rd_config3();
308 /* Print Config3 if it contains any useful info */
309 if (cfg3 & ~(0x80000000))
310 printf(" Config3=0x%b\n", cfg3, "\20\2SmartMIPS\1TraceLogic");
313 static struct rman cpu_hardirq_rman;
315 static devclass_t cpu_devclass;
320 static int cpu_probe(device_t);
321 static int cpu_attach(device_t);
322 static struct resource *cpu_alloc_resource(device_t, device_t, int, int *,
323 u_long, u_long, u_long, u_int);
324 static int cpu_setup_intr(device_t, device_t, struct resource *, int,
325 driver_filter_t *f, driver_intr_t *, void *,
328 static device_method_t cpu_methods[] = {
329 /* Device interface */
330 DEVMETHOD(device_probe, cpu_probe),
331 DEVMETHOD(device_attach, cpu_attach),
332 DEVMETHOD(device_detach, bus_generic_detach),
333 DEVMETHOD(device_shutdown, bus_generic_shutdown),
336 DEVMETHOD(bus_alloc_resource, cpu_alloc_resource),
337 DEVMETHOD(bus_setup_intr, cpu_setup_intr),
338 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
343 static driver_t cpu_driver = {
344 "cpu", cpu_methods, 1
348 cpu_probe(device_t dev)
354 cpu_attach(device_t dev)
361 cpu_hardirq_rman.rm_start = 0;
362 cpu_hardirq_rman.rm_end = 5;
363 cpu_hardirq_rman.rm_type = RMAN_ARRAY;
364 cpu_hardirq_rman.rm_descr = "CPU Hard Interrupts";
366 error = rman_init(&cpu_hardirq_rman);
368 device_printf(dev, "failed to initialize irq resources\n");
371 /* XXX rman_manage_all. */
372 error = rman_manage_region(&cpu_hardirq_rman,
373 cpu_hardirq_rman.rm_start,
374 cpu_hardirq_rman.rm_end);
376 device_printf(dev, "failed to manage irq resources\n");
380 if (device_get_unit(dev) != 0)
381 panic("can't attach more cpus");
382 device_set_desc(dev, "MIPS32 processor");
385 clock = device_add_child(dev, "clock", device_get_unit(dev));
387 device_printf(dev, "clock failed to attach");
390 return (bus_generic_attach(dev));
393 static struct resource *
394 cpu_alloc_resource(device_t dev, device_t child, int type, int *rid,
395 u_long start, u_long end, u_long count, u_int flags)
397 struct resource *res;
399 if (type != SYS_RES_IRQ)
401 res = rman_reserve_resource(&cpu_hardirq_rman, start, end, count, 0,
407 cpu_setup_intr(device_t dev, device_t child, struct resource *res, int flags,
408 driver_filter_t *filt, driver_intr_t *handler, void *arg,
414 error = rman_activate_resource(res);
416 device_printf(child, "could not activate irq\n");
420 intr = rman_get_start(res);
422 cpu_establish_hardintr(device_get_nameunit(child), filt, handler, arg,
423 intr, flags, cookiep);
424 device_printf(child, "established CPU interrupt %d\n", intr);
428 DRIVER_MODULE(cpu, root, cpu_driver, cpu_devclass, 0, 0);