2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright (c) 2006 Oleksandr Tymoshenko
5 * Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification, immediately at the beginning of the file.
14 * 2. The name of the author may not be used to endorse or promote products
15 * derived from this software without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
21 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include "opt_hwpmc_hooks.h"
36 #include <sys/param.h>
37 #include <sys/systm.h>
39 #include <sys/interrupt.h>
41 #include <sys/pmckern.h>
43 #include <machine/clock.h>
44 #include <machine/cpu.h>
45 #include <machine/cpufunc.h>
46 #include <machine/cpuinfo.h>
47 #include <machine/cpuregs.h>
48 #include <machine/frame.h>
49 #include <machine/intr_machdep.h>
50 #include <machine/md_var.h>
51 #include <machine/trap.h>
54 #define INTRCNT_COUNT 256
55 #define INTRNAME_LEN (2*MAXCOMLEN + 1)
57 MALLOC_DECLARE(M_MIPSINTR);
58 MALLOC_DEFINE(M_MIPSINTR, "mipsintr", "MIPS interrupt handling");
66 static struct intr_event *hardintr_events[NHARD_IRQS];
67 static struct intr_event *softintr_events[NSOFT_IRQS];
68 static mips_intrcnt_t mips_intr_counters[NSOFT_IRQS + NHARD_IRQS];
70 static int intrcnt_index;
72 static cpu_intr_mask_t hardintr_mask_func;
73 static cpu_intr_unmask_t hardintr_unmask_func;
76 mips_intrcnt_create(const char* name)
78 mips_intrcnt_t counter = &intrcnt[intrcnt_index++];
80 mips_intrcnt_setname(counter, name);
85 mips_intrcnt_setname(mips_intrcnt_t counter, const char *name)
87 int idx = counter - intrcnt;
89 KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter"));
91 snprintf(intrnames + (MAXCOMLEN + 1) * idx,
92 MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name);
96 mips_mask_hard_irq(void *source)
98 uintptr_t irq = (uintptr_t)source;
100 mips_wr_status(mips_rd_status() & ~(((1 << irq) << 8) << 2));
104 mips_unmask_hard_irq(void *source)
106 uintptr_t irq = (uintptr_t)source;
108 mips_wr_status(mips_rd_status() | (((1 << irq) << 8) << 2));
112 mips_mask_soft_irq(void *source)
114 uintptr_t irq = (uintptr_t)source;
116 mips_wr_status(mips_rd_status() & ~((1 << irq) << 8));
120 mips_unmask_soft_irq(void *source)
122 uintptr_t irq = (uintptr_t)source;
124 mips_wr_status(mips_rd_status() | ((1 << irq) << 8));
128 * Perform initialization of interrupts prior to setting
132 cpu_init_interrupts()
135 char name[MAXCOMLEN + 1];
138 intrcnt = mallocarray(INTRCNT_COUNT, sizeof(u_long), M_MIPSINTR,
140 intrnames = mallocarray(INTRCNT_COUNT, INTRNAME_LEN, M_MIPSINTR,
142 sintrcnt = INTRCNT_COUNT * sizeof(u_long);
143 sintrnames = INTRCNT_COUNT * INTRNAME_LEN;
147 * Initialize all available vectors so spare IRQ
148 * would show up in systat output
150 for (i = 0; i < NSOFT_IRQS; i++) {
151 snprintf(name, MAXCOMLEN + 1, "sint%d:", i);
152 mips_intr_counters[i] = mips_intrcnt_create(name);
155 for (i = 0; i < NHARD_IRQS; i++) {
156 snprintf(name, MAXCOMLEN + 1, "int%d:", i);
157 mips_intr_counters[NSOFT_IRQS + i] = mips_intrcnt_create(name);
162 cpu_set_hardintr_mask_func(cpu_intr_mask_t func)
165 hardintr_mask_func = func;
169 cpu_set_hardintr_unmask_func(cpu_intr_unmask_t func)
172 hardintr_unmask_func = func;
176 cpu_establish_hardintr(const char *name, driver_filter_t *filt,
177 void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
179 struct intr_event *event;
183 * We have 6 levels, but thats 0 - 5 (not including 6)
185 if (irq < 0 || irq >= NHARD_IRQS)
186 panic("%s called for unknown hard intr %d", __func__, irq);
188 if (hardintr_mask_func == NULL)
189 hardintr_mask_func = mips_mask_hard_irq;
191 if (hardintr_unmask_func == NULL)
192 hardintr_unmask_func = mips_unmask_hard_irq;
194 event = hardintr_events[irq];
196 error = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
197 irq, hardintr_mask_func, hardintr_unmask_func,
198 NULL, NULL, "int%d", irq);
201 hardintr_events[irq] = event;
202 mips_unmask_hard_irq((void*)(uintptr_t)irq);
205 intr_event_add_handler(event, name, filt, handler, arg,
206 intr_priority(flags), flags, cookiep);
208 mips_intrcnt_setname(mips_intr_counters[NSOFT_IRQS + irq],
213 cpu_establish_softintr(const char *name, driver_filter_t *filt,
214 void (*handler)(void*), void *arg, int irq, int flags,
217 struct intr_event *event;
221 printf("Establish SOFT IRQ %d: filt %p handler %p arg %p\n",
222 irq, filt, handler, arg);
224 if (irq < 0 || irq > NSOFT_IRQS)
225 panic("%s called for unknown hard intr %d", __func__, irq);
227 event = softintr_events[irq];
229 error = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
230 irq, mips_mask_soft_irq, mips_unmask_soft_irq,
231 NULL, NULL, "sint%d:", irq);
234 softintr_events[irq] = event;
235 mips_unmask_soft_irq((void*)(uintptr_t)irq);
238 intr_event_add_handler(event, name, filt, handler, arg,
239 intr_priority(flags), flags, cookiep);
241 mips_intrcnt_setname(mips_intr_counters[irq], event->ie_fullname);
245 cpu_intr(struct trapframe *tf)
247 struct intr_event *event;
248 register_t cause, status;
253 cause = mips_rd_cause();
254 status = mips_rd_status();
255 intr = (cause & MIPS_INT_MASK) >> 8;
257 * Do not handle masked interrupts. They were masked by
258 * pre_ithread function (mips_mask_XXX_intr) and will be
259 * unmasked once ithread is through with handler
261 intr &= (status & MIPS_INT_MASK) >> 8;
262 while ((i = fls(intr)) != 0) {
263 intr &= ~(1 << (i - 1));
266 /* Software interrupt. */
267 i--; /* Get a 0-offset interrupt. */
269 event = softintr_events[i];
270 mips_intrcnt_inc(mips_intr_counters[i]);
273 /* Hardware interrupt. */
274 i -= 2; /* Trim software interrupt bits. */
275 i--; /* Get a 0-offset interrupt. */
277 event = hardintr_events[i];
278 mips_intrcnt_inc(mips_intr_counters[NSOFT_IRQS + i]);
282 if (!event || CK_SLIST_EMPTY(&event->ie_handlers)) {
283 printf("stray %s interrupt %d\n",
284 hard ? "hard" : "soft", i);
288 if (intr_event_handle(event, tf) != 0) {
289 printf("stray %s interrupt %d\n",
290 hard ? "hard" : "soft", i);
294 KASSERT(i == 0, ("all interrupts handled"));
299 if (pmc_hook && (PCPU_GET(curthread)->td_pflags & TDP_CALLCHAIN))
300 pmc_hook(PCPU_GET(curthread), PMC_FN_USER_CALLCHAIN, tf);