1 /* $OpenBSD: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1988 University of Utah.
7 * Copyright (c) 1992, 1993
8 * The Regents of the University of California. All rights reserved.
10 * This code is derived from software contributed to Berkeley by
11 * the Systems Programming Group of the University of Utah Computer
12 * Science Department, The Mach Operating System project at
13 * Carnegie-Mellon University and Ralph Campbell.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)machdep.c 8.3 (Berkeley) 1/12/94
40 * Id: machdep.c,v 1.33 1998/09/15 10:58:54 pefo Exp
41 * JNPR: machdep.c,v 1.11.2.3 2007/08/29 12:24:49
44 #include <sys/cdefs.h>
45 __FBSDID("$FreeBSD$");
50 #include <sys/param.h>
52 #include <sys/systm.h>
57 #include <sys/kernel.h>
58 #include <sys/linker.h>
59 #include <sys/malloc.h>
61 #include <sys/msgbuf.h>
62 #include <sys/reboot.h>
63 #include <sys/rwlock.h>
64 #include <sys/sched.h>
65 #include <sys/sysctl.h>
66 #include <sys/sysproto.h>
67 #include <sys/vmmeter.h>
70 #include <vm/vm_kern.h>
71 #include <vm/vm_object.h>
72 #include <vm/vm_page.h>
74 #include <vm/vm_map.h>
75 #include <vm/vm_pager.h>
76 #include <vm/vm_extern.h>
77 #include <sys/socket.h>
80 #include <sys/interrupt.h>
82 #include <sys/syslog.h>
83 #include <machine/asm.h>
84 #include <machine/bootinfo.h>
85 #include <machine/cache.h>
86 #include <machine/clock.h>
87 #include <machine/cpu.h>
88 #include <machine/cpuregs.h>
89 #include <machine/elf.h>
90 #include <machine/hwfunc.h>
91 #include <machine/intr_machdep.h>
92 #include <machine/md_var.h>
93 #include <machine/tlb.h>
99 #include <sys/random.h>
102 #define BOOTINFO_DEBUG 0
104 char machine[] = "mips";
105 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, machine, 0, "Machine class");
108 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, cpu_model, 0, "Machine model");
111 SYSCTL_STRING(_hw, OID_AUTO, board, CTLFLAG_RD, cpu_board, 0, "Machine board");
116 int cpu_clock = MIPS_DEFAULT_HZ;
117 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
118 &cpu_clock, 0, "CPU instruction clock rate");
119 int clocks_running = 0;
124 * Each entry in the pcpu_space[] array is laid out in the following manner:
125 * struct pcpu for cpu 'n' pcpu_space[n]
126 * boot stack for cpu 'n' pcpu_space[n] + PAGE_SIZE * 2 - CALLFRAME_SIZ
128 * Note that the boot stack grows downwards and we assume that we never
129 * use enough stack space to trample over the 'struct pcpu' that is at
130 * the beginning of the array.
132 * The array is aligned on a (PAGE_SIZE * 2) boundary so that the 'struct pcpu'
133 * is always in the even page frame of the wired TLB entry on SMP kernels.
135 * The array is in the .data section so that the stack does not get zeroed out
136 * when the .bss section is zeroed.
138 char pcpu_space[MAXCPU][PAGE_SIZE * 2] \
139 __aligned(PAGE_SIZE * 2) __section(".data");
141 struct pcpu *pcpup = (struct pcpu *)pcpu_space;
143 vm_paddr_t phys_avail[PHYS_AVAIL_ENTRIES + 2];
144 vm_paddr_t physmem_desc[PHYS_AVAIL_ENTRIES + 2];
145 vm_paddr_t dump_avail[PHYS_AVAIL_ENTRIES + 2];
148 struct platform platform;
151 static void cpu_startup(void *);
152 SYSINIT(cpu, SI_SUB_CPU, SI_ORDER_FIRST, cpu_startup, NULL);
154 struct kva_md_info kmi;
156 int cpucfg; /* Value of processor config register */
157 int num_tlbentries = 64; /* Size of the CPU tlb */
160 extern char MipsException[], MipsExceptionEnd[];
162 /* TLB miss handler address and end */
163 extern char MipsTLBMiss[], MipsTLBMissEnd[];
165 /* Cache error handler */
166 extern char MipsCache[], MipsCacheEnd[];
168 /* MIPS wait skip region */
169 extern char MipsWaitStart[], MipsWaitEnd[];
171 extern char edata[], end[];
174 struct bootinfo bootinfo;
176 * First kseg0 address available for use. By default it's equal to &end.
177 * But in some cases there might be additional data placed right after
178 * _end by loader or ELF trampoline.
180 vm_offset_t kernel_kseg0_end = (vm_offset_t)&end;
183 cpu_startup(void *dummy)
186 if (boothowto & RB_VERBOSE)
189 printf("real memory = %ju (%juK bytes)\n", ptoa((uintmax_t)realmem),
190 ptoa((uintmax_t)realmem) / 1024);
193 * Display any holes after the first chunk of extended memory.
198 printf("Physical memory chunk(s):\n");
199 for (indx = 0; phys_avail[indx + 1] != 0; indx += 2) {
200 vm_paddr_t size1 = phys_avail[indx + 1] - phys_avail[indx];
202 printf("0x%08jx - 0x%08jx, %ju bytes (%ju pages)\n",
203 (uintmax_t)phys_avail[indx],
204 (uintmax_t)phys_avail[indx + 1] - 1,
206 (uintmax_t)size1 / PAGE_SIZE);
210 vm_ksubmap_init(&kmi);
212 printf("avail memory = %ju (%juMB)\n",
213 ptoa((uintmax_t)vm_cnt.v_free_count),
214 ptoa((uintmax_t)vm_cnt.v_free_count) / 1048576);
215 cpu_init_interrupts();
218 * Set up buffers, so they can be used to read disk labels.
221 vm_pager_bufferinit();
225 * Shutdown the CPU as much as possible
235 * Flush the D-cache for non-DMA I/O so that the I-cache can
236 * be made coherent later.
239 cpu_flush_dcache(void *ptr, size_t len)
244 /* Get current clock frequency for the given cpu id. */
246 cpu_est_clockrate(int cpu_id, uint64_t *rate)
253 * Shutdown the CPU as much as possible
262 SYSCTL_STRUCT(_machdep, OID_AUTO, bootinfo, CTLFLAG_RD, &bootinfo,
263 bootinfo, "Bootinfo struct: kernel filename, BIOS harddisk geometry, etc");
266 * Initialize per cpu data structures, include curthread.
271 /* Initialize pcpu info of cpu-zero */
272 pcpu_init(PCPU_ADDR(0), 0, sizeof(struct pcpu));
273 PCPU_SET(curthread, &thread0);
277 * Initialize mips and configure to run kernel
280 mips_proc0_init(void)
283 if (platform_processor_id() != 0)
284 panic("BSP must be processor number 0");
286 proc_linkup0(&proc0, &thread0);
288 KASSERT((kstack0 & PAGE_MASK) == 0,
289 ("kstack0 is not aligned on a page boundary: 0x%0lx",
291 thread0.td_kstack = kstack0;
292 thread0.td_kstack_pages = KSTACK_PAGES;
294 * Do not use cpu_thread_alloc to initialize these fields
295 * thread0 is the only thread that has kstack located in KSEG0
296 * while cpu_thread_alloc handles kstack allocated in KSEG2.
298 thread0.td_pcb = (struct pcb *)(thread0.td_kstack +
299 thread0.td_kstack_pages * PAGE_SIZE) - 1;
300 thread0.td_frame = &thread0.td_pcb->pcb_regs;
302 /* Steal memory for the dynamic per-cpu area. */
303 dpcpu_init((void *)pmap_steal_memory(DPCPU_SIZE), 0);
305 PCPU_SET(curpcb, thread0.td_pcb);
307 * There is no need to initialize md_upte array for thread0 as it's
308 * located in .bss section and should be explicitly zeroed during
309 * kernel initialization.
317 platform_initclocks();
318 cpu_initclocks_bsp();
321 struct msgbuf *msgbufp = NULL;
324 * Initialize the hardware exception vectors, and the jump table used to
325 * call locore cache and TLB management functions, based on the kind
326 * of CPU the kernel is running on.
329 mips_vector_init(void)
332 * Make sure that the Wait region logic is not been
335 if (MipsWaitEnd - MipsWaitStart != 16)
336 panic("startup: MIPS wait region not correct");
338 * Copy down exception vector code.
340 if (MipsTLBMissEnd - MipsTLBMiss > 0x80)
341 panic("startup: UTLB code too large");
343 if (MipsCacheEnd - MipsCache > 0x80)
344 panic("startup: Cache error code too large");
346 bcopy(MipsTLBMiss, (void *)MIPS_UTLB_MISS_EXC_VEC,
347 MipsTLBMissEnd - MipsTLBMiss);
350 * XXXRW: Why don't we install the XTLB handler for all 64-bit
353 #if defined(__mips_n64) || defined(CPU_RMI) || defined(CPU_NLM) || defined(CPU_BERI)
354 /* Fake, but sufficient, for the 32-bit with 64-bit hardware addresses */
355 bcopy(MipsTLBMiss, (void *)MIPS_XTLB_MISS_EXC_VEC,
356 MipsTLBMissEnd - MipsTLBMiss);
359 bcopy(MipsException, (void *)MIPS_GEN_EXC_VEC,
360 MipsExceptionEnd - MipsException);
362 bcopy(MipsCache, (void *)MIPS_CACHE_ERR_EXC_VEC,
363 MipsCacheEnd - MipsCache);
366 * Clear out the I and D caches.
368 mips_icache_sync_all();
369 mips_dcache_wbinv_all();
372 * Mask all interrupts. Each interrupt will be enabled
373 * when handler is installed for it
377 /* Clear BEV in SR so we start handling our own exceptions */
378 mips_wr_status(mips_rd_status() & ~MIPS_SR_BEV);
382 * Fix kernel_kseg0_end address in case trampoline placed debug sympols
386 mips_postboot_fixup(void)
388 static char fake_preload[256];
389 caddr_t preload_ptr = (caddr_t)&fake_preload[0];
392 #define PRELOAD_PUSH_VALUE(type, value) do { \
393 *(type *)(preload_ptr + size) = (value); \
394 size += sizeof(type); \
398 * Provide kernel module file information
400 PRELOAD_PUSH_VALUE(uint32_t, MODINFO_NAME);
401 PRELOAD_PUSH_VALUE(uint32_t, strlen("kernel") + 1);
402 strcpy((char*)(preload_ptr + size), "kernel");
403 size += strlen("kernel") + 1;
404 size = roundup(size, sizeof(u_long));
406 PRELOAD_PUSH_VALUE(uint32_t, MODINFO_TYPE);
407 PRELOAD_PUSH_VALUE(uint32_t, strlen("elf kernel") + 1);
408 strcpy((char*)(preload_ptr + size), "elf kernel");
409 size += strlen("elf kernel") + 1;
410 size = roundup(size, sizeof(u_long));
412 PRELOAD_PUSH_VALUE(uint32_t, MODINFO_ADDR);
413 PRELOAD_PUSH_VALUE(uint32_t, sizeof(vm_offset_t));
414 PRELOAD_PUSH_VALUE(vm_offset_t, KERNLOADADDR);
415 size = roundup(size, sizeof(u_long));
417 PRELOAD_PUSH_VALUE(uint32_t, MODINFO_SIZE);
418 PRELOAD_PUSH_VALUE(uint32_t, sizeof(size_t));
419 PRELOAD_PUSH_VALUE(size_t, (size_t)&end - KERNLOADADDR);
420 size = roundup(size, sizeof(u_long));
423 PRELOAD_PUSH_VALUE(uint32_t, 0);
424 PRELOAD_PUSH_VALUE(uint32_t, 0);
426 #undef PRELOAD_PUSH_VALUE
428 KASSERT((size < sizeof(fake_preload)),
429 ("fake preload size is more thenallocated"));
431 preload_metadata = (void *)fake_preload;
434 Elf_Size *trampoline_data = (Elf_Size*)kernel_kseg0_end;
435 Elf_Size symtabsize = 0;
436 vm_offset_t ksym_start;
437 vm_offset_t ksym_end;
439 if (trampoline_data[0] == SYMTAB_MAGIC) {
440 symtabsize = trampoline_data[1];
441 kernel_kseg0_end += 2 * sizeof(Elf_Size);
442 /* start of .symtab */
443 ksym_start = kernel_kseg0_end;
444 kernel_kseg0_end += symtabsize;
446 ksym_end = kernel_kseg0_end;
447 db_fetch_ksymtab(ksym_start, ksym_end);
454 mips_pcpu_tlb_init(struct pcpu *pcpu)
460 * Map the pcpu structure at the virtual address 'pcpup'.
461 * We use a wired tlb index to do this one-time mapping.
464 pte = PTE_D | PTE_V | PTE_G | PTE_C_CACHE;
465 tlb_insert_wired(PCPU_TLB_ENTRY, (vm_offset_t)pcpup,
466 TLBLO_PA_TO_PFN(pa) | pte,
467 TLBLO_PA_TO_PFN(pa + PAGE_SIZE) | pte);
472 * Initialise a struct pcpu.
475 cpu_pcpu_init(struct pcpu *pcpu, int cpuid, size_t size)
478 pcpu->pc_next_asid = 1;
479 pcpu->pc_asid_generation = 1;
480 pcpu->pc_self = pcpu;
482 if ((vm_offset_t)pcpup >= VM_MIN_KERNEL_ADDRESS &&
483 (vm_offset_t)pcpup <= VM_MAX_KERNEL_ADDRESS) {
484 mips_pcpu_tlb_init(pcpu);
490 fill_dbregs(struct thread *td, struct dbreg *dbregs)
493 /* No debug registers on mips */
498 set_dbregs(struct thread *td, struct dbreg *dbregs)
501 /* No debug registers on mips */
512 if (td->td_md.md_spinlock_count == 0) {
513 intr = intr_disable();
514 td->td_md.md_spinlock_count = 1;
515 td->td_md.md_saved_intr = intr;
517 td->td_md.md_spinlock_count++;
529 intr = td->td_md.md_saved_intr;
530 td->td_md.md_spinlock_count--;
531 if (td->td_md.md_spinlock_count == 0)
536 * call platform specific code to halt (until next interrupt) for the idle loop
541 KASSERT((mips_rd_status() & MIPS_SR_INT_IE) != 0,
542 ("interrupts disabled in idle process."));
543 KASSERT((mips_rd_status() & MIPS_INT_MASK) != 0,
544 ("all interrupts masked in idle process."));
558 cpu_idle_wakeup(int cpu)
565 is_cacheable_mem(vm_paddr_t pa)
569 for (i = 0; physmem_desc[i + 1] != 0; i += 2) {
570 if (pa >= physmem_desc[i] && pa < physmem_desc[i + 1])