sys/mips/mips/mips_pic.c

   1 /*-
   2  * Copyright (c) 2015 Alexander Kabaev
   3  * Copyright (c) 2006 Oleksandr Tymoshenko
   4  * Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification, immediately at the beginning of the file.
  13  * 2. The name of the author may not be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include "opt_platform.h"
  34 #include "opt_hwpmc_hooks.h"
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/bus.h>
  39 #include <sys/kernel.h>
  40 #include <sys/ktr.h>
  41 #include <sys/module.h>
  42 #include <sys/malloc.h>
  43 #include <sys/rman.h>
  44 #include <sys/pcpu.h>
  45 #include <sys/proc.h>
  46 #include <sys/cpuset.h>
  47 #include <sys/lock.h>
  48 #include <sys/mutex.h>
  49 #include <sys/smp.h>
  50 #include <sys/sched.h>
  51 #include <sys/pmc.h>
  52 #include <sys/pmckern.h>
  53
  54 #include <machine/bus.h>
  55 #include <machine/hwfunc.h>
  56 #include <machine/intr.h>
  57 #include <machine/smp.h>
  58
  59 #ifdef FDT
  60 #include <dev/fdt/fdt_common.h>
  61 #include <dev/ofw/openfirm.h>
  62 #include <dev/ofw/ofw_bus.h>
  63 #include <dev/ofw/ofw_bus_subr.h>
  64 #endif
  65
  66 #include "pic_if.h"
  67
  68 #define NHARD_IRQS      6
  69 #define NSOFT_IRQS      2
  70 #define NREAL_IRQS      (NHARD_IRQS + NSOFT_IRQS)
  71
  72 static int mips_pic_intr(void *);
  73
  74 struct mips_pic_irqsrc {
  75         struct intr_irqsrc      isrc;
  76         struct resource         *res;
  77         u_int                   irq;
  78 };
  79
  80 struct mips_pic_softc {
  81         device_t                        pic_dev;
  82         struct mips_pic_irqsrc          pic_irqs[NREAL_IRQS];
  83         struct rman                     pic_irq_rman;
  84         struct mtx                      mutex;
  85         uint32_t                        nirqs;
  86 };
  87
  88 static struct mips_pic_softc *pic_sc;
  89
  90 #define PIC_INTR_ISRC(sc, irq)          (&(sc)->pic_irqs[(irq)].isrc)
  91
  92 #ifdef FDT
  93 static struct ofw_compat_data compat_data[] = {
  94         {"mti,cpu-interrupt-controller",        true},
  95         {NULL,                                  false}
  96 };
  97 #endif
  98
  99 #ifndef FDT
 100 static void
 101 mips_pic_identify(driver_t *drv, device_t parent)
 102 {
 103
 104         BUS_ADD_CHILD(parent, 0, "cpupic", 0);
 105 }
 106 #endif
 107
 108 static int
 109 mips_pic_probe(device_t dev)
 110 {
 111
 112 #ifdef FDT
 113         if (!ofw_bus_status_okay(dev))
 114                 return (ENXIO);
 115
 116         if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
 117                 return (ENXIO);
 118 #endif
 119         device_set_desc(dev, "MIPS32 Interrupt Controller");
 120         return (BUS_PROBE_DEFAULT);
 121 }
 122
 123 static inline void
 124 pic_irq_unmask(struct mips_pic_softc *sc, u_int irq)
 125 {
 126
 127         mips_wr_status(mips_rd_status() | ((1 << irq) << 8));
 128 }
 129
 130 static inline void
 131 pic_irq_mask(struct mips_pic_softc *sc, u_int irq)
 132 {
 133
 134         mips_wr_status(mips_rd_status() & ~((1 << irq) << 8));
 135 }
 136
 137 static inline intptr_t
 138 pic_xref(device_t dev)
 139 {
 140 #ifdef FDT
 141         return (OF_xref_from_node(ofw_bus_get_node(dev)));
 142 #else
 143         return (0);
 144 #endif
 145 }
 146
 147 static int
 148 mips_pic_register_isrcs(struct mips_pic_softc *sc)
 149 {
 150         int error;
 151         uint32_t irq, i, tmpirq;
 152         struct intr_irqsrc *isrc;
 153         char *name;
 154
 155         for (irq = 0; irq < sc->nirqs; irq++) {
 156                 sc->pic_irqs[irq].irq = irq;
 157                 sc->pic_irqs[irq].res = rman_reserve_resource(&sc->pic_irq_rman,
 158                     irq, irq, 1, RF_ACTIVE, sc->pic_dev);
 159                 if (sc->pic_irqs[irq].res == NULL) {
 160                         device_printf(sc->pic_dev,
 161                             "%s failed to alloc resource for irq %u",
 162                             __func__, irq);
 163                         return (ENOMEM);
 164                 }
 165                 isrc = PIC_INTR_ISRC(sc, irq);
 166                 if (irq < NSOFT_IRQS) {
 167                         name = "sint";
 168                         tmpirq = irq;
 169                 } else {
 170                         name = "int";
 171                         tmpirq = irq - NSOFT_IRQS;
 172                 }
 173                 error = intr_isrc_register(isrc, sc->pic_dev, 0, "%s%u",
 174                     name, tmpirq);
 175                 if (error != 0) {
 176                         for (i = 0; i < irq; i++) {
 177                                 intr_isrc_deregister(PIC_INTR_ISRC(sc, i));
 178                         }
 179                         device_printf(sc->pic_dev, "%s failed", __func__);
 180                         return (error);
 181                 }
 182         }
 183
 184         return (0);
 185 }
 186
 187 static int
 188 mips_pic_attach(device_t dev)
 189 {
 190         struct          mips_pic_softc *sc;
 191         intptr_t        xref = pic_xref(dev);
 192
 193         if (pic_sc)
 194                 return (ENXIO);
 195
 196         sc = device_get_softc(dev);
 197
 198         sc->pic_dev = dev;
 199         pic_sc = sc;
 200
 201         /* Initialize mutex */
 202         mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
 203
 204         /* Set the number of interrupts */
 205         sc->nirqs = nitems(sc->pic_irqs);
 206
 207         /* Init the IRQ rman */
 208         sc->pic_irq_rman.rm_type = RMAN_ARRAY;
 209         sc->pic_irq_rman.rm_descr = "MIPS PIC IRQs";
 210         if (rman_init(&sc->pic_irq_rman) != 0 ||
 211             rman_manage_region(&sc->pic_irq_rman, 0, sc->nirqs - 1) != 0) {
 212                 device_printf(dev, "failed to setup IRQ rman\n");
 213                 goto cleanup;
 214         }
 215
 216         /* Register the interrupts */
 217         if (mips_pic_register_isrcs(sc) != 0) {
 218                 device_printf(dev, "could not register PIC ISRCs\n");
 219                 goto cleanup;
 220         }
 221
 222         /*
 223          * Now, when everything is initialized, it's right time to
 224          * register interrupt controller to interrupt framefork.
 225          */
 226         if (intr_pic_register(dev, xref) != 0) {
 227                 device_printf(dev, "could not register PIC\n");
 228                 goto cleanup;
 229         }
 230
 231         /* Claim our root controller role */
 232         if (intr_pic_claim_root(dev, xref, mips_pic_intr, sc, 0) != 0) {
 233                 device_printf(dev, "could not set PIC as a root\n");
 234                 intr_pic_deregister(dev, xref);
 235                 goto cleanup;
 236         }
 237
 238         return (0);
 239
 240 cleanup:
 241         return(ENXIO);
 242 }
 243
 244 int
 245 mips_pic_intr(void *arg)
 246 {
 247         struct mips_pic_softc *sc = arg;
 248         register_t cause, status;
 249         int i, intr;
 250
 251         cause = mips_rd_cause();
 252         status = mips_rd_status();
 253         intr = (cause & MIPS_INT_MASK) >> 8;
 254         /*
 255          * Do not handle masked interrupts. They were masked by
 256          * pre_ithread function (mips_mask_XXX_intr) and will be
 257          * unmasked once ithread is through with handler
 258          */
 259         intr &= (status & MIPS_INT_MASK) >> 8;
 260         while ((i = fls(intr)) != 0) {
 261                 i--; /* Get a 0-offset interrupt. */
 262                 intr &= ~(1 << i);
 263
 264                 if (intr_isrc_dispatch(PIC_INTR_ISRC(sc, i),
 265                     curthread->td_intr_frame) != 0) {
 266                         device_printf(sc->pic_dev,
 267                             "Stray interrupt %u detected\n", i);
 268                         pic_irq_mask(sc, i);
 269                         continue;
 270                 }
 271         }
 272
 273         KASSERT(i == 0, ("all interrupts handled"));
 274
 275 #ifdef HWPMC_HOOKS
 276         if (pmc_hook && (PCPU_GET(curthread)->td_pflags & TDP_CALLCHAIN)) {
 277                 struct trapframe *tf = PCPU_GET(curthread)->td_intr_frame;
 278
 279                 pmc_hook(PCPU_GET(curthread), PMC_FN_USER_CALLCHAIN, tf);
 280         }
 281 #endif
 282         return (FILTER_HANDLED);
 283 }
 284
 285 static void
 286 mips_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc)
 287 {
 288         u_int irq;
 289
 290         irq = ((struct mips_pic_irqsrc *)isrc)->irq;
 291         pic_irq_mask(device_get_softc(dev), irq);
 292 }
 293
 294 static void
 295 mips_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 296 {
 297         u_int irq;
 298
 299         irq = ((struct mips_pic_irqsrc *)isrc)->irq;
 300         pic_irq_unmask(device_get_softc(dev), irq);
 301 }
 302
 303 static int
 304 mips_pic_map_intr(device_t dev, struct intr_map_data *data,
 305     struct intr_irqsrc **isrcp)
 306 {
 307 #ifdef FDT
 308         struct mips_pic_softc *sc;
 309
 310         sc = device_get_softc(dev);
 311
 312         if (data == NULL || data->type != INTR_MAP_DATA_FDT ||
 313             data->fdt.ncells != 1 || data->fdt.cells[0] >= sc->nirqs)
 314                 return (EINVAL);
 315
 316         *isrcp = PIC_INTR_ISRC(sc, data->fdt.cells[0]);
 317         return (0);
 318 #else
 319         return (EINVAL);
 320 #endif
 321 }
 322
 323 static void
 324 mips_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 325 {
 326
 327         mips_pic_disable_intr(dev, isrc);
 328 }
 329
 330 static void
 331 mips_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 332 {
 333
 334         mips_pic_enable_intr(dev, isrc);
 335 }
 336
 337 static void
 338 mips_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
 339 {
 340 }
 341
 342 static device_method_t mips_pic_methods[] = {
 343         /* Device interface */
 344 #ifndef FDT
 345         DEVMETHOD(device_identify,      mips_pic_identify),
 346 #endif
 347         DEVMETHOD(device_probe,         mips_pic_probe),
 348         DEVMETHOD(device_attach,        mips_pic_attach),
 349
 350         /* Interrupt controller interface */
 351         DEVMETHOD(pic_disable_intr,     mips_pic_disable_intr),
 352         DEVMETHOD(pic_enable_intr,      mips_pic_enable_intr),
 353         DEVMETHOD(pic_map_intr,         mips_pic_map_intr),
 354         DEVMETHOD(pic_pre_ithread,      mips_pic_pre_ithread),
 355         DEVMETHOD(pic_post_ithread,     mips_pic_post_ithread),
 356         DEVMETHOD(pic_post_filter,      mips_pic_post_filter),
 357
 358         { 0, 0 }
 359 };
 360
 361 static driver_t mips_pic_driver = {
 362         "cpupic",
 363         mips_pic_methods,
 364         sizeof(struct mips_pic_softc),
 365 };
 366
 367 static devclass_t mips_pic_devclass;
 368
 369 #ifdef FDT
 370 EARLY_DRIVER_MODULE(cpupic, ofwbus, mips_pic_driver, mips_pic_devclass, 0, 0,
 371     BUS_PASS_INTERRUPT);
 372 #else
 373 EARLY_DRIVER_MODULE(cpupic, nexus, mips_pic_driver, mips_pic_devclass, 0, 0,
 374     BUS_PASS_INTERRUPT);
 375 #endif
 376
 377 void
 378 cpu_init_interrupts(void)
 379 {
 380 }
 381
 382 void
 383 cpu_establish_hardintr(const char *name, driver_filter_t *filt,
 384     void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
 385 {
 386         int res;
 387
 388         /*
 389          * We have 6 levels, but thats 0 - 5 (not including 6)
 390          */
 391         if (irq < 0 || irq >= NHARD_IRQS)
 392                 panic("%s called for unknown hard intr %d", __func__, irq);
 393
 394         KASSERT(pic_sc != NULL, ("%s: no pic", __func__));
 395
 396         irq += NSOFT_IRQS;
 397         res = intr_setup_irq(pic_sc->pic_dev, pic_sc->pic_irqs[irq].res, filt,
 398             handler, arg, flags, cookiep);
 399         if (res != 0) panic("Unable to add hard IRQ %d handler", irq);
 400 }
 401
 402 void
 403 cpu_establish_softintr(const char *name, driver_filter_t *filt,
 404     void (*handler)(void*), void *arg, int irq, int flags,
 405     void **cookiep)
 406 {
 407         int res;
 408
 409         if (irq < 0 || irq > NSOFT_IRQS)
 410                 panic("%s called for unknown soft intr %d", __func__, irq);
 411
 412         KASSERT(pic_sc != NULL, ("%s: no pic", __func__));
 413
 414         res = intr_setup_irq(pic_sc->pic_dev, pic_sc->pic_irqs[irq].res, filt,
 415             handler, arg, flags, cookiep);
 416         if (res != 0) panic("Unable to add soft IRQ %d handler", irq);
 417 }
 418