sys/mips/mips/mips_pic.c

   1 /*-
   2  * Copyright (c) 2015 Alexander Kabaev
   3  * Copyright (c) 2006 Oleksandr Tymoshenko
   4  * Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions, and the following disclaimer,
  12  *    without modification, immediately at the beginning of the file.
  13  * 2. The name of the author may not be used to endorse or promote products
  14  *    derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
  20  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  *
  28  */
  29
  30 #include <sys/cdefs.h>
  31 __FBSDID("$FreeBSD$");
  32
  33 #include "opt_platform.h"
  34 #include "opt_hwpmc_hooks.h"
  35
  36 #include <sys/param.h>
  37 #include <sys/systm.h>
  38 #include <sys/bus.h>
  39 #include <sys/kernel.h>
  40 #include <sys/ktr.h>
  41 #include <sys/module.h>
  42 #include <sys/malloc.h>
  43 #include <sys/rman.h>
  44 #include <sys/pcpu.h>
  45 #include <sys/proc.h>
  46 #include <sys/cpuset.h>
  47 #include <sys/lock.h>
  48 #include <sys/mutex.h>
  49 #include <sys/smp.h>
  50 #include <sys/sched.h>
  51 #include <sys/pmc.h>
  52 #include <sys/pmckern.h>
  53
  54 #include <machine/bus.h>
  55 #include <machine/hwfunc.h>
  56 #include <machine/intr.h>
  57 #include <machine/smp.h>
  58
  59 #ifdef FDT
  60 #include <dev/fdt/fdt_common.h>
  61 #include <dev/ofw/openfirm.h>
  62 #include <dev/ofw/ofw_bus.h>
  63 #include <dev/ofw/ofw_bus_subr.h>
  64 #endif
  65
  66 #include "pic_if.h"
  67
  68 #define NHARD_IRQS      6
  69 #define NSOFT_IRQS      2
  70 #define NREAL_IRQS      (NHARD_IRQS + NSOFT_IRQS)
  71
  72 static int mips_pic_intr(void *);
  73
  74 struct mips_pic_softc {
  75         device_t                pic_dev;
  76         struct intr_irqsrc *    pic_irqs[NREAL_IRQS];
  77         struct mtx              mutex;
  78         uint32_t                nirqs;
  79 };
  80
  81 static struct mips_pic_softc *pic_sc;
  82
  83 #ifdef FDT
  84 static struct ofw_compat_data compat_data[] = {
  85         {"mti,cpu-interrupt-controller",        true},
  86         {NULL,                                  false}
  87 };
  88 #endif
  89
  90 #ifndef FDT
  91 static void
  92 mips_pic_identify(driver_t *drv, device_t parent)
  93 {
  94
  95         BUS_ADD_CHILD(parent, 0, "cpupic", 0);
  96 }
  97 #endif
  98
  99 static int
 100 mips_pic_probe(device_t dev)
 101 {
 102
 103 #ifdef FDT
 104         if (!ofw_bus_status_okay(dev))
 105                 return (ENXIO);
 106
 107         if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
 108                 return (ENXIO);
 109 #endif
 110         device_set_desc(dev, "MIPS32 Interrupt Controller");
 111         return (BUS_PROBE_DEFAULT);
 112 }
 113
 114 static inline void
 115 pic_irq_unmask(struct mips_pic_softc *sc, u_int irq)
 116 {
 117
 118         mips_wr_status(mips_rd_status() | ((1 << irq) << 8));
 119 }
 120
 121 static inline void
 122 pic_irq_mask(struct mips_pic_softc *sc, u_int irq)
 123 {
 124
 125         mips_wr_status(mips_rd_status() & ~((1 << irq) << 8));
 126 }
 127
 128 #ifdef SMP
 129 static void
 130 mips_pic_init_secondary(device_t dev)
 131 {
 132 }
 133 #endif /* SMP */
 134
 135 static inline intptr_t
 136 pic_xref(device_t dev)
 137 {
 138 #ifdef FDT
 139         return (OF_xref_from_node(ofw_bus_get_node(dev)));
 140 #else
 141         return (0);
 142 #endif
 143 }
 144
 145 static int
 146 mips_pic_attach(device_t dev)
 147 {
 148         struct          mips_pic_softc *sc;
 149         intptr_t        xref = pic_xref(dev);
 150
 151         if (pic_sc)
 152                 return (ENXIO);
 153
 154         sc = device_get_softc(dev);
 155
 156         sc->pic_dev = dev;
 157         pic_sc = sc;
 158
 159         /* Initialize mutex */
 160         mtx_init(&sc->mutex, "PIC lock", "", MTX_SPIN);
 161
 162         /* Set the number of interrupts */
 163         sc->nirqs = nitems(sc->pic_irqs);
 164
 165         /*
 166          * Now, when everything is initialized, it's right time to
 167          * register interrupt controller to interrupt framefork.
 168          */
 169         if (intr_pic_register(dev, xref) != 0) {
 170                 device_printf(dev, "could not register PIC\n");
 171                 goto cleanup;
 172         }
 173
 174         /* Claim our root controller role */
 175         if (intr_pic_claim_root(dev, xref, mips_pic_intr, sc, 0) != 0) {
 176                 device_printf(dev, "could not set PIC as a root\n");
 177                 intr_pic_unregister(dev, xref);
 178                 goto cleanup;
 179         }
 180
 181         return (0);
 182
 183 cleanup:
 184         return(ENXIO);
 185 }
 186
 187 int
 188 mips_pic_intr(void *arg)
 189 {
 190         struct mips_pic_softc *sc = arg;
 191         register_t cause, status;
 192         struct intr_irqsrc *isrc;
 193         int i, intr;
 194
 195         cause = mips_rd_cause();
 196         status = mips_rd_status();
 197         intr = (cause & MIPS_INT_MASK) >> 8;
 198         /*
 199          * Do not handle masked interrupts. They were masked by
 200          * pre_ithread function (mips_mask_XXX_intr) and will be
 201          * unmasked once ithread is through with handler
 202          */
 203         intr &= (status & MIPS_INT_MASK) >> 8;
 204         while ((i = fls(intr)) != 0) {
 205                 i--; /* Get a 0-offset interrupt. */
 206                 intr &= ~(1 << i);
 207
 208                 isrc = sc->pic_irqs[i];
 209                 if (isrc == NULL) {
 210                         device_printf(sc->pic_dev,
 211                             "Stray interrupt %u detected\n", i);
 212                         pic_irq_mask(sc, i);
 213                         continue;
 214                 }
 215
 216                 intr_irq_dispatch(isrc, curthread->td_intr_frame);
 217         }
 218
 219         KASSERT(i == 0, ("all interrupts handled"));
 220
 221 #ifdef HWPMC_HOOKS
 222         if (pmc_hook && (PCPU_GET(curthread)->td_pflags & TDP_CALLCHAIN)) {
 223                 struct trapframe *tf = PCPU_GET(curthread)->td_intr_frame;
 224
 225                 pmc_hook(PCPU_GET(curthread), PMC_FN_USER_CALLCHAIN, tf);
 226         }
 227 #endif
 228         return (FILTER_HANDLED);
 229 }
 230
 231 static int
 232 pic_attach_isrc(struct mips_pic_softc *sc, struct intr_irqsrc *isrc, u_int irq)
 233 {
 234
 235         /*
 236          * 1. The link between ISRC and controller must be set atomically.
 237          * 2. Just do things only once in rare case when consumers
 238          *    of shared interrupt came here at the same moment.
 239          */
 240         mtx_lock_spin(&sc->mutex);
 241         if (sc->pic_irqs[irq] != NULL) {
 242                 mtx_unlock_spin(&sc->mutex);
 243                 return (sc->pic_irqs[irq] == isrc ? 0 : EEXIST);
 244         }
 245         sc->pic_irqs[irq] = isrc;
 246         isrc->isrc_data = irq;
 247         mtx_unlock_spin(&sc->mutex);
 248
 249         if (irq < NSOFT_IRQS)
 250                 intr_irq_set_name(isrc, "sint%u", irq);
 251         else if (irq < NREAL_IRQS)
 252                 intr_irq_set_name(isrc, "int%u", irq - NSOFT_IRQS);
 253         else
 254                 panic("Invalid irq %u", irq);
 255         return (0);
 256 }
 257
 258 static int
 259 pic_detach_isrc(struct mips_pic_softc *sc, struct intr_irqsrc *isrc, u_int irq)
 260 {
 261
 262         mtx_lock_spin(&sc->mutex);
 263         if (sc->pic_irqs[irq] != isrc) {
 264                 mtx_unlock_spin(&sc->mutex);
 265                 return (sc->pic_irqs[irq] == NULL ? 0 : EINVAL);
 266         }
 267         sc->pic_irqs[irq] = NULL;
 268         isrc->isrc_data = 0;
 269         mtx_unlock_spin(&sc->mutex);
 270
 271         intr_irq_set_name(isrc, "%s", "");
 272         return (0);
 273 }
 274
 275 static int
 276 pic_irq_from_nspc(struct mips_pic_softc *sc, u_int type, u_int num, u_int *irqp)
 277 {
 278
 279         switch (type) {
 280         case INTR_IRQ_NSPC_PLAIN:
 281                 *irqp = num;
 282                 return (*irqp < sc->nirqs ? 0 : EINVAL);
 283
 284         case INTR_IRQ_NSPC_SWI:
 285                 *irqp = num;
 286                 return (num < NSOFT_IRQS ? 0 : EINVAL);
 287
 288         case INTR_IRQ_NSPC_IRQ:
 289                 *irqp = num + NSOFT_IRQS;
 290                 return (num < NHARD_IRQS ? 0 : EINVAL);
 291
 292         default:
 293                 return (EINVAL);
 294         }
 295 }
 296
 297 static int
 298 pic_map_nspc(struct mips_pic_softc *sc, struct intr_irqsrc *isrc, u_int *irqp)
 299 {
 300         int error;
 301
 302         error = pic_irq_from_nspc(sc, isrc->isrc_nspc_type, isrc->isrc_nspc_num,
 303             irqp);
 304         if (error != 0)
 305                 return (error);
 306         return (pic_attach_isrc(sc, isrc, *irqp));
 307 }
 308
 309 #ifdef FDT
 310 static int
 311 pic_map_fdt(struct mips_pic_softc *sc, struct intr_irqsrc *isrc, u_int *irqp)
 312 {
 313         u_int irq;
 314         int error;
 315
 316         irq = isrc->isrc_cells[0];
 317
 318         if (irq >= sc->nirqs)
 319                 return (EINVAL);
 320
 321         error = pic_attach_isrc(sc, isrc, irq);
 322         if (error != 0)
 323                 return (error);
 324
 325         isrc->isrc_nspc_type = INTR_IRQ_NSPC_PLAIN;
 326         isrc->isrc_nspc_num = irq;
 327         isrc->isrc_trig = INTR_TRIGGER_CONFORM;
 328         isrc->isrc_pol = INTR_POLARITY_CONFORM;
 329
 330         *irqp = irq;
 331         return (0);
 332 }
 333 #endif
 334
 335 static int
 336 mips_pic_register(device_t dev, struct intr_irqsrc *isrc, boolean_t *is_percpu)
 337 {
 338         struct mips_pic_softc *sc = device_get_softc(dev);
 339         u_int irq;
 340         int error;
 341
 342         if (isrc->isrc_type == INTR_ISRCT_NAMESPACE)
 343                 error = pic_map_nspc(sc, isrc, &irq);
 344 #ifdef FDT
 345         else if (isrc->isrc_type == INTR_ISRCT_FDT)
 346                 error = pic_map_fdt(sc, isrc, &irq);
 347 #endif
 348         else
 349                 return (EINVAL);
 350
 351         if (error == 0)
 352                 *is_percpu = TRUE;
 353         return (error);
 354 }
 355
 356 static void
 357 mips_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc)
 358 {
 359
 360         if (isrc->isrc_trig == INTR_TRIGGER_CONFORM)
 361                 isrc->isrc_trig = INTR_TRIGGER_LEVEL;
 362 }
 363
 364 static void
 365 mips_pic_enable_source(device_t dev, struct intr_irqsrc *isrc)
 366 {
 367         struct mips_pic_softc *sc = device_get_softc(dev);
 368         u_int irq = isrc->isrc_data;
 369
 370         pic_irq_unmask(sc, irq);
 371 }
 372
 373 static void
 374 mips_pic_disable_source(device_t dev, struct intr_irqsrc *isrc)
 375 {
 376         struct mips_pic_softc *sc = device_get_softc(dev);
 377         u_int irq = isrc->isrc_data;
 378
 379         pic_irq_mask(sc, irq);
 380 }
 381
 382 static int
 383 mips_pic_unregister(device_t dev, struct intr_irqsrc *isrc)
 384 {
 385         struct mips_pic_softc *sc = device_get_softc(dev);
 386         u_int irq = isrc->isrc_data;
 387
 388         return (pic_detach_isrc(sc, isrc, irq));
 389 }
 390
 391 static void
 392 mips_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc)
 393 {
 394
 395         mips_pic_disable_source(dev, isrc);
 396 }
 397
 398 static void
 399 mips_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc)
 400 {
 401
 402         mips_pic_enable_source(dev, isrc);
 403 }
 404
 405 static void
 406 mips_pic_post_filter(device_t dev, struct intr_irqsrc *isrc)
 407 {
 408 }
 409
 410 #ifdef SMP
 411 static int
 412 mips_pic_bind(device_t dev, struct intr_irqsrc *isrc)
 413 {
 414         return (EOPNOTSUPP);
 415 }
 416
 417 static void
 418 mips_pic_ipi_send(device_t dev, struct intr_irqsrc *isrc, cpuset_t cpus)
 419 {
 420 }
 421 #endif
 422
 423 static device_method_t mips_pic_methods[] = {
 424         /* Device interface */
 425 #ifndef FDT
 426         DEVMETHOD(device_identify,      mips_pic_identify),
 427 #endif
 428         DEVMETHOD(device_probe,         mips_pic_probe),
 429         DEVMETHOD(device_attach,        mips_pic_attach),
 430         /* Interrupt controller interface */
 431         DEVMETHOD(pic_disable_source,   mips_pic_disable_source),
 432         DEVMETHOD(pic_enable_intr,      mips_pic_enable_intr),
 433         DEVMETHOD(pic_enable_source,    mips_pic_enable_source),
 434         DEVMETHOD(pic_post_filter,      mips_pic_post_filter),
 435         DEVMETHOD(pic_post_ithread,     mips_pic_post_ithread),
 436         DEVMETHOD(pic_pre_ithread,      mips_pic_pre_ithread),
 437         DEVMETHOD(pic_register,         mips_pic_register),
 438         DEVMETHOD(pic_unregister,       mips_pic_unregister),
 439 #ifdef SMP
 440         DEVMETHOD(pic_bind,             mips_pic_bind),
 441         DEVMETHOD(pic_init_secondary,   mips_pic_init_secondary),
 442         DEVMETHOD(pic_ipi_send,         mips_pic_ipi_send),
 443 #endif
 444         { 0, 0 }
 445 };
 446
 447 static driver_t mips_pic_driver = {
 448         "cpupic",
 449         mips_pic_methods,
 450         sizeof(struct mips_pic_softc),
 451 };
 452
 453 static devclass_t mips_pic_devclass;
 454
 455 #ifdef FDT
 456 EARLY_DRIVER_MODULE(cpupic, ofwbus, mips_pic_driver, mips_pic_devclass, 0, 0,
 457     BUS_PASS_INTERRUPT);
 458 #else
 459 EARLY_DRIVER_MODULE(cpupic, nexus, mips_pic_driver, mips_pic_devclass, 0, 0,
 460     BUS_PASS_INTERRUPT);
 461 #endif
 462
 463 void
 464 cpu_init_interrupts(void)
 465 {
 466 }
 467
 468 void
 469 cpu_establish_hardintr(const char *name, driver_filter_t *filt,
 470     void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
 471 {
 472         u_int vec;
 473         int res;
 474
 475         /*
 476          * We have 6 levels, but thats 0 - 5 (not including 6)
 477          */
 478         if (irq < 0 || irq >= NHARD_IRQS)
 479                 panic("%s called for unknown hard intr %d", __func__, irq);
 480
 481         KASSERT(pic_sc != NULL, ("%s: no pic", __func__));
 482         vec = intr_namespace_map_irq(pic_sc->pic_dev, INTR_IRQ_NSPC_IRQ, irq);
 483         KASSERT(vec != NIRQ, ("Unable to map hard IRQ %d\n", irq));
 484
 485         res = intr_irq_add_handler(pic_sc->pic_dev, filt, handler, arg, vec,
 486             flags, cookiep);
 487         if (res != 0) panic("Unable to add hard IRQ %d handler", irq);
 488
 489         (void)pic_irq_from_nspc(pic_sc, INTR_IRQ_NSPC_IRQ, irq, &vec);
 490         KASSERT(pic_sc->pic_irqs[vec] != NULL,
 491             ("Hard IRQ %d not registered\n", irq));
 492         intr_irq_set_name(pic_sc->pic_irqs[vec], "%s", name);
 493 }
 494
 495 void
 496 cpu_establish_softintr(const char *name, driver_filter_t *filt,
 497     void (*handler)(void*), void *arg, int irq, int flags,
 498     void **cookiep)
 499 {
 500         u_int vec;
 501         int res;
 502
 503         if (irq < 0 || irq > NSOFT_IRQS)
 504                 panic("%s called for unknown soft intr %d", __func__, irq);
 505
 506         KASSERT(pic_sc != NULL, ("%s: no pic", __func__));
 507         vec = intr_namespace_map_irq(pic_sc->pic_dev, INTR_IRQ_NSPC_SWI, irq);
 508         KASSERT(vec <= NIRQ, ("Unable to map soft IRQ %d\n", irq));
 509
 510         intr_irq_add_handler(pic_sc->pic_dev, filt, handler, arg, vec,
 511             flags, cookiep);
 512         if (res != 0) panic("Unable to add soft IRQ %d handler", irq);
 513
 514         (void)pic_irq_from_nspc(pic_sc, INTR_IRQ_NSPC_SWI, irq, &vec);
 515         KASSERT(pic_sc->pic_irqs[vec] != NULL,
 516             ("Soft IRQ %d not registered\n", irq));
 517         intr_irq_set_name(pic_sc->pic_irqs[vec], "%s", name);
 518 }
 519