2 * Copyright (c) 1992 Terrence R. Lambert.
3 * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
6 * This code is derived from software contributed to Berkeley by
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * from: @(#)machdep.c 7.4 (Berkeley) 6/3/91
34 * from: src/sys/i386/i386/machdep.c,v 1.385.2.3 2000/05/10 02:04:46 obrien
35 * JNPR: pm_machdep.c,v 1.9.2.1 2007/08/16 15:59:10 girish
38 #include <sys/cdefs.h>
39 __FBSDID("$FreeBSD$");
41 #include "opt_compat.h"
43 #include <sys/types.h>
44 #include <sys/param.h>
45 #include <sys/systm.h>
46 #include <sys/sysent.h>
48 #include <sys/signalvar.h>
50 #include <sys/imgact.h>
51 #include <sys/ucontext.h>
53 #include <sys/syscallsubr.h>
54 #include <sys/sysproto.h>
55 #include <sys/ptrace.h>
56 #include <sys/syslog.h>
59 #include <vm/vm_map.h>
60 #include <vm/vm_extern.h>
63 #include <machine/cpuinfo.h>
64 #include <machine/reg.h>
65 #include <machine/md_var.h>
66 #include <machine/sigframe.h>
67 #include <machine/tls.h>
68 #include <machine/vmparam.h>
69 #include <sys/vnode.h>
70 #include <fs/pseudofs/pseudofs.h>
71 #include <fs/procfs/procfs.h>
73 #define UCONTEXT_MAGIC 0xACEDBADE
76 * Send an interrupt to process.
78 * Stack is set up to allow sigcode stored
79 * at top to call routine, followed by kcall
80 * to sigreturn routine below. After sigreturn
81 * resets the signal mask, the stack, and the
82 * frame pointer, it returns to the user
86 sendsig(sig_t catcher, ksiginfo_t *ksi, sigset_t *mask)
90 struct trapframe *regs;
92 struct sigframe sf, *sfp;
98 PROC_LOCK_ASSERT(p, MA_OWNED);
101 mtx_assert(&psp->ps_mtx, MA_OWNED);
104 oonstack = sigonstack(regs->sp);
106 /* save user context */
107 bzero(&sf, sizeof(struct sigframe));
108 sf.sf_uc.uc_sigmask = *mask;
109 sf.sf_uc.uc_stack = td->td_sigstk;
110 sf.sf_uc.uc_mcontext.mc_onstack = (oonstack) ? 1 : 0;
111 sf.sf_uc.uc_mcontext.mc_pc = regs->pc;
112 sf.sf_uc.uc_mcontext.mullo = regs->mullo;
113 sf.sf_uc.uc_mcontext.mulhi = regs->mulhi;
114 sf.sf_uc.uc_mcontext.mc_tls = td->td_md.md_tls;
115 sf.sf_uc.uc_mcontext.mc_regs[0] = UCONTEXT_MAGIC; /* magic number */
116 bcopy((void *)®s->ast, (void *)&sf.sf_uc.uc_mcontext.mc_regs[1],
117 sizeof(sf.sf_uc.uc_mcontext.mc_regs) - sizeof(register_t));
118 sf.sf_uc.uc_mcontext.mc_fpused = td->td_md.md_flags & MDTD_FPUSED;
119 if (sf.sf_uc.uc_mcontext.mc_fpused) {
120 /* if FPU has current state, save it first */
121 if (td == PCPU_GET(fpcurthread))
122 MipsSaveCurFPState(td);
123 bcopy((void *)&td->td_frame->f0,
124 (void *)sf.sf_uc.uc_mcontext.mc_fpregs,
125 sizeof(sf.sf_uc.uc_mcontext.mc_fpregs));
128 /* Allocate and validate space for the signal handler context. */
129 if ((td->td_pflags & TDP_ALTSTACK) != 0 && !oonstack &&
130 SIGISMEMBER(psp->ps_sigonstack, sig)) {
131 sfp = (struct sigframe *)(((uintptr_t)td->td_sigstk.ss_sp +
132 td->td_sigstk.ss_size - sizeof(struct sigframe))
133 & ~(sizeof(__int64_t) - 1));
135 sfp = (struct sigframe *)((vm_offset_t)(regs->sp -
136 sizeof(struct sigframe)) & ~(sizeof(__int64_t) - 1));
138 /* Build the argument list for the signal handler. */
140 regs->a2 = (register_t)(intptr_t)&sfp->sf_uc;
141 if (SIGISMEMBER(psp->ps_siginfo, sig)) {
142 /* Signal handler installed with SA_SIGINFO. */
143 regs->a1 = (register_t)(intptr_t)&sfp->sf_si;
144 /* sf.sf_ahu.sf_action = (__siginfohandler_t *)catcher; */
146 /* fill siginfo structure */
147 sf.sf_si = ksi->ksi_info;
148 sf.sf_si.si_signo = sig;
149 sf.sf_si.si_code = ksi->ksi_code;
150 sf.sf_si.si_addr = (void*)(intptr_t)regs->badvaddr;
152 /* Old FreeBSD-style arguments. */
153 regs->a1 = ksi->ksi_code;
154 regs->a3 = regs->badvaddr;
155 /* sf.sf_ahu.sf_handler = catcher; */
158 mtx_unlock(&psp->ps_mtx);
162 * Copy the sigframe out to the user's stack.
164 if (copyout(&sf, sfp, sizeof(struct sigframe)) != 0) {
166 * Something is wrong with the stack pointer.
167 * ...Kill the process.
173 regs->pc = (register_t)(intptr_t)catcher;
174 regs->t9 = (register_t)(intptr_t)catcher;
175 regs->sp = (register_t)(intptr_t)sfp;
177 * Signal trampoline code is at base of user stack.
179 regs->ra = (register_t)(intptr_t)PS_STRINGS - *(p->p_sysent->sv_szsigcode);
181 mtx_lock(&psp->ps_mtx);
185 * System call to cleanup state after a signal
186 * has been taken. Reset signal mask and
187 * stack state from context left by sendsig (above).
188 * Return to previous pc as specified by
189 * context left by sendsig.
192 sys_sigreturn(struct thread *td, struct sigreturn_args *uap)
197 error = copyin(uap->sigcntxp, &uc, sizeof(uc));
201 error = set_mcontext(td, &uc.uc_mcontext);
205 kern_sigprocmask(td, SIG_SETMASK, &uc.uc_sigmask, NULL, 0);
207 return (EJUSTRETURN);
211 ptrace_set_pc(struct thread *td, unsigned long addr)
213 td->td_frame->pc = (register_t) addr;
218 ptrace_read_int(struct thread *td, off_t addr, int *v)
221 if (proc_readmem(td, td->td_proc, addr, v, sizeof(*v)) != sizeof(*v))
227 ptrace_write_int(struct thread *td, off_t addr, int v)
230 if (proc_writemem(td, td->td_proc, addr, &v, sizeof(v)) != sizeof(v))
236 ptrace_single_step(struct thread *td)
239 struct trapframe *locr0 = td->td_frame;
241 int bpinstr = MIPS_BREAK_SSTEP;
248 * Fetch what's at the current location.
250 ptrace_read_int(td, (off_t)locr0->pc, &curinstr);
252 /* compute next address after current location */
254 va = MipsEmulateBranch(locr0, locr0->pc, locr0->fsr,
255 (uintptr_t)&curinstr);
259 if (td->td_md.md_ss_addr) {
260 printf("SS %s (%d): breakpoint already set at %x (va %x)\n",
261 p->p_comm, p->p_pid, td->td_md.md_ss_addr, va); /* XXX */
264 td->td_md.md_ss_addr = va;
266 * Fetch what's at the current location.
268 ptrace_read_int(td, (off_t)va, &td->td_md.md_ss_instr);
271 * Store breakpoint instruction at the "next" location now.
273 i = ptrace_write_int (td, va, bpinstr);
276 * The sync'ing of I & D caches is done by procfs_domem()
277 * through procfs_rwmem().
284 printf("SS %s (%d): breakpoint set at %x: %x (pc %x) br %x\n",
285 p->p_comm, p->p_pid, p->p_md.md_ss_addr,
286 p->p_md.md_ss_instr, locr0->pc, curinstr); /* XXX */
293 makectx(struct trapframe *tf, struct pcb *pcb)
296 pcb->pcb_context[PCB_REG_RA] = tf->ra;
297 pcb->pcb_context[PCB_REG_PC] = tf->pc;
298 pcb->pcb_context[PCB_REG_SP] = tf->sp;
302 fill_regs(struct thread *td, struct reg *regs)
304 memcpy(regs, td->td_frame, sizeof(struct reg));
309 set_regs(struct thread *td, struct reg *regs)
314 f = (struct trapframe *) td->td_frame;
316 * Don't allow the user to change SR
319 memcpy(td->td_frame, regs, sizeof(struct reg));
325 get_mcontext(struct thread *td, mcontext_t *mcp, int flags)
327 struct trapframe *tp;
330 PROC_LOCK(curthread->td_proc);
331 mcp->mc_onstack = sigonstack(tp->sp);
332 PROC_UNLOCK(curthread->td_proc);
333 bcopy((void *)&td->td_frame->zero, (void *)&mcp->mc_regs,
334 sizeof(mcp->mc_regs));
336 mcp->mc_fpused = td->td_md.md_flags & MDTD_FPUSED;
337 if (mcp->mc_fpused) {
338 bcopy((void *)&td->td_frame->f0, (void *)&mcp->mc_fpregs,
339 sizeof(mcp->mc_fpregs));
341 if (flags & GET_MC_CLEAR_RET) {
342 mcp->mc_regs[V0] = 0;
343 mcp->mc_regs[V1] = 0;
344 mcp->mc_regs[A3] = 0;
347 mcp->mc_pc = td->td_frame->pc;
348 mcp->mullo = td->td_frame->mullo;
349 mcp->mulhi = td->td_frame->mulhi;
350 mcp->mc_tls = td->td_md.md_tls;
355 set_mcontext(struct thread *td, mcontext_t *mcp)
357 struct trapframe *tp;
360 bcopy((void *)&mcp->mc_regs, (void *)&td->td_frame->zero,
361 sizeof(mcp->mc_regs));
363 td->td_md.md_flags = mcp->mc_fpused & MDTD_FPUSED;
364 if (mcp->mc_fpused) {
365 bcopy((void *)&mcp->mc_fpregs, (void *)&td->td_frame->f0,
366 sizeof(mcp->mc_fpregs));
368 td->td_frame->pc = mcp->mc_pc;
369 td->td_frame->mullo = mcp->mullo;
370 td->td_frame->mulhi = mcp->mulhi;
371 td->td_md.md_tls = mcp->mc_tls;
372 /* Dont let user to set any bits in status and cause registers. */
378 fill_fpregs(struct thread *td, struct fpreg *fpregs)
380 if (td == PCPU_GET(fpcurthread))
381 MipsSaveCurFPState(td);
382 memcpy(fpregs, &td->td_frame->f0, sizeof(struct fpreg));
383 fpregs->r_regs[FIR_NUM] = cpuinfo.fpu_id;
388 set_fpregs(struct thread *td, struct fpreg *fpregs)
390 if (PCPU_GET(fpcurthread) == td)
391 PCPU_SET(fpcurthread, (struct thread *)0);
392 memcpy(&td->td_frame->f0, fpregs, sizeof(struct fpreg));
398 * Clear registers on exec
399 * $sp is set to the stack pointer passed in. $pc is set to the entry
400 * point given by the exec_package passed in, as is $t9 (used for PIC
401 * code by the MIPS elf abi).
404 exec_setregs(struct thread *td, struct image_params *imgp, u_long stack)
407 bzero((caddr_t)td->td_frame, sizeof(struct trapframe));
410 * The stack pointer has to be aligned to accommodate the largest
411 * datatype at minimum. This probably means it should be 16-byte
412 * aligned, but for now we're 8-byte aligning it.
414 td->td_frame->sp = ((register_t) stack) & ~(sizeof(__int64_t) - 1);
417 * If we're running o32 or n32 programs but have 64-bit registers,
418 * GCC may use stack-relative addressing near the top of user
419 * address space that, due to sign extension, will yield an
420 * invalid address. For instance, if sp is 0x7fffff00 then GCC
421 * might do something like this to load a word from 0x7ffffff0:
426 * On systems with 64-bit registers, sp is sign-extended to
427 * 0xffffffff80007f00 and the load is instead done from
428 * 0xffffffff7ffffff0.
430 * To prevent this, we subtract 64K from the stack pointer here
431 * for processes with 32-bit pointers.
433 #if defined(__mips_n32) || defined(__mips_n64)
434 if (!SV_PROC_FLAG(td->td_proc, SV_LP64))
435 td->td_frame->sp -= 65536;
438 td->td_frame->pc = imgp->entry_addr & ~3;
439 td->td_frame->t9 = imgp->entry_addr & ~3; /* abicall req */
440 td->td_frame->sr = MIPS_SR_KSU_USER | MIPS_SR_EXL | MIPS_SR_INT_IE |
441 (mips_rd_status() & MIPS_SR_INT_MASK);
442 #if defined(__mips_n32)
443 td->td_frame->sr |= MIPS_SR_PX;
444 #elif defined(__mips_n64)
445 td->td_frame->sr |= MIPS_SR_PX | MIPS_SR_UX | MIPS_SR_KX;
448 * FREEBSD_DEVELOPERS_FIXME:
449 * Setup any other CPU-Specific registers (Not MIPS Standard)
450 * and/or bits in other standard MIPS registers (if CPU-Specific)
455 * Set up arguments for the rtld-capable crt0:
457 * a1 rtld cleanup (filled in by dynamic loader)
458 * a2 rtld object (filled in by dynamic loader)
461 td->td_frame->a0 = (register_t) stack;
462 td->td_frame->a1 = 0;
463 td->td_frame->a2 = 0;
464 td->td_frame->a3 = (register_t)imgp->ps_strings;
466 td->td_md.md_flags &= ~MDTD_FPUSED;
467 if (PCPU_GET(fpcurthread) == td)
468 PCPU_SET(fpcurthread, (struct thread *)0);
469 td->td_md.md_ss_addr = 0;
471 td->td_md.md_tls_tcb_offset = TLS_TP_OFFSET + TLS_TCB_SIZE;
475 ptrace_clear_single_step(struct thread *td)
481 PROC_LOCK_ASSERT(p, MA_OWNED);
482 if (!td->td_md.md_ss_addr)
486 * Restore original instruction and clear BP
488 i = ptrace_write_int (td, td->td_md.md_ss_addr, td->td_md.md_ss_instr);
490 /* The sync'ing of I & D caches is done by procfs_domem(). */
493 log(LOG_ERR, "SS %s %d: can't restore instruction at %x: %x\n",
494 p->p_comm, p->p_pid, td->td_md.md_ss_addr,
495 td->td_md.md_ss_instr);
497 td->td_md.md_ss_addr = 0;