2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps
41 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish
45 * Manages physical address maps.
47 * Since the information managed by this module is
48 * also stored by the logical address mapping module,
49 * this module may throw away valid virtual-to-physical
50 * mappings at almost any time. However, invalidations
51 * of virtual-to-physical mappings must be done as
54 * In order to cope with hardware architectures which
55 * make virtual-to-physical map invalidates expensive,
56 * this module may delay invalidate or reduced protection
57 * operations until such time as they are actually
58 * necessary. This module is given full information as
59 * to which processors are currently using which maps,
60 * and to when physical maps must be made correct.
63 #include <sys/cdefs.h>
64 __FBSDID("$FreeBSD$");
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/kernel.h>
74 #include <sys/msgbuf.h>
75 #include <sys/mutex.h>
78 #include <sys/rwlock.h>
79 #include <sys/sched.h>
81 #include <sys/sysctl.h>
82 #include <sys/vmmeter.h>
89 #include <vm/vm_param.h>
90 #include <vm/vm_kern.h>
91 #include <vm/vm_page.h>
92 #include <vm/vm_phys.h>
93 #include <vm/vm_map.h>
94 #include <vm/vm_object.h>
95 #include <vm/vm_extern.h>
96 #include <vm/vm_pageout.h>
97 #include <vm/vm_pager.h>
100 #include <machine/cache.h>
101 #include <machine/md_var.h>
102 #include <machine/tlb.h>
106 #if !defined(DIAGNOSTIC)
107 #define PMAP_INLINE __inline
113 #define PV_STAT(x) do { x ; } while (0)
115 #define PV_STAT(x) do { } while (0)
119 * Get PDEs and PTEs for user/kernel address space
121 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
122 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1))
123 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1))
124 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT)
127 #define NUPDE (NPDEPG * NPDEPG)
128 #define NUSERPGTBLS (NUPDE + NPDEPG)
130 #define NUPDE (NPDEPG)
131 #define NUSERPGTBLS (NUPDE)
134 #define is_kernel_pmap(x) ((x) == kernel_pmap)
136 struct pmap kernel_pmap_store;
137 pd_entry_t *kernel_segmap;
139 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
140 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
142 static int need_local_mappings;
145 unsigned pmap_max_asid; /* max ASID supported by the system */
147 #define PMAP_ASID_RESERVED 0
149 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
151 static void pmap_asid_alloc(pmap_t pmap);
153 static struct rwlock_padalign pvh_global_lock;
156 * Data for the pv entry allocation mechanism
158 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
159 static int pv_entry_count;
161 static void free_pv_chunk(struct pv_chunk *pc);
162 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
163 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
164 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
165 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
166 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
168 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req);
169 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
170 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
171 static void pmap_grow_direct_page(int req);
172 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
174 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
175 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
176 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
177 vm_offset_t va, vm_page_t m);
178 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
179 static void pmap_invalidate_all(pmap_t pmap);
180 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
181 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m);
183 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
184 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags);
185 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t);
186 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot);
188 static void pmap_invalidate_page_action(void *arg);
189 static void pmap_invalidate_range_action(void *arg);
190 static void pmap_update_page_action(void *arg);
194 static vm_offset_t crashdumpva;
197 * These functions are for high memory (memory above 512Meg in 32 bit) support.
198 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to
199 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc.
201 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To
202 * access a highmem physical address on a CPU, we map the physical address to
203 * the reserved virtual address for the CPU in the kernel pagetable.
207 pmap_init_reserved_pages(void)
213 if (need_local_mappings == 0)
219 * Skip if the mapping has already been initialized,
220 * i.e. this is the BSP.
222 if (pc->pc_cmap1_addr != 0)
224 pages = kva_alloc(PAGE_SIZE * 3);
226 panic("%s: unable to allocate KVA", __func__);
227 pc->pc_cmap1_ptep = pmap_pte(kernel_pmap, pages);
228 pc->pc_cmap2_ptep = pmap_pte(kernel_pmap, pages + PAGE_SIZE);
230 pmap_pte(kernel_pmap, pages + (PAGE_SIZE * 2));
231 pc->pc_cmap1_addr = pages;
232 pc->pc_cmap2_addr = pages + PAGE_SIZE;
233 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
236 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
239 pmap_alloc_lmem_map(void)
241 PCPU_SET(cmap1_addr, virtual_avail);
242 PCPU_SET(cmap2_addr, virtual_avail + PAGE_SIZE);
243 PCPU_SET(cmap1_ptep, pmap_pte(kernel_pmap, virtual_avail));
244 PCPU_SET(cmap2_ptep, pmap_pte(kernel_pmap, virtual_avail + PAGE_SIZE));
245 PCPU_SET(qmap_addr, virtual_avail + (2 * PAGE_SIZE));
246 PCPU_SET(qmap_ptep, pmap_pte(kernel_pmap, virtual_avail + (2 * PAGE_SIZE)));
247 crashdumpva = virtual_avail + (3 * PAGE_SIZE);
248 virtual_avail += PAGE_SIZE * 4;
251 static __inline vm_offset_t
252 pmap_lmem_map1(vm_paddr_t phys)
255 *PCPU_GET(cmap1_ptep) =
256 TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
257 return (PCPU_GET(cmap1_addr));
260 static __inline vm_offset_t
261 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
264 *PCPU_GET(cmap1_ptep) =
265 TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
266 *PCPU_GET(cmap2_ptep) =
267 TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
268 return (PCPU_GET(cmap1_addr));
272 pmap_lmem_unmap(void)
274 *PCPU_GET(cmap1_ptep) = PTE_G;
275 tlb_invalidate_address(kernel_pmap, PCPU_GET(cmap1_addr));
276 if (*PCPU_GET(cmap2_ptep) != PTE_G) {
277 *PCPU_GET(cmap2_ptep) = PTE_G;
278 tlb_invalidate_address(kernel_pmap, PCPU_GET(cmap2_addr));
283 #else /* __mips_n64 */
286 pmap_alloc_lmem_map(void)
290 static __inline vm_offset_t
291 pmap_lmem_map1(vm_paddr_t phys)
297 static __inline vm_offset_t
298 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
304 static __inline vm_offset_t
305 pmap_lmem_unmap(void)
310 #endif /* !__mips_n64 */
313 pmap_pte_cache_bits(vm_paddr_t pa, vm_page_t m)
317 ma = pmap_page_get_memattr(m);
318 if (ma == VM_MEMATTR_WRITE_BACK && !is_cacheable_mem(pa))
319 ma = VM_MEMATTR_UNCACHEABLE;
322 #define PMAP_PTE_SET_CACHE_BITS(pte, pa, m) { \
323 pte &= ~PTE_C_MASK; \
324 pte |= pmap_pte_cache_bits(pa, m); \
328 * Page table entry lookup routines.
330 static __inline pd_entry_t *
331 pmap_segmap(pmap_t pmap, vm_offset_t va)
334 return (&pmap->pm_segtab[pmap_seg_index(va)]);
338 static __inline pd_entry_t *
339 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
343 pde = (pd_entry_t *)*pdpe;
344 return (&pde[pmap_pde_index(va)]);
347 static __inline pd_entry_t *
348 pmap_pde(pmap_t pmap, vm_offset_t va)
352 pdpe = pmap_segmap(pmap, va);
356 return (pmap_pdpe_to_pde(pdpe, va));
359 static __inline pd_entry_t *
360 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
367 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va)
370 return (pmap_segmap(pmap, va));
374 static __inline pt_entry_t *
375 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
379 pte = (pt_entry_t *)*pde;
380 return (&pte[pmap_pte_index(va)]);
384 pmap_pte(pmap_t pmap, vm_offset_t va)
388 pde = pmap_pde(pmap, va);
389 if (pde == NULL || *pde == NULL)
392 return (pmap_pde_to_pte(pde, va));
396 pmap_steal_memory(vm_size_t size)
398 vm_paddr_t bank_size, pa;
401 size = round_page(size);
402 bank_size = phys_avail[1] - phys_avail[0];
403 while (size > bank_size) {
406 for (i = 0; phys_avail[i + 2]; i += 2) {
407 phys_avail[i] = phys_avail[i + 2];
408 phys_avail[i + 1] = phys_avail[i + 3];
411 phys_avail[i + 1] = 0;
413 panic("pmap_steal_memory: out of memory");
414 bank_size = phys_avail[1] - phys_avail[0];
418 phys_avail[0] += size;
419 if (MIPS_DIRECT_MAPPABLE(pa) == 0)
420 panic("Out of memory below 512Meg?");
421 va = MIPS_PHYS_TO_DIRECT(pa);
422 bzero((caddr_t)va, size);
427 * Bootstrap the system enough to run with virtual memory. This
428 * assumes that the phys_avail array has been initialized.
431 pmap_create_kernel_pagetable(void)
443 * Allocate segment table for the kernel
445 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE);
448 * Allocate second level page tables for the kernel
451 npde = howmany(NKPT, NPDEPG);
452 pdaddr = pmap_steal_memory(PAGE_SIZE * npde);
455 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt);
458 * The R[4-7]?00 stores only one copy of the Global bit in the
459 * translation lookaside buffer for each 2 page entry. Thus invalid
460 * entrys must have the Global bit set so when Entry LO and Entry HI
461 * G bits are anded together they will produce a global bit to store
464 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++)
468 for (i = 0, npt = nkpt; npt > 0; i++) {
469 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE);
470 pde = (pd_entry_t *)kernel_segmap[i];
472 for (j = 0; j < NPDEPG && npt > 0; j++, npt--)
473 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE);
476 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++)
477 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE));
480 PMAP_LOCK_INIT(kernel_pmap);
481 kernel_pmap->pm_segtab = kernel_segmap;
482 CPU_FILL(&kernel_pmap->pm_active);
483 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
484 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
485 kernel_pmap->pm_asid[0].gen = 0;
486 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE;
496 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
498 * Keep the memory aligned on page boundary.
500 phys_avail[i] = round_page(phys_avail[i]);
501 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
505 if (phys_avail[i - 2] > phys_avail[i]) {
508 ptemp[0] = phys_avail[i + 0];
509 ptemp[1] = phys_avail[i + 1];
511 phys_avail[i + 0] = phys_avail[i - 2];
512 phys_avail[i + 1] = phys_avail[i - 1];
514 phys_avail[i - 2] = ptemp[0];
515 phys_avail[i - 1] = ptemp[1];
521 * In 32 bit, we may have memory which cannot be mapped directly.
522 * This memory will need temporary mapping before it can be
525 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1))
526 need_local_mappings = 1;
529 * Copy the phys_avail[] array before we start stealing memory from it.
531 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
532 physmem_desc[i] = phys_avail[i];
533 physmem_desc[i + 1] = phys_avail[i + 1];
536 Maxmem = atop(phys_avail[i - 1]);
539 printf("Physical memory chunk(s):\n");
540 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
543 size = phys_avail[i + 1] - phys_avail[i];
544 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n",
545 (uintmax_t) phys_avail[i],
546 (uintmax_t) phys_avail[i + 1] - 1,
547 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE);
549 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem));
552 * Steal the message buffer from the beginning of memory.
554 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize);
555 msgbufinit(msgbufp, msgbufsize);
558 * Steal thread0 kstack.
560 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
562 virtual_avail = VM_MIN_KERNEL_ADDRESS;
563 virtual_end = VM_MAX_KERNEL_ADDRESS;
567 * Steal some virtual address space to map the pcpu area.
569 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2);
570 pcpup = (struct pcpu *)virtual_avail;
571 virtual_avail += PAGE_SIZE * 2;
574 * Initialize the wired TLB entry mapping the pcpu region for
575 * the BSP at 'pcpup'. Up until this point we were operating
576 * with the 'pcpup' for the BSP pointing to a virtual address
577 * in KSEG0 so there was no need for a TLB mapping.
579 mips_pcpu_tlb_init(PCPU_ADDR(0));
582 printf("pcpu is available at virtual address %p.\n", pcpup);
585 pmap_create_kernel_pagetable();
586 if (need_local_mappings)
587 pmap_alloc_lmem_map();
588 pmap_max_asid = VMNUM_PIDS;
593 * Initialize the global pv list lock.
595 rw_init(&pvh_global_lock, "pmap pv global");
599 * Initialize a vm_page's machine-dependent fields.
602 pmap_page_init(vm_page_t m)
605 TAILQ_INIT(&m->md.pv_list);
606 m->md.pv_flags = VM_MEMATTR_DEFAULT << PV_MEMATTR_SHIFT;
610 * Initialize the pmap module.
611 * Called by vm_init, to initialize any structures that the pmap
612 * system needs to map virtual memory.
619 /***************************************************
620 * Low level helper routines.....
621 ***************************************************/
625 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
627 int cpuid, cpu, self;
628 cpuset_t active_cpus;
631 if (is_kernel_pmap(pmap)) {
632 smp_rendezvous(NULL, fn, NULL, arg);
635 /* Force ASID update on inactive CPUs */
637 if (!CPU_ISSET(cpu, &pmap->pm_active))
638 pmap->pm_asid[cpu].gen = 0;
640 cpuid = PCPU_GET(cpuid);
642 * XXX: barrier/locking for active?
644 * Take a snapshot of active here, any further changes are ignored.
645 * tlb update/invalidate should be harmless on inactive CPUs
647 active_cpus = pmap->pm_active;
648 self = CPU_ISSET(cpuid, &active_cpus);
649 CPU_CLR(cpuid, &active_cpus);
650 /* Optimize for the case where this cpu is the only active one */
651 if (CPU_EMPTY(&active_cpus)) {
656 CPU_SET(cpuid, &active_cpus);
657 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg);
664 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
668 if (is_kernel_pmap(pmap)) {
672 cpuid = PCPU_GET(cpuid);
673 if (!CPU_ISSET(cpuid, &pmap->pm_active))
674 pmap->pm_asid[cpuid].gen = 0;
681 pmap_invalidate_all(pmap_t pmap)
684 pmap_call_on_active_cpus(pmap,
685 (void (*)(void *))tlb_invalidate_all_user, pmap);
688 struct pmap_invalidate_page_arg {
694 pmap_invalidate_page_action(void *arg)
696 struct pmap_invalidate_page_arg *p = arg;
698 tlb_invalidate_address(p->pmap, p->va);
702 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
704 struct pmap_invalidate_page_arg arg;
708 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg);
711 struct pmap_invalidate_range_arg {
718 pmap_invalidate_range_action(void *arg)
720 struct pmap_invalidate_range_arg *p = arg;
722 tlb_invalidate_range(p->pmap, p->sva, p->eva);
726 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
728 struct pmap_invalidate_range_arg arg;
733 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg);
736 struct pmap_update_page_arg {
743 pmap_update_page_action(void *arg)
745 struct pmap_update_page_arg *p = arg;
747 tlb_update(p->pmap, p->va, p->pte);
751 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte)
753 struct pmap_update_page_arg arg;
758 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg);
762 * Routine: pmap_extract
764 * Extract the physical page address associated
765 * with the given map/virtual_address pair.
768 pmap_extract(pmap_t pmap, vm_offset_t va)
771 vm_offset_t retval = 0;
774 pte = pmap_pte(pmap, va);
776 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK);
783 * Routine: pmap_extract_and_hold
785 * Atomically extract and hold the physical page
786 * with the given pmap and virtual address pair
787 * if that mapping permits the given protection.
790 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
792 pt_entry_t pte, *ptep;
798 ptep = pmap_pte(pmap, va);
801 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) ||
802 (prot & VM_PROT_WRITE) == 0)) {
803 pa = TLBLO_PTE_TO_PA(pte);
804 m = PHYS_TO_VM_PAGE(pa);
805 if (!vm_page_wire_mapped(m))
813 /***************************************************
814 * Low level mapping routines.....
815 ***************************************************/
818 * add a wired page to the kva
821 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
824 pt_entry_t opte, npte;
827 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
830 pte = pmap_pte(kernel_pmap, va);
832 npte = TLBLO_PA_TO_PFN(pa) | PTE_C(ma) | PTE_D | PTE_V | PTE_G;
834 if (pte_test(&opte, PTE_V) && opte != npte)
835 pmap_update_page(kernel_pmap, va, npte);
839 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
842 KASSERT(is_cacheable_mem(pa),
843 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa));
845 pmap_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
849 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
852 KASSERT((size & PAGE_MASK) == 0,
853 ("%s: device mapping not page-sized", __func__));
855 for (; size > 0; size -= PAGE_SIZE) {
857 * XXXCEM: this is somewhat inefficient on SMP systems in that
858 * every single page is individually TLB-invalidated via
859 * rendezvous (pmap_update_page()), instead of invalidating the
860 * entire range via a single rendezvous.
862 pmap_kenter_attr(va, pa, VM_MEMATTR_UNCACHEABLE);
869 pmap_kremove_device(vm_offset_t va, vm_size_t size)
872 KASSERT((size & PAGE_MASK) == 0,
873 ("%s: device mapping not page-sized", __func__));
876 * XXXCEM: Similar to pmap_kenter_device, this is inefficient on SMP,
877 * in that pages are invalidated individually instead of a single range
880 for (; size > 0; size -= PAGE_SIZE) {
887 * remove a page from the kernel pagetables
889 /* PMAP_INLINE */ void
890 pmap_kremove(vm_offset_t va)
895 * Write back all caches from the page being destroyed
897 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
899 pte = pmap_pte(kernel_pmap, va);
901 pmap_invalidate_page(kernel_pmap, va);
905 * Used to map a range of physical addresses into kernel
906 * virtual address space.
908 * The value passed in '*virt' is a suggested virtual address for
909 * the mapping. Architectures which can support a direct-mapped
910 * physical to virtual region can return the appropriate address
911 * within that region, leaving '*virt' unchanged. Other
912 * architectures should map the pages starting at '*virt' and
913 * update '*virt' with the first usable address after the mapped
916 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
919 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
923 if (MIPS_DIRECT_MAPPABLE(end - 1))
924 return (MIPS_PHYS_TO_DIRECT(start));
927 while (start < end) {
928 pmap_kenter(va, start);
937 * Add a list of wired pages to the kva
938 * this routine is only used for temporary
939 * kernel mappings that do not need to have
940 * page modification or references recorded.
941 * Note that old mappings are simply written
942 * over. The page *must* be wired.
945 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
948 vm_offset_t origva = va;
950 for (i = 0; i < count; i++) {
951 pmap_flush_pvcache(m[i]);
952 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i]));
956 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count);
960 * this routine jerks page mappings from the
961 * kernel -- it is meant only for temporary mappings.
964 pmap_qremove(vm_offset_t va, int count)
971 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count);
974 pte = pmap_pte(kernel_pmap, va);
977 } while (--count > 0);
978 pmap_invalidate_range(kernel_pmap, origva, va);
981 /***************************************************
982 * Page table page management routines.....
983 ***************************************************/
986 * Decrements a page table page's reference count, which is used to record the
987 * number of valid page table entries within the page. If the reference count
988 * drops to zero, then the page table page is unmapped. Returns TRUE if the
989 * page table page was unmapped and FALSE otherwise.
991 static PMAP_INLINE boolean_t
992 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
996 if (m->ref_count == 0) {
997 _pmap_unwire_ptp(pmap, va, m);
1004 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
1007 vm_offset_t sva, eva;
1009 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1011 * unmap the page table page
1014 if (m->pindex < NUPDE) {
1015 pde = pmap_pde(pmap, va);
1016 sva = va & ~PDRMASK;
1019 pde = pmap_segmap(pmap, va);
1020 sva = va & ~SEGMASK;
1024 pde = pmap_pde(pmap, va);
1025 sva = va & ~SEGMASK;
1029 pmap->pm_stats.resident_count--;
1032 if (m->pindex < NUPDE) {
1037 * Recursively decrement next level pagetable refcount.
1038 * Either that shoots down a larger range from TLBs (below)
1039 * or we're to shoot down just the page in question.
1041 pdp = (pd_entry_t *)*pmap_segmap(pmap, va);
1042 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp));
1043 if (!pmap_unwire_ptp(pmap, va, pdpg)) {
1044 pmap_invalidate_range(pmap, sva, eva);
1047 /* Segmap entry shootdown */
1048 pmap_invalidate_range(pmap, sva, eva);
1051 /* Segmap entry shootdown */
1052 pmap_invalidate_range(pmap, sva, eva);
1056 * If the page is finally unwired, simply free it.
1058 vm_page_free_zero(m);
1063 * After removing a page table entry, this routine is used to
1064 * conditionally free the page, and manage the reference count.
1067 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1071 if (va >= VM_MAXUSER_ADDRESS)
1073 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0"));
1074 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde));
1075 return (pmap_unwire_ptp(pmap, va, mpte));
1079 pmap_pinit0(pmap_t pmap)
1083 PMAP_LOCK_INIT(pmap);
1084 pmap->pm_segtab = kernel_segmap;
1085 CPU_ZERO(&pmap->pm_active);
1086 for (i = 0; i < MAXCPU; i++) {
1087 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1088 pmap->pm_asid[i].gen = 0;
1090 PCPU_SET(curpmap, pmap);
1091 TAILQ_INIT(&pmap->pm_pvchunk);
1092 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1096 pmap_grow_direct_page(int req)
1102 if (!vm_page_reclaim_contig(req, 1, 0, MIPS_KSEG0_LARGEST_PHYS,
1109 pmap_alloc_direct_page(unsigned int index, int req)
1113 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED |
1118 if ((m->flags & PG_ZERO) == 0)
1126 * Initialize a preallocated and zeroed pmap structure,
1127 * such as one in a vmspace structure.
1130 pmap_pinit(pmap_t pmap)
1137 * allocate the page directory page
1139 req_class = VM_ALLOC_NORMAL;
1140 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, req_class)) ==
1142 pmap_grow_direct_page(req_class);
1144 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg));
1145 pmap->pm_segtab = (pd_entry_t *)ptdva;
1146 CPU_ZERO(&pmap->pm_active);
1147 for (i = 0; i < MAXCPU; i++) {
1148 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1149 pmap->pm_asid[i].gen = 0;
1151 TAILQ_INIT(&pmap->pm_pvchunk);
1152 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1158 * this routine is called if the page table page is not
1162 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags)
1169 * Find or fabricate a new pagetable page
1171 req_class = VM_ALLOC_NORMAL;
1172 if ((m = pmap_alloc_direct_page(ptepindex, req_class)) == NULL) {
1173 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1175 rw_wunlock(&pvh_global_lock);
1176 pmap_grow_direct_page(req_class);
1177 rw_wlock(&pvh_global_lock);
1182 * Indicate the need to retry. While waiting, the page
1183 * table page may have been allocated.
1189 * Map the pagetable page into the process address space, if it
1190 * isn't already there.
1192 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1195 if (ptepindex >= NUPDE) {
1196 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva;
1198 pd_entry_t *pdep, *pde;
1199 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT);
1200 int pdeindex = ptepindex & (NPDEPG - 1);
1203 pdep = &pmap->pm_segtab[segindex];
1204 if (*pdep == NULL) {
1205 /* recurse for allocating page dir */
1206 if (_pmap_allocpte(pmap, NUPDE + segindex,
1208 /* alloc failed, release current */
1209 vm_page_unwire_noq(m);
1210 vm_page_free_zero(m);
1214 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep));
1217 /* Next level entry */
1218 pde = (pd_entry_t *)*pdep;
1219 pde[pdeindex] = (pd_entry_t)pageva;
1222 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva;
1224 pmap->pm_stats.resident_count++;
1229 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1236 * Calculate pagetable page index
1238 ptepindex = pmap_pde_pindex(va);
1241 * Get the page directory entry
1243 pde = pmap_pde(pmap, va);
1246 * If the page table page is mapped, we just increment the hold
1247 * count, and activate it.
1249 if (pde != NULL && *pde != NULL) {
1250 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde));
1254 * Here if the pte page isn't mapped, or if it has been
1257 m = _pmap_allocpte(pmap, ptepindex, flags);
1258 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1265 /***************************************************
1266 * Pmap allocation/deallocation routines.
1267 ***************************************************/
1270 * Release any resources held by the given physical map.
1271 * Called when a pmap initialized by pmap_pinit is being released.
1272 * Should only be called if the map contains no valid mappings.
1275 pmap_release(pmap_t pmap)
1280 KASSERT(pmap->pm_stats.resident_count == 0,
1281 ("pmap_release: pmap resident count %ld != 0",
1282 pmap->pm_stats.resident_count));
1284 ptdva = (vm_offset_t)pmap->pm_segtab;
1285 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva));
1287 vm_page_unwire_noq(ptdpg);
1288 vm_page_free_zero(ptdpg);
1292 * grow the number of kernel page table entries, if needed
1295 pmap_growkernel(vm_offset_t addr)
1298 pd_entry_t *pde, *pdpe;
1302 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1303 req_class = VM_ALLOC_INTERRUPT;
1304 addr = roundup2(addr, NBSEG);
1305 if (addr - 1 >= vm_map_max(kernel_map))
1306 addr = vm_map_max(kernel_map);
1307 while (kernel_vm_end < addr) {
1308 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end);
1311 /* new intermediate page table entry */
1312 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1314 panic("pmap_growkernel: no memory to grow kernel");
1315 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1316 continue; /* try again */
1319 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
1321 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1322 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1323 kernel_vm_end = vm_map_max(kernel_map);
1330 * This index is bogus, but out of the way
1332 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1334 if (nkpg == NULL && vm_page_reclaim_contig(req_class, 1,
1335 0, MIPS_KSEG0_LARGEST_PHYS, PAGE_SIZE, 0))
1336 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1339 panic("pmap_growkernel: no memory to grow kernel");
1341 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1344 * The R[4-7]?00 stores only one copy of the Global bit in
1345 * the translation lookaside buffer for each 2 page entry.
1346 * Thus invalid entrys must have the Global bit set so when
1347 * Entry LO and Entry HI G bits are anded together they will
1348 * produce a global bit to store in the tlb.
1350 pte = (pt_entry_t *)*pde;
1351 for (i = 0; i < NPTEPG; i++)
1354 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1355 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1356 kernel_vm_end = vm_map_max(kernel_map);
1362 /***************************************************
1363 * page management routines.
1364 ***************************************************/
1366 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1368 CTASSERT(_NPCM == 3);
1369 CTASSERT(_NPCPV == 168);
1371 CTASSERT(_NPCM == 11);
1372 CTASSERT(_NPCPV == 336);
1375 static __inline struct pv_chunk *
1376 pv_to_chunk(pv_entry_t pv)
1379 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1382 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1385 #define PC_FREE0_1 0xfffffffffffffffful
1386 #define PC_FREE2 0x000000fffffffffful
1388 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
1389 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
1392 static const u_long pc_freemask[_NPCM] = {
1394 PC_FREE0_1, PC_FREE0_1, PC_FREE2
1396 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1397 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1398 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1399 PC_FREE0_9, PC_FREE10
1403 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1404 "VM/pmap parameters");
1406 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1407 "Current number of pv entries");
1410 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1412 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1413 "Current number of pv entry chunks");
1414 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1415 "Current number of pv entry chunks allocated");
1416 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1417 "Current number of pv entry chunks frees");
1418 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1419 "Number of times tried to get a chunk page but failed.");
1421 static long pv_entry_frees, pv_entry_allocs;
1422 static int pv_entry_spare;
1424 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1425 "Current number of pv entry frees");
1426 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1427 "Current number of pv entry allocs");
1428 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1429 "Current number of spare pv entries");
1433 * We are in a serious low memory condition. Resort to
1434 * drastic measures to free some pages so we can allocate
1435 * another pv entry chunk.
1438 pmap_pv_reclaim(pmap_t locked_pmap)
1441 struct pv_chunk *pc;
1444 pt_entry_t *pte, oldpte;
1449 int bit, field, freed, idx;
1451 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1454 TAILQ_INIT(&newtail);
1455 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) {
1456 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1457 if (pmap != pc->pc_pmap) {
1459 pmap_invalidate_all(pmap);
1460 if (pmap != locked_pmap)
1464 /* Avoid deadlock and lock recursion. */
1465 if (pmap > locked_pmap)
1467 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
1469 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1475 * Destroy every non-wired, 4 KB page mapping in the chunk.
1478 for (field = 0; field < _NPCM; field++) {
1479 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1480 inuse != 0; inuse &= ~(1UL << bit)) {
1481 bit = ffsl(inuse) - 1;
1482 idx = field * sizeof(inuse) * NBBY + bit;
1483 pv = &pc->pc_pventry[idx];
1485 pde = pmap_pde(pmap, va);
1486 KASSERT(pde != NULL && *pde != 0,
1487 ("pmap_pv_reclaim: pde"));
1488 pte = pmap_pde_to_pte(pde, va);
1490 if (pte_test(&oldpte, PTE_W))
1492 if (is_kernel_pmap(pmap))
1496 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte));
1497 if (pte_test(&oldpte, PTE_D))
1499 if (m->md.pv_flags & PV_TABLE_REF)
1500 vm_page_aflag_set(m, PGA_REFERENCED);
1501 m->md.pv_flags &= ~PV_TABLE_REF;
1502 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1503 if (TAILQ_EMPTY(&m->md.pv_list))
1504 vm_page_aflag_clear(m, PGA_WRITEABLE);
1505 pc->pc_map[field] |= 1UL << bit;
1508 * For simplicity, we will unconditionally shoot
1509 * down TLBs either at the end of this function
1510 * or at the top of the loop above if we switch
1511 * to a different pmap.
1513 (void)pmap_unuse_pt(pmap, va, *pde);
1519 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1522 /* Every freed mapping is for a 4 KB page. */
1523 pmap->pm_stats.resident_count -= freed;
1524 PV_STAT(pv_entry_frees += freed);
1525 PV_STAT(pv_entry_spare += freed);
1526 pv_entry_count -= freed;
1527 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1528 for (field = 0; field < _NPCM; field++)
1529 if (pc->pc_map[field] != pc_freemask[field]) {
1530 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1532 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1535 * One freed pv entry in locked_pmap is
1538 if (pmap == locked_pmap)
1542 if (field == _NPCM) {
1543 PV_STAT(pv_entry_spare -= _NPCPV);
1544 PV_STAT(pc_chunk_count--);
1545 PV_STAT(pc_chunk_frees++);
1546 /* Entire chunk is free; return it. */
1547 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(
1549 dump_drop_page(m_pc->phys_addr);
1554 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
1556 pmap_invalidate_all(pmap);
1557 if (pmap != locked_pmap)
1564 * free the pv_entry back to the free list
1567 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1569 struct pv_chunk *pc;
1570 int bit, field, idx;
1572 rw_assert(&pvh_global_lock, RA_WLOCKED);
1573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1574 PV_STAT(pv_entry_frees++);
1575 PV_STAT(pv_entry_spare++);
1577 pc = pv_to_chunk(pv);
1578 idx = pv - &pc->pc_pventry[0];
1579 field = idx / (sizeof(u_long) * NBBY);
1580 bit = idx % (sizeof(u_long) * NBBY);
1581 pc->pc_map[field] |= 1ul << bit;
1582 for (idx = 0; idx < _NPCM; idx++)
1583 if (pc->pc_map[idx] != pc_freemask[idx]) {
1585 * 98% of the time, pc is already at the head of the
1586 * list. If it isn't already, move it to the head.
1588 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
1590 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1591 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1596 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1601 free_pv_chunk(struct pv_chunk *pc)
1605 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1606 PV_STAT(pv_entry_spare -= _NPCPV);
1607 PV_STAT(pc_chunk_count--);
1608 PV_STAT(pc_chunk_frees++);
1609 /* entire chunk is free, return it */
1610 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc));
1611 dump_drop_page(m->phys_addr);
1612 vm_page_unwire_noq(m);
1617 * get a new pv_entry, allocating a block from the system
1621 get_pv_entry(pmap_t pmap, boolean_t try)
1623 struct pv_chunk *pc;
1626 int bit, field, idx;
1628 rw_assert(&pvh_global_lock, RA_WLOCKED);
1629 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1630 PV_STAT(pv_entry_allocs++);
1633 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1635 for (field = 0; field < _NPCM; field++) {
1636 if (pc->pc_map[field]) {
1637 bit = ffsl(pc->pc_map[field]) - 1;
1641 if (field < _NPCM) {
1642 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
1643 pv = &pc->pc_pventry[idx];
1644 pc->pc_map[field] &= ~(1ul << bit);
1645 /* If this was the last item, move it to tail */
1646 for (field = 0; field < _NPCM; field++)
1647 if (pc->pc_map[field] != 0) {
1648 PV_STAT(pv_entry_spare--);
1649 return (pv); /* not full, return */
1651 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1652 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
1653 PV_STAT(pv_entry_spare--);
1657 /* No free items, allocate another chunk */
1658 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL |
1663 PV_STAT(pc_chunk_tryfail++);
1666 m = pmap_pv_reclaim(pmap);
1670 PV_STAT(pc_chunk_count++);
1671 PV_STAT(pc_chunk_allocs++);
1672 dump_add_page(m->phys_addr);
1673 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1675 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
1676 for (field = 1; field < _NPCM; field++)
1677 pc->pc_map[field] = pc_freemask[field];
1678 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1679 pv = &pc->pc_pventry[0];
1680 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1681 PV_STAT(pv_entry_spare += _NPCPV - 1);
1686 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1690 rw_assert(&pvh_global_lock, RA_WLOCKED);
1691 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
1692 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1693 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
1701 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1705 pv = pmap_pvh_remove(pvh, pmap, va);
1706 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx",
1707 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)),
1709 free_pv_entry(pmap, pv);
1713 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
1716 rw_assert(&pvh_global_lock, RA_WLOCKED);
1717 pmap_pvh_free(&m->md, pmap, va);
1718 if (TAILQ_EMPTY(&m->md.pv_list))
1719 vm_page_aflag_clear(m, PGA_WRITEABLE);
1723 * Conditionally create a pv entry.
1726 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va,
1731 rw_assert(&pvh_global_lock, RA_WLOCKED);
1732 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1733 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
1735 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
1742 * pmap_remove_pte: do the things to unmap a page in a process
1744 * Returns true if this was the last PTE in the PT (and possibly the last PT in
1745 * the PD, and possibly the last PD in the segmap), in which case...
1747 * 1) the TLB has been invalidated for the whole PT's span (at least),
1748 * already, to ensure that MipsDoTLBMiss does not attempt to follow a
1749 * dangling pointer into a freed page. No additional TLB shootdown is
1752 * 2) if this removal was part of a sweep to remove PTEs, it is safe to jump
1753 * to the PT span boundary and continue.
1755 * 3) The given pde may now point onto a freed page and must not be
1758 * If the return value is false, the TLB has not been shot down (and the segmap
1759 * entry, PD, and PT all remain in place).
1762 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
1769 rw_assert(&pvh_global_lock, RA_WLOCKED);
1770 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1773 * Write back all cache lines from the page being unmapped.
1775 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
1778 if (is_kernel_pmap(pmap))
1783 if (pte_test(&oldpte, PTE_W))
1784 pmap->pm_stats.wired_count -= 1;
1786 pmap->pm_stats.resident_count -= 1;
1788 if (pte_test(&oldpte, PTE_MANAGED)) {
1789 pa = TLBLO_PTE_TO_PA(oldpte);
1790 m = PHYS_TO_VM_PAGE(pa);
1791 if (pte_test(&oldpte, PTE_D)) {
1792 KASSERT(!pte_test(&oldpte, PTE_RO),
1793 ("%s: modified page not writable: va: %p, pte: %#jx",
1794 __func__, (void *)va, (uintmax_t)oldpte));
1797 if (m->md.pv_flags & PV_TABLE_REF)
1798 vm_page_aflag_set(m, PGA_REFERENCED);
1799 m->md.pv_flags &= ~PV_TABLE_REF;
1801 pmap_remove_entry(pmap, m, va);
1803 return (pmap_unuse_pt(pmap, va, pde));
1807 * Remove a single page from a process address space
1810 pmap_remove_page(struct pmap *pmap, vm_offset_t va)
1815 rw_assert(&pvh_global_lock, RA_WLOCKED);
1816 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1817 pde = pmap_pde(pmap, va);
1818 if (pde == NULL || *pde == 0)
1820 ptq = pmap_pde_to_pte(pde, va);
1823 * If there is no pte for this address, just skip it!
1825 if (!pte_test(ptq, PTE_V))
1829 * Remove this PTE from the PT. If this is the last one, then
1830 * the TLB has already been shot down, so don't bother again
1832 if (!pmap_remove_pte(pmap, ptq, va, *pde))
1833 pmap_invalidate_page(pmap, va);
1837 * Remove the given range of addresses from the specified map.
1839 * It is assumed that the start and end are properly
1840 * rounded to the page size.
1843 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1845 pd_entry_t *pde, *pdpe;
1847 vm_offset_t va_next;
1848 vm_offset_t va_init, va_fini;
1849 bool need_tlb_shootdown;
1852 * Perform an unsynchronized read. This is, however, safe.
1854 if (pmap->pm_stats.resident_count == 0)
1857 rw_wlock(&pvh_global_lock);
1861 * special handling of removing one page. a very common operation
1862 * and easy to short circuit some code.
1864 if ((sva + PAGE_SIZE) == eva) {
1865 pmap_remove_page(pmap, sva);
1868 for (; sva < eva; sva = va_next) {
1869 pdpe = pmap_segmap(pmap, sva);
1872 va_next = (sva + NBSEG) & ~SEGMASK;
1879 /* Scan up to the end of the page table pointed to by pde */
1880 va_next = (sva + NBPDR) & ~PDRMASK;
1884 pde = pmap_pdpe_to_pde(pdpe, sva);
1889 * Limit our scan to either the end of the va represented
1890 * by the current page table page, or to the end of the
1891 * range being removed.
1896 need_tlb_shootdown = false;
1899 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1902 /* Skip over invalid entries; no need to shootdown */
1903 if (!pte_test(pte, PTE_V)) {
1905 * If we have not yet found a valid entry, then
1906 * we can move the lower edge of the region to
1907 * invalidate to the next PTE.
1909 if (!need_tlb_shootdown)
1910 va_init = sva + PAGE_SIZE;
1915 * A valid entry; the range we are shooting down must
1916 * include this page. va_fini is used instead of sva
1917 * so that if the range ends with a run of !PTE_V PTEs,
1918 * but doesn't clear out so much that pmap_remove_pte
1919 * removes the entire PT, we won't include these !PTE_V
1920 * entries in the region to be shot down.
1922 va_fini = sva + PAGE_SIZE;
1924 if (pmap_remove_pte(pmap, pte, sva, *pde)) {
1925 /* Entire PT removed and TLBs shot down. */
1926 need_tlb_shootdown = false;
1929 need_tlb_shootdown = true;
1932 if (need_tlb_shootdown)
1933 pmap_invalidate_range(pmap, va_init, va_fini);
1936 rw_wunlock(&pvh_global_lock);
1941 * Routine: pmap_remove_all
1943 * Removes this physical page from
1944 * all physical maps in which it resides.
1945 * Reflects back modify bits to the pager.
1948 * Original versions of this routine were very
1949 * inefficient because they iteratively called
1950 * pmap_remove (slow...)
1954 pmap_remove_all(vm_page_t m)
1959 pt_entry_t *pte, tpte;
1961 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1962 ("pmap_remove_all: page %p is not managed", m));
1963 rw_wlock(&pvh_global_lock);
1965 if (m->md.pv_flags & PV_TABLE_REF)
1966 vm_page_aflag_set(m, PGA_REFERENCED);
1968 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
1973 * If it's last mapping writeback all caches from
1974 * the page being destroyed
1976 if (TAILQ_NEXT(pv, pv_list) == NULL)
1977 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
1979 pmap->pm_stats.resident_count--;
1981 pde = pmap_pde(pmap, pv->pv_va);
1982 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde"));
1983 pte = pmap_pde_to_pte(pde, pv->pv_va);
1986 if (is_kernel_pmap(pmap))
1991 if (pte_test(&tpte, PTE_W))
1992 pmap->pm_stats.wired_count--;
1995 * Update the vm_page_t clean and reference bits.
1997 if (pte_test(&tpte, PTE_D)) {
1998 KASSERT(!pte_test(&tpte, PTE_RO),
1999 ("%s: modified page not writable: va: %p, pte: %#jx",
2000 __func__, (void *)pv->pv_va, (uintmax_t)tpte));
2004 if (!pmap_unuse_pt(pmap, pv->pv_va, *pde))
2005 pmap_invalidate_page(pmap, pv->pv_va);
2007 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2008 free_pv_entry(pmap, pv);
2012 vm_page_aflag_clear(m, PGA_WRITEABLE);
2013 m->md.pv_flags &= ~PV_TABLE_REF;
2014 rw_wunlock(&pvh_global_lock);
2018 * Set the physical protection on the
2019 * specified range of this map as requested.
2022 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2024 pt_entry_t pbits, *pte;
2025 pd_entry_t *pde, *pdpe;
2026 vm_offset_t va, va_next;
2030 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2031 pmap_remove(pmap, sva, eva);
2034 if (prot & VM_PROT_WRITE)
2038 for (; sva < eva; sva = va_next) {
2039 pdpe = pmap_segmap(pmap, sva);
2042 va_next = (sva + NBSEG) & ~SEGMASK;
2048 va_next = (sva + NBPDR) & ~PDRMASK;
2052 pde = pmap_pdpe_to_pde(pdpe, sva);
2057 * Limit our scan to either the end of the va represented
2058 * by the current page table page, or to the end of the
2059 * range being write protected.
2065 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2068 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits,
2070 if (va != va_next) {
2071 pmap_invalidate_range(pmap, va, sva);
2076 pte_set(&pbits, PTE_RO);
2077 if (pte_test(&pbits, PTE_D)) {
2078 pte_clear(&pbits, PTE_D);
2079 if (pte_test(&pbits, PTE_MANAGED)) {
2080 pa = TLBLO_PTE_TO_PA(pbits);
2081 m = PHYS_TO_VM_PAGE(pa);
2088 * Unless PTE_D is set, any TLB entries
2089 * mapping "sva" don't allow write access, so
2090 * they needn't be invalidated.
2092 if (va != va_next) {
2093 pmap_invalidate_range(pmap, va, sva);
2100 pmap_invalidate_range(pmap, va, sva);
2106 * Insert the given physical page (p) at
2107 * the specified virtual address (v) in the
2108 * target physical map with the protection requested.
2110 * If specified, the page will be wired down, meaning
2111 * that the related pte can not be reclaimed.
2113 * NB: This is the only routine which MAY NOT lazy-evaluate
2114 * or lose information. That is, this routine must actually
2115 * insert this page into the given map NOW.
2118 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2119 u_int flags, int8_t psind __unused)
2123 pt_entry_t origpte, newpte;
2128 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2129 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
2130 va >= kmi.clean_eva,
2131 ("pmap_enter: managed mapping within the clean submap"));
2132 if ((m->oflags & VPO_UNMANAGED) == 0)
2133 VM_PAGE_OBJECT_BUSY_ASSERT(m);
2134 pa = VM_PAGE_TO_PHYS(m);
2135 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot);
2136 if ((flags & PMAP_ENTER_WIRED) != 0)
2138 if (is_kernel_pmap(pmap))
2140 PMAP_PTE_SET_CACHE_BITS(newpte, pa, m);
2141 if ((m->oflags & VPO_UNMANAGED) == 0)
2142 newpte |= PTE_MANAGED;
2146 rw_wlock(&pvh_global_lock);
2150 * In the case that a page table page is not resident, we are
2153 if (va < VM_MAXUSER_ADDRESS) {
2154 mpte = pmap_allocpte(pmap, va, flags);
2156 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
2157 ("pmap_allocpte failed with sleep allowed"));
2158 rw_wunlock(&pvh_global_lock);
2160 return (KERN_RESOURCE_SHORTAGE);
2163 pte = pmap_pte(pmap, va);
2166 * Page Directory table entry not valid, we need a new PT page
2169 panic("pmap_enter: invalid page directory, pdir=%p, va=%p",
2170 (void *)pmap->pm_segtab, (void *)va);
2174 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO | PTE_V),
2175 ("pmap_enter: modified page not writable: va: %p, pte: %#jx",
2176 (void *)va, (uintmax_t)origpte));
2177 opa = TLBLO_PTE_TO_PA(origpte);
2180 * Mapping has not changed, must be protection or wiring change.
2182 if (pte_test(&origpte, PTE_V) && opa == pa) {
2184 * Wiring change, just update stats. We don't worry about
2185 * wiring PT pages as they remain resident as long as there
2186 * are valid mappings in them. Hence, if a user page is
2187 * wired, the PT page will be also.
2189 if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W))
2190 pmap->pm_stats.wired_count++;
2191 else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte,
2193 pmap->pm_stats.wired_count--;
2196 * Remove extra pte reference
2201 if (pte_test(&origpte, PTE_MANAGED)) {
2202 m->md.pv_flags |= PV_TABLE_REF;
2203 if (!pte_test(&newpte, PTE_RO))
2204 vm_page_aflag_set(m, PGA_WRITEABLE);
2212 * Mapping has changed, invalidate old range and fall through to
2213 * handle validating new mapping.
2216 if (is_kernel_pmap(pmap))
2220 if (pte_test(&origpte, PTE_W))
2221 pmap->pm_stats.wired_count--;
2222 if (pte_test(&origpte, PTE_MANAGED)) {
2223 om = PHYS_TO_VM_PAGE(opa);
2224 if (pte_test(&origpte, PTE_D))
2226 if ((om->md.pv_flags & PV_TABLE_REF) != 0) {
2227 om->md.pv_flags &= ~PV_TABLE_REF;
2228 vm_page_aflag_set(om, PGA_REFERENCED);
2230 pv = pmap_pvh_remove(&om->md, pmap, va);
2231 if (!pte_test(&newpte, PTE_MANAGED))
2232 free_pv_entry(pmap, pv);
2233 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
2234 TAILQ_EMPTY(&om->md.pv_list))
2235 vm_page_aflag_clear(om, PGA_WRITEABLE);
2237 pmap_invalidate_page(pmap, va);
2241 KASSERT(mpte->ref_count > 0,
2242 ("pmap_enter: missing reference to page table page,"
2243 " va: %p", (void *)va));
2246 pmap->pm_stats.resident_count++;
2249 * Enter on the PV list if part of our managed memory.
2251 if (pte_test(&newpte, PTE_MANAGED)) {
2252 m->md.pv_flags |= PV_TABLE_REF;
2254 pv = get_pv_entry(pmap, FALSE);
2257 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2258 if (!pte_test(&newpte, PTE_RO))
2259 vm_page_aflag_set(m, PGA_WRITEABLE);
2263 * Increment counters
2265 if (pte_test(&newpte, PTE_W))
2266 pmap->pm_stats.wired_count++;
2271 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
2275 * if the mapping or permission bits are different, we need to
2278 if (origpte != newpte) {
2280 if (pte_test(&origpte, PTE_V)) {
2281 KASSERT(opa == pa, ("pmap_enter: invalid update"));
2282 if (pte_test(&origpte, PTE_D)) {
2283 if (pte_test(&origpte, PTE_MANAGED))
2286 pmap_update_page(pmap, va, newpte);
2291 * Sync I & D caches for executable pages. Do this only if the
2292 * target pmap belongs to the current process. Otherwise, an
2293 * unresolvable TLB miss may occur.
2295 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
2296 (prot & VM_PROT_EXECUTE)) {
2297 mips_icache_sync_range(va, PAGE_SIZE);
2298 mips_dcache_wbinv_range(va, PAGE_SIZE);
2300 rw_wunlock(&pvh_global_lock);
2302 return (KERN_SUCCESS);
2306 * this code makes some *MAJOR* assumptions:
2307 * 1. Current pmap & pmap exists.
2310 * 4. No page table pages.
2311 * but is *MUCH* faster than pmap_enter...
2315 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2318 rw_wlock(&pvh_global_lock);
2320 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
2321 rw_wunlock(&pvh_global_lock);
2326 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2327 vm_prot_t prot, vm_page_t mpte)
2329 pt_entry_t *pte, npte;
2332 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2333 (m->oflags & VPO_UNMANAGED) != 0,
2334 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2335 rw_assert(&pvh_global_lock, RA_WLOCKED);
2336 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2339 * In the case that a page table page is not resident, we are
2342 if (va < VM_MAXUSER_ADDRESS) {
2347 * Calculate pagetable page index
2349 ptepindex = pmap_pde_pindex(va);
2350 if (mpte && (mpte->pindex == ptepindex)) {
2354 * Get the page directory entry
2356 pde = pmap_pde(pmap, va);
2359 * If the page table page is mapped, we just
2360 * increment the hold count, and activate it.
2362 if (pde && *pde != 0) {
2363 mpte = PHYS_TO_VM_PAGE(
2364 MIPS_DIRECT_TO_PHYS(*pde));
2367 mpte = _pmap_allocpte(pmap, ptepindex,
2368 PMAP_ENTER_NOSLEEP);
2377 pte = pmap_pte(pmap, va);
2378 if (pte_test(pte, PTE_V)) {
2387 * Enter on the PV list if part of our managed memory.
2389 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2390 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) {
2392 pmap_unwire_ptp(pmap, va, mpte);
2399 * Increment counters
2401 pmap->pm_stats.resident_count++;
2403 pa = VM_PAGE_TO_PHYS(m);
2406 * Now validate mapping with RO protection
2408 npte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V;
2409 if ((m->oflags & VPO_UNMANAGED) == 0)
2410 npte |= PTE_MANAGED;
2412 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2414 if (is_kernel_pmap(pmap))
2415 *pte = npte | PTE_G;
2419 * Sync I & D caches. Do this only if the target pmap
2420 * belongs to the current process. Otherwise, an
2421 * unresolvable TLB miss may occur. */
2422 if (pmap == &curproc->p_vmspace->vm_pmap) {
2424 mips_icache_sync_range(va, PAGE_SIZE);
2425 mips_dcache_wbinv_range(va, PAGE_SIZE);
2432 * Make a temporary mapping for a physical address. This is only intended
2433 * to be used for panic dumps.
2435 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2438 pmap_kenter_temporary(vm_paddr_t pa, int i)
2443 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
2446 if (MIPS_DIRECT_MAPPABLE(pa)) {
2447 va = MIPS_PHYS_TO_DIRECT(pa);
2449 #ifndef __mips_n64 /* XXX : to be converted to new style */
2450 pt_entry_t *pte, npte;
2452 pte = pmap_pte(kernel_pmap, crashdumpva);
2454 /* Since this is for the debugger, no locks or any other fun */
2455 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
2458 pmap_update_page(kernel_pmap, crashdumpva, npte);
2462 return ((void *)va);
2466 pmap_kenter_temporary_free(vm_paddr_t pa)
2468 #ifndef __mips_n64 /* XXX : to be converted to new style */
2471 if (MIPS_DIRECT_MAPPABLE(pa)) {
2472 /* nothing to do for this case */
2475 #ifndef __mips_n64 /* XXX : to be converted to new style */
2476 pte = pmap_pte(kernel_pmap, crashdumpva);
2478 pmap_invalidate_page(kernel_pmap, crashdumpva);
2483 * Maps a sequence of resident pages belonging to the same object.
2484 * The sequence begins with the given page m_start. This page is
2485 * mapped at the given virtual address start. Each subsequent page is
2486 * mapped at a virtual address that is offset from start by the same
2487 * amount as the page is offset from m_start within the object. The
2488 * last page in the sequence is the page with the largest offset from
2489 * m_start that can be mapped at a virtual address less than the given
2490 * virtual address end. Not every virtual page between start and end
2491 * is mapped; only those for which a resident page exists with the
2492 * corresponding offset from m_start are mapped.
2495 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2496 vm_page_t m_start, vm_prot_t prot)
2499 vm_pindex_t diff, psize;
2501 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2503 psize = atop(end - start);
2506 rw_wlock(&pvh_global_lock);
2508 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2509 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m,
2511 m = TAILQ_NEXT(m, listq);
2513 rw_wunlock(&pvh_global_lock);
2518 * pmap_object_init_pt preloads the ptes for a given object
2519 * into the specified pmap. This eliminates the blast of soft
2520 * faults on process startup and immediately after an mmap.
2523 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
2524 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2526 VM_OBJECT_ASSERT_WLOCKED(object);
2527 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2528 ("pmap_object_init_pt: non-device object"));
2532 * Clear the wired attribute from the mappings for the specified range of
2533 * addresses in the given pmap. Every valid mapping within that range
2534 * must have the wired attribute set. In contrast, invalid mappings
2535 * cannot have the wired attribute set, so they are ignored.
2537 * The wired attribute of the page table entry is not a hardware feature,
2538 * so there is no need to invalidate any TLB entries.
2541 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2543 pd_entry_t *pde, *pdpe;
2545 vm_offset_t va_next;
2548 for (; sva < eva; sva = va_next) {
2549 pdpe = pmap_segmap(pmap, sva);
2551 if (*pdpe == NULL) {
2552 va_next = (sva + NBSEG) & ~SEGMASK;
2558 va_next = (sva + NBPDR) & ~PDRMASK;
2561 pde = pmap_pdpe_to_pde(pdpe, sva);
2566 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2568 if (!pte_test(pte, PTE_V))
2570 if (!pte_test(pte, PTE_W))
2571 panic("pmap_unwire: pte %#jx is missing PG_W",
2573 pte_clear(pte, PTE_W);
2574 pmap->pm_stats.wired_count--;
2581 * Copy the range specified by src_addr/len
2582 * from the source map to the range dst_addr/len
2583 * in the destination map.
2585 * This routine is only advisory and need not do anything.
2589 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2590 vm_size_t len, vm_offset_t src_addr)
2595 * pmap_zero_page zeros the specified hardware page by mapping
2596 * the page into KVM and using bzero to clear its contents.
2598 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2601 pmap_zero_page(vm_page_t m)
2604 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2606 if (MIPS_DIRECT_MAPPABLE(phys)) {
2607 va = MIPS_PHYS_TO_DIRECT(phys);
2608 bzero((caddr_t)va, PAGE_SIZE);
2609 mips_dcache_wbinv_range(va, PAGE_SIZE);
2611 va = pmap_lmem_map1(phys);
2612 bzero((caddr_t)va, PAGE_SIZE);
2613 mips_dcache_wbinv_range(va, PAGE_SIZE);
2619 * pmap_zero_page_area zeros the specified hardware page by mapping
2620 * the page into KVM and using bzero to clear its contents.
2622 * off and size may not cover an area beyond a single hardware page.
2625 pmap_zero_page_area(vm_page_t m, int off, int size)
2628 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2630 if (MIPS_DIRECT_MAPPABLE(phys)) {
2631 va = MIPS_PHYS_TO_DIRECT(phys);
2632 bzero((char *)(caddr_t)va + off, size);
2633 mips_dcache_wbinv_range(va + off, size);
2635 va = pmap_lmem_map1(phys);
2636 bzero((char *)va + off, size);
2637 mips_dcache_wbinv_range(va + off, size);
2643 * pmap_copy_page copies the specified (machine independent)
2644 * page by mapping the page into virtual memory and using
2645 * bcopy to copy the page, one machine dependent page at a
2648 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2651 pmap_copy_page(vm_page_t src, vm_page_t dst)
2653 vm_offset_t va_src, va_dst;
2654 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src);
2655 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst);
2657 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) {
2658 /* easy case, all can be accessed via KSEG0 */
2660 * Flush all caches for VA that are mapped to this page
2661 * to make sure that data in SDRAM is up to date
2663 pmap_flush_pvcache(src);
2664 mips_dcache_wbinv_range_index(
2665 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE);
2666 va_src = MIPS_PHYS_TO_DIRECT(phys_src);
2667 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst);
2668 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
2669 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2671 va_src = pmap_lmem_map2(phys_src, phys_dst);
2672 va_dst = va_src + PAGE_SIZE;
2673 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE);
2674 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2679 int unmapped_buf_allowed;
2682 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2683 vm_offset_t b_offset, int xfersize)
2687 vm_offset_t a_pg_offset, b_pg_offset;
2688 vm_paddr_t a_phys, b_phys;
2691 while (xfersize > 0) {
2692 a_pg_offset = a_offset & PAGE_MASK;
2693 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2694 a_m = ma[a_offset >> PAGE_SHIFT];
2695 a_phys = VM_PAGE_TO_PHYS(a_m);
2696 b_pg_offset = b_offset & PAGE_MASK;
2697 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2698 b_m = mb[b_offset >> PAGE_SHIFT];
2699 b_phys = VM_PAGE_TO_PHYS(b_m);
2700 if (MIPS_DIRECT_MAPPABLE(a_phys) &&
2701 MIPS_DIRECT_MAPPABLE(b_phys)) {
2702 pmap_flush_pvcache(a_m);
2703 mips_dcache_wbinv_range_index(
2704 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE);
2705 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) +
2707 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) +
2709 bcopy(a_cp, b_cp, cnt);
2710 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2712 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys);
2713 b_cp = (char *)a_cp + PAGE_SIZE;
2714 a_cp += a_pg_offset;
2715 b_cp += b_pg_offset;
2716 bcopy(a_cp, b_cp, cnt);
2717 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2727 pmap_quick_enter_page(vm_page_t m)
2729 #if defined(__mips_n64)
2730 return MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
2734 pt_entry_t *pte, npte;
2736 pa = VM_PAGE_TO_PHYS(m);
2738 if (MIPS_DIRECT_MAPPABLE(pa)) {
2739 if (pmap_page_get_memattr(m) != VM_MEMATTR_WRITE_BACK)
2740 return (MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
2742 return (MIPS_PHYS_TO_DIRECT(pa));
2745 qaddr = PCPU_GET(qmap_addr);
2746 pte = PCPU_GET(qmap_ptep);
2748 KASSERT(*pte == PTE_G, ("pmap_quick_enter_page: PTE busy"));
2750 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G;
2751 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2759 pmap_quick_remove_page(vm_offset_t addr)
2761 mips_dcache_wbinv_range(addr, PAGE_SIZE);
2763 #if !defined(__mips_n64)
2766 if (addr >= MIPS_KSEG0_START && addr < MIPS_KSEG0_END)
2769 pte = PCPU_GET(qmap_ptep);
2771 KASSERT(*pte != PTE_G,
2772 ("pmap_quick_remove_page: PTE not in use"));
2773 KASSERT(PCPU_GET(qmap_addr) == addr,
2774 ("pmap_quick_remove_page: invalid address"));
2777 tlb_invalidate_address(kernel_pmap, addr);
2783 * Returns true if the pmap's pv is one of the first
2784 * 16 pvs linked to from this page. This count may
2785 * be changed upwards or downwards in the future; it
2786 * is only necessary that true be returned for a small
2787 * subset of pmaps for proper page aging.
2790 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2796 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2797 ("pmap_page_exists_quick: page %p is not managed", m));
2799 rw_wlock(&pvh_global_lock);
2800 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2801 if (PV_PMAP(pv) == pmap) {
2809 rw_wunlock(&pvh_global_lock);
2814 * Remove all pages from specified address space
2815 * this aids process exit speeds. Also, this code
2816 * is special cased for current process only, but
2817 * can have the more generic (and slightly slower)
2818 * mode enabled. This is much faster than pmap_remove
2819 * in the case of running down an entire address space.
2822 pmap_remove_pages(pmap_t pmap)
2825 pt_entry_t *pte, tpte;
2828 struct pv_chunk *pc, *npc;
2829 u_long inuse, bitmask;
2830 int allfree, bit, field, idx;
2832 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
2833 printf("warning: pmap_remove_pages called with non-current pmap\n");
2836 rw_wlock(&pvh_global_lock);
2838 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2840 for (field = 0; field < _NPCM; field++) {
2841 inuse = ~pc->pc_map[field] & pc_freemask[field];
2842 while (inuse != 0) {
2843 bit = ffsl(inuse) - 1;
2844 bitmask = 1UL << bit;
2845 idx = field * sizeof(inuse) * NBBY + bit;
2846 pv = &pc->pc_pventry[idx];
2849 pde = pmap_pde(pmap, pv->pv_va);
2850 KASSERT(pde != NULL && *pde != 0,
2851 ("pmap_remove_pages: pde"));
2852 pte = pmap_pde_to_pte(pde, pv->pv_va);
2853 if (!pte_test(pte, PTE_V))
2854 panic("pmap_remove_pages: bad pte");
2858 * We cannot remove wired pages from a process' mapping at this time
2860 if (pte_test(&tpte, PTE_W)) {
2864 *pte = is_kernel_pmap(pmap) ? PTE_G : 0;
2866 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte));
2868 ("pmap_remove_pages: bad tpte %#jx",
2872 * Update the vm_page_t clean and reference bits.
2874 if (pte_test(&tpte, PTE_D))
2878 PV_STAT(pv_entry_frees++);
2879 PV_STAT(pv_entry_spare++);
2881 pc->pc_map[field] |= bitmask;
2882 pmap->pm_stats.resident_count--;
2883 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2884 if (TAILQ_EMPTY(&m->md.pv_list))
2885 vm_page_aflag_clear(m, PGA_WRITEABLE);
2888 * For simplicity, unconditionally call
2889 * pmap_invalidate_all(), below.
2891 (void)pmap_unuse_pt(pmap, pv->pv_va, *pde);
2895 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2899 pmap_invalidate_all(pmap);
2901 rw_wunlock(&pvh_global_lock);
2905 * pmap_testbit tests bits in pte's
2908 pmap_testbit(vm_page_t m, int bit)
2913 boolean_t rv = FALSE;
2915 if (m->oflags & VPO_UNMANAGED)
2918 rw_assert(&pvh_global_lock, RA_WLOCKED);
2919 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2922 pte = pmap_pte(pmap, pv->pv_va);
2923 rv = pte_test(pte, bit);
2932 * pmap_page_wired_mappings:
2934 * Return the number of managed mappings to the given physical page
2938 pmap_page_wired_mappings(vm_page_t m)
2946 if ((m->oflags & VPO_UNMANAGED) != 0)
2948 rw_wlock(&pvh_global_lock);
2949 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2952 pte = pmap_pte(pmap, pv->pv_va);
2953 if (pte_test(pte, PTE_W))
2957 rw_wunlock(&pvh_global_lock);
2962 * Clear the write and modified bits in each of the given page's mappings.
2965 pmap_remove_write(vm_page_t m)
2968 pt_entry_t pbits, *pte;
2971 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2972 ("pmap_remove_write: page %p is not managed", m));
2973 vm_page_assert_busied(m);
2975 if (!pmap_page_is_write_mapped(m))
2977 rw_wlock(&pvh_global_lock);
2978 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2981 pte = pmap_pte(pmap, pv->pv_va);
2982 KASSERT(pte != NULL && pte_test(pte, PTE_V),
2983 ("page on pv_list has no pte"));
2985 if (pte_test(&pbits, PTE_D)) {
2986 pte_clear(&pbits, PTE_D);
2989 pte_set(&pbits, PTE_RO);
2990 if (pbits != *pte) {
2992 pmap_update_page(pmap, pv->pv_va, pbits);
2996 vm_page_aflag_clear(m, PGA_WRITEABLE);
2997 rw_wunlock(&pvh_global_lock);
3001 * pmap_ts_referenced:
3003 * Return the count of reference bits for a page, clearing all of them.
3006 pmap_ts_referenced(vm_page_t m)
3009 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3010 ("pmap_ts_referenced: page %p is not managed", m));
3011 if (m->md.pv_flags & PV_TABLE_REF) {
3012 rw_wlock(&pvh_global_lock);
3013 m->md.pv_flags &= ~PV_TABLE_REF;
3014 rw_wunlock(&pvh_global_lock);
3023 * Return whether or not the specified physical page was modified
3024 * in any physical maps.
3027 pmap_is_modified(vm_page_t m)
3031 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3032 ("pmap_is_modified: page %p is not managed", m));
3035 * If the page is not busied then this check is racy.
3037 if (!pmap_page_is_write_mapped(m))
3040 rw_wlock(&pvh_global_lock);
3041 rv = pmap_testbit(m, PTE_D);
3042 rw_wunlock(&pvh_global_lock);
3049 * pmap_is_prefaultable:
3051 * Return whether or not the specified virtual address is elgible
3055 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3063 pde = pmap_pde(pmap, addr);
3064 if (pde != NULL && *pde != 0) {
3065 pte = pmap_pde_to_pte(pde, addr);
3073 * Apply the given advice to the specified range of addresses within the
3074 * given pmap. Depending on the advice, clear the referenced and/or
3075 * modified flags in each mapping and set the mapped page's dirty field.
3078 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3080 pd_entry_t *pde, *pdpe;
3082 vm_offset_t va, va_next;
3086 if (advice != MADV_DONTNEED && advice != MADV_FREE)
3088 rw_wlock(&pvh_global_lock);
3090 for (; sva < eva; sva = va_next) {
3091 pdpe = pmap_segmap(pmap, sva);
3094 va_next = (sva + NBSEG) & ~SEGMASK;
3100 va_next = (sva + NBPDR) & ~PDRMASK;
3104 pde = pmap_pdpe_to_pde(pdpe, sva);
3109 * Limit our scan to either the end of the va represented
3110 * by the current page table page, or to the end of the
3111 * range being write protected.
3117 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3119 if (!pte_test(pte, PTE_MANAGED | PTE_V)) {
3120 if (va != va_next) {
3121 pmap_invalidate_range(pmap, va, sva);
3126 pa = TLBLO_PTE_TO_PA(*pte);
3127 m = PHYS_TO_VM_PAGE(pa);
3128 m->md.pv_flags &= ~PV_TABLE_REF;
3129 if (pte_test(pte, PTE_D)) {
3130 if (advice == MADV_DONTNEED) {
3132 * Future calls to pmap_is_modified()
3133 * can be avoided by making the page
3138 pte_clear(pte, PTE_D);
3144 * Unless PTE_D is set, any TLB entries
3145 * mapping "sva" don't allow write access, so
3146 * they needn't be invalidated.
3148 if (va != va_next) {
3149 pmap_invalidate_range(pmap, va, sva);
3155 pmap_invalidate_range(pmap, va, sva);
3157 rw_wunlock(&pvh_global_lock);
3162 * Clear the modify bits on the specified physical page.
3165 pmap_clear_modify(vm_page_t m)
3171 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3172 ("pmap_clear_modify: page %p is not managed", m));
3173 vm_page_assert_busied(m);
3175 if (!pmap_page_is_write_mapped(m))
3177 rw_wlock(&pvh_global_lock);
3178 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3181 pte = pmap_pte(pmap, pv->pv_va);
3182 if (pte_test(pte, PTE_D)) {
3183 pte_clear(pte, PTE_D);
3184 pmap_update_page(pmap, pv->pv_va, *pte);
3188 rw_wunlock(&pvh_global_lock);
3192 * pmap_is_referenced:
3194 * Return whether or not the specified physical page was referenced
3195 * in any physical maps.
3198 pmap_is_referenced(vm_page_t m)
3201 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3202 ("pmap_is_referenced: page %p is not managed", m));
3203 return ((m->md.pv_flags & PV_TABLE_REF) != 0);
3207 * Miscellaneous support routines follow
3211 * Map a set of physical memory pages into the kernel virtual
3212 * address space. Return a pointer to where it is mapped. This
3213 * routine is intended to be used for mapping device memory,
3216 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit.
3219 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3221 vm_offset_t va, tmpva, offset;
3224 * KSEG1 maps only first 512M of phys address space. For
3225 * pa > 0x20000000 we should make proper mapping * using pmap_kenter.
3227 if (MIPS_DIRECT_MAPPABLE(pa + size - 1) && ma == VM_MEMATTR_UNCACHEABLE)
3228 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
3230 offset = pa & PAGE_MASK;
3231 size = roundup(size + offset, PAGE_SIZE);
3233 va = kva_alloc(size);
3235 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3236 pa = trunc_page(pa);
3237 for (tmpva = va; size > 0;) {
3238 pmap_kenter_attr(tmpva, pa, ma);
3245 return ((void *)(va + offset));
3249 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3251 return pmap_mapdev_attr(pa, size, VM_MEMATTR_UNCACHEABLE);
3255 pmap_unmapdev(vm_offset_t va, vm_size_t size)
3258 vm_offset_t base, offset;
3260 /* If the address is within KSEG1 then there is nothing to do */
3261 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
3264 base = trunc_page(va);
3265 offset = va & PAGE_MASK;
3266 size = roundup(size + offset, PAGE_SIZE);
3267 kva_free(base, size);
3272 * Perform the pmap work for mincore(2). If the page is not both referenced and
3273 * modified by this pmap, returns its physical address so that the caller can
3274 * find other mappings.
3277 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
3279 pt_entry_t *ptep, pte;
3285 ptep = pmap_pte(pmap, addr);
3286 pte = (ptep != NULL) ? *ptep : 0;
3287 if (!pte_test(&pte, PTE_V)) {
3291 val = MINCORE_INCORE;
3292 if (pte_test(&pte, PTE_D))
3293 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3294 pa = TLBLO_PTE_TO_PA(pte);
3295 if (pte_test(&pte, PTE_MANAGED)) {
3297 * This may falsely report the given address as
3298 * MINCORE_REFERENCED. Unfortunately, due to the lack of
3299 * per-PTE reference information, it is impossible to
3300 * determine if the address is MINCORE_REFERENCED.
3302 m = PHYS_TO_VM_PAGE(pa);
3303 if ((m->a.flags & PGA_REFERENCED) != 0)
3304 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3306 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3307 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
3308 pte_test(&pte, PTE_MANAGED)) {
3316 pmap_activate(struct thread *td)
3318 pmap_t pmap, oldpmap;
3319 struct proc *p = td->td_proc;
3324 pmap = vmspace_pmap(p->p_vmspace);
3325 oldpmap = PCPU_GET(curpmap);
3326 cpuid = PCPU_GET(cpuid);
3329 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
3330 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
3331 pmap_asid_alloc(pmap);
3332 if (td == curthread) {
3333 PCPU_SET(segbase, pmap->pm_segtab);
3334 mips_wr_entryhi(pmap->pm_asid[cpuid].asid);
3337 PCPU_SET(curpmap, pmap);
3342 pmap_sync_icache_one(void *arg __unused)
3345 mips_icache_sync_all();
3346 mips_dcache_wbinv_all();
3350 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3353 smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
3357 * Increase the starting virtual address of the given mapping if a
3358 * different alignment might result in more superpage mappings.
3361 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3362 vm_offset_t *addr, vm_size_t size)
3364 vm_offset_t superpage_offset;
3368 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
3369 offset += ptoa(object->pg_color);
3370 superpage_offset = offset & PDRMASK;
3371 if (size - ((PDRSIZE - superpage_offset) & PDRMASK) < PDRSIZE ||
3372 (*addr & PDRMASK) == superpage_offset)
3374 if ((*addr & PDRMASK) < superpage_offset)
3375 *addr = (*addr & ~PDRMASK) + superpage_offset;
3377 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
3381 DB_SHOW_COMMAND(ptable, ddb_pid_dump)
3384 struct thread *td = NULL;
3391 td = db_lookup_thread(addr, true);
3393 db_printf("Invalid pid or tid");
3397 if (p->p_vmspace == NULL) {
3398 db_printf("No vmspace for process");
3401 pmap = vmspace_pmap(p->p_vmspace);
3405 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n",
3406 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid,
3407 pmap->pm_asid[0].gen);
3408 for (i = 0; i < NPDEPG; i++) {
3413 pdpe = (pd_entry_t *)pmap->pm_segtab[i];
3416 db_printf("[%4d] %p\n", i, pdpe);
3418 for (j = 0; j < NPDEPG; j++) {
3419 pde = (pt_entry_t *)pdpe[j];
3422 db_printf("\t[%4d] %p\n", j, pde);
3426 pde = (pt_entry_t *)pdpe;
3428 for (k = 0; k < NPTEPG; k++) {
3430 if (pte == 0 || !pte_test(&pte, PTE_V))
3432 pa = TLBLO_PTE_TO_PA(pte);
3433 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT);
3434 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n",
3435 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa);
3443 * Allocate TLB address space tag (called ASID or TLBPID) and return it.
3444 * It takes almost as much or more time to search the TLB for a
3445 * specific ASID and flush those entries as it does to flush the entire TLB.
3446 * Therefore, when we allocate a new ASID, we just take the next number. When
3447 * we run out of numbers, we flush the TLB, increment the generation count
3448 * and start over. ASID zero is reserved for kernel use.
3451 pmap_asid_alloc(pmap)
3454 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED &&
3455 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
3457 if (PCPU_GET(next_asid) == pmap_max_asid) {
3458 tlb_invalidate_all_user(NULL);
3459 PCPU_SET(asid_generation,
3460 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
3461 if (PCPU_GET(asid_generation) == 0) {
3462 PCPU_SET(asid_generation, 1);
3464 PCPU_SET(next_asid, 1); /* 0 means invalid */
3466 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid);
3467 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation);
3468 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1);
3473 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot)
3477 if (!(prot & VM_PROT_WRITE))
3478 rw = PTE_V | PTE_RO;
3479 else if ((m->oflags & VPO_UNMANAGED) == 0) {
3480 if ((access & VM_PROT_WRITE) != 0)
3485 /* Needn't emulate a modified bit for unmanaged pages. */
3491 * pmap_emulate_modified : do dirty bit emulation
3493 * On SMP, update just the local TLB, other CPUs will update their
3494 * TLBs from PTE lazily, if they get the exception.
3495 * Returns 0 in case of sucess, 1 if the page is read only and we
3499 pmap_emulate_modified(pmap_t pmap, vm_offset_t va)
3504 pte = pmap_pte(pmap, va);
3507 * It is possible that some other CPU or thread changed the pmap while
3508 * we weren't looking; in the SMP case, this is readily apparent, but
3509 * it can even happen in the UP case, because we may have been blocked
3510 * on PMAP_LOCK(pmap) above while someone changed this out from
3516 * This PTE's PTP (or one of its ancestors) has been reclaimed;
3517 * trigger a full fault to reconstruct it via pmap_enter.
3523 if (!pte_test(pte, PTE_V)) {
3525 * This PTE is no longer valid; the other thread or other
3526 * processor must have arranged for our TLB to no longer
3527 * have this entry, possibly by IPI, so no tlb_update is
3528 * required. Fall out of the fast path and go take a
3529 * general fault before retrying the instruction (or taking
3536 if (pte_test(pte, PTE_D)) {
3538 * This PTE is valid and has the PTE_D bit asserted; since
3539 * this is an increase in permission, we may have been expected
3540 * to update the TLB lazily. Do so here and return, on the
3541 * fast path, to retry the instruction.
3543 tlb_update(pmap, va, *pte);
3548 if (pte_test(pte, PTE_RO)) {
3550 * This PTE is valid, not dirty, and read-only. Go take a
3551 * full fault (most likely to upgrade this part of the address
3552 * space to writeable).
3558 if (!pte_test(pte, PTE_MANAGED))
3559 panic("pmap_emulate_modified: unmanaged page");
3562 * PTE is valid, managed, not dirty, and not read-only. Set PTE_D
3563 * and eagerly update the local TLB, returning on the fast path.
3566 pte_set(pte, PTE_D);
3567 tlb_update(pmap, va, *pte);
3574 * Routine: pmap_kextract
3576 * Extract the physical page address associated
3580 pmap_kextract(vm_offset_t va)
3585 * First, the direct-mapped regions.
3587 #if defined(__mips_n64)
3588 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
3589 return (MIPS_XKPHYS_TO_PHYS(va));
3591 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
3592 return (MIPS_KSEG0_TO_PHYS(va));
3594 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
3595 return (MIPS_KSEG1_TO_PHYS(va));
3598 * User virtual addresses.
3600 if (va < VM_MAXUSER_ADDRESS) {
3603 if (curproc && curproc->p_vmspace) {
3604 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
3606 return (TLBLO_PTE_TO_PA(*ptep) |
3614 * Should be kernel virtual here, otherwise fail
3616 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
3617 #if defined(__mips_n64)
3618 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
3627 /* Is the kernel pmap initialized? */
3628 if (!CPU_EMPTY(&kernel_pmap->pm_active)) {
3629 /* It's inside the virtual address range */
3630 ptep = pmap_pte(kernel_pmap, va);
3632 return (TLBLO_PTE_TO_PA(*ptep) |
3639 panic("%s for unknown address space %p.", __func__, (void *)va);
3644 pmap_flush_pvcache(vm_page_t m)
3649 for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
3650 pv = TAILQ_NEXT(pv, pv_list)) {
3651 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
3657 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3661 * It appears that this function can only be called before any mappings
3662 * for the page are established. If this ever changes, this code will
3663 * need to walk the pv_list and make each of the existing mappings
3664 * uncacheable, being careful to sync caches and PTEs (and maybe
3665 * invalidate TLB?) for any current mapping it modifies.
3667 if (TAILQ_FIRST(&m->md.pv_list) != NULL)
3668 panic("Can't change memattr on page with existing mappings");
3670 /* Clean memattr portion of pv_flags */
3671 m->md.pv_flags &= ~PV_MEMATTR_MASK;
3672 m->md.pv_flags |= (ma << PV_MEMATTR_SHIFT) & PV_MEMATTR_MASK;
3675 static __inline void
3676 pmap_pte_attr(pt_entry_t *pte, vm_memattr_t ma)
3680 npte = *(u_int *)pte;
3681 npte &= ~PTE_C_MASK;
3687 pmap_change_attr(vm_offset_t sva, vm_size_t size, vm_memattr_t ma)
3689 pd_entry_t *pde, *pdpe;
3691 vm_offset_t ova, eva, va, va_next;
3702 for (; sva < eva; sva = va_next) {
3703 pdpe = pmap_segmap(pmap, sva);
3706 va_next = (sva + NBSEG) & ~SEGMASK;
3712 va_next = (sva + NBPDR) & ~PDRMASK;
3716 pde = pmap_pdpe_to_pde(pdpe, sva);
3721 * Limit our scan to either the end of the va represented
3722 * by the current page table page, or to the end of the
3723 * range being removed.
3729 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3731 if (!pte_test(pte, PTE_V) || pte_cache_bits(pte) == ma) {
3732 if (va != va_next) {
3733 pmap_invalidate_range(pmap, va, sva);
3741 pmap_pte_attr(pte, ma);
3744 pmap_invalidate_range(pmap, va, sva);
3748 /* Flush caches to be in the safe side */
3749 mips_dcache_wbinv_range(ova, size);
3754 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
3758 case VM_MEMATTR_UNCACHEABLE:
3759 case VM_MEMATTR_WRITE_BACK:
3761 case VM_MEMATTR_WRITE_COMBINING: