2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps
41 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish
45 * Manages physical address maps.
47 * Since the information managed by this module is
48 * also stored by the logical address mapping module,
49 * this module may throw away valid virtual-to-physical
50 * mappings at almost any time. However, invalidations
51 * of virtual-to-physical mappings must be done as
54 * In order to cope with hardware architectures which
55 * make virtual-to-physical map invalidates expensive,
56 * this module may delay invalidate or reduced protection
57 * operations until such time as they are actually
58 * necessary. This module is given full information as
59 * to which processors are currently using which maps,
60 * and to when physical maps must be made correct.
63 #include <sys/cdefs.h>
64 __FBSDID("$FreeBSD$");
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/kernel.h>
74 #include <sys/msgbuf.h>
75 #include <sys/mutex.h>
78 #include <sys/rwlock.h>
79 #include <sys/sched.h>
81 #include <sys/sysctl.h>
82 #include <sys/vmmeter.h>
89 #include <vm/vm_param.h>
90 #include <vm/vm_kern.h>
91 #include <vm/vm_page.h>
92 #include <vm/vm_phys.h>
93 #include <vm/vm_map.h>
94 #include <vm/vm_object.h>
95 #include <vm/vm_extern.h>
96 #include <vm/vm_pageout.h>
97 #include <vm/vm_pager.h>
100 #include <machine/cache.h>
101 #include <machine/md_var.h>
102 #include <machine/tlb.h>
106 #if !defined(DIAGNOSTIC)
107 #define PMAP_INLINE __inline
113 #define PV_STAT(x) do { x ; } while (0)
115 #define PV_STAT(x) do { } while (0)
119 * Get PDEs and PTEs for user/kernel address space
121 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
122 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1))
123 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1))
124 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT)
127 #define NUPDE (NPDEPG * NPDEPG)
128 #define NUSERPGTBLS (NUPDE + NPDEPG)
130 #define NUPDE (NPDEPG)
131 #define NUSERPGTBLS (NUPDE)
134 #define is_kernel_pmap(x) ((x) == kernel_pmap)
136 struct pmap kernel_pmap_store;
137 pd_entry_t *kernel_segmap;
139 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
140 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
142 static int need_local_mappings;
145 unsigned pmap_max_asid; /* max ASID supported by the system */
147 #define PMAP_ASID_RESERVED 0
149 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
151 static void pmap_asid_alloc(pmap_t pmap);
153 static struct rwlock_padalign pvh_global_lock;
156 * Data for the pv entry allocation mechanism
158 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
159 static int pv_entry_count;
161 static void free_pv_chunk(struct pv_chunk *pc);
162 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
163 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
164 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
165 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
166 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
168 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req);
169 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
170 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
171 static void pmap_grow_direct_page(int req);
172 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
174 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
175 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
176 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
177 vm_offset_t va, vm_page_t m);
178 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
179 static void pmap_invalidate_all(pmap_t pmap);
180 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
181 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m);
183 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
184 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags);
185 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t);
186 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot);
188 static void pmap_invalidate_page_action(void *arg);
189 static void pmap_invalidate_range_action(void *arg);
190 static void pmap_update_page_action(void *arg);
194 static vm_offset_t crashdumpva;
197 * These functions are for high memory (memory above 512Meg in 32 bit) support.
198 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to
199 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc.
201 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To
202 * access a highmem physical address on a CPU, we map the physical address to
203 * the reserved virtual address for the CPU in the kernel pagetable.
207 pmap_init_reserved_pages(void)
213 if (need_local_mappings == 0)
219 * Skip if the mapping has already been initialized,
220 * i.e. this is the BSP.
222 if (pc->pc_cmap1_addr != 0)
224 pages = kva_alloc(PAGE_SIZE * 3);
226 panic("%s: unable to allocate KVA", __func__);
227 pc->pc_cmap1_ptep = pmap_pte(kernel_pmap, pages);
228 pc->pc_cmap2_ptep = pmap_pte(kernel_pmap, pages + PAGE_SIZE);
230 pmap_pte(kernel_pmap, pages + (PAGE_SIZE * 2));
231 pc->pc_cmap1_addr = pages;
232 pc->pc_cmap2_addr = pages + PAGE_SIZE;
233 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
236 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
239 pmap_alloc_lmem_map(void)
241 PCPU_SET(cmap1_addr, virtual_avail);
242 PCPU_SET(cmap2_addr, virtual_avail + PAGE_SIZE);
243 PCPU_SET(cmap1_ptep, pmap_pte(kernel_pmap, virtual_avail));
244 PCPU_SET(cmap2_ptep, pmap_pte(kernel_pmap, virtual_avail + PAGE_SIZE));
245 PCPU_SET(qmap_addr, virtual_avail + (2 * PAGE_SIZE));
246 PCPU_SET(qmap_ptep, pmap_pte(kernel_pmap, virtual_avail + (2 * PAGE_SIZE)));
247 crashdumpva = virtual_avail + (3 * PAGE_SIZE);
248 virtual_avail += PAGE_SIZE * 4;
251 static __inline vm_offset_t
252 pmap_lmem_map1(vm_paddr_t phys)
255 *PCPU_GET(cmap1_ptep) =
256 TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
257 return (PCPU_GET(cmap1_addr));
260 static __inline vm_offset_t
261 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
264 *PCPU_GET(cmap1_ptep) =
265 TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
266 *PCPU_GET(cmap2_ptep) =
267 TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
268 return (PCPU_GET(cmap1_addr));
272 pmap_lmem_unmap(void)
274 *PCPU_GET(cmap1_ptep) = PTE_G;
275 tlb_invalidate_address(kernel_pmap, PCPU_GET(cmap1_addr));
276 if (*PCPU_GET(cmap2_ptep) != PTE_G) {
277 *PCPU_GET(cmap2_ptep) = PTE_G;
278 tlb_invalidate_address(kernel_pmap, PCPU_GET(cmap2_addr));
283 #else /* __mips_n64 */
286 pmap_alloc_lmem_map(void)
290 static __inline vm_offset_t
291 pmap_lmem_map1(vm_paddr_t phys)
297 static __inline vm_offset_t
298 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
304 static __inline vm_offset_t
305 pmap_lmem_unmap(void)
310 #endif /* !__mips_n64 */
313 pmap_pte_cache_bits(vm_paddr_t pa, vm_page_t m)
317 ma = pmap_page_get_memattr(m);
318 if (ma == VM_MEMATTR_WRITE_BACK && !is_cacheable_mem(pa))
319 ma = VM_MEMATTR_UNCACHEABLE;
322 #define PMAP_PTE_SET_CACHE_BITS(pte, pa, m) { \
323 pte &= ~PTE_C_MASK; \
324 pte |= pmap_pte_cache_bits(pa, m); \
328 * Page table entry lookup routines.
330 static __inline pd_entry_t *
331 pmap_segmap(pmap_t pmap, vm_offset_t va)
334 return (&pmap->pm_segtab[pmap_seg_index(va)]);
338 static __inline pd_entry_t *
339 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
343 pde = (pd_entry_t *)*pdpe;
344 return (&pde[pmap_pde_index(va)]);
347 static __inline pd_entry_t *
348 pmap_pde(pmap_t pmap, vm_offset_t va)
352 pdpe = pmap_segmap(pmap, va);
356 return (pmap_pdpe_to_pde(pdpe, va));
359 static __inline pd_entry_t *
360 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
367 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va)
370 return (pmap_segmap(pmap, va));
374 static __inline pt_entry_t *
375 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
379 pte = (pt_entry_t *)*pde;
380 return (&pte[pmap_pte_index(va)]);
384 pmap_pte(pmap_t pmap, vm_offset_t va)
388 pde = pmap_pde(pmap, va);
389 if (pde == NULL || *pde == NULL)
392 return (pmap_pde_to_pte(pde, va));
396 pmap_steal_memory(vm_size_t size)
398 vm_paddr_t bank_size, pa;
401 size = round_page(size);
402 bank_size = phys_avail[1] - phys_avail[0];
403 while (size > bank_size) {
406 for (i = 0; phys_avail[i + 2]; i += 2) {
407 phys_avail[i] = phys_avail[i + 2];
408 phys_avail[i + 1] = phys_avail[i + 3];
411 phys_avail[i + 1] = 0;
413 panic("pmap_steal_memory: out of memory");
414 bank_size = phys_avail[1] - phys_avail[0];
418 phys_avail[0] += size;
419 if (MIPS_DIRECT_MAPPABLE(pa) == 0)
420 panic("Out of memory below 512Meg?");
421 va = MIPS_PHYS_TO_DIRECT(pa);
422 bzero((caddr_t)va, size);
427 * Bootstrap the system enough to run with virtual memory. This
428 * assumes that the phys_avail array has been initialized.
431 pmap_create_kernel_pagetable(void)
443 * Allocate segment table for the kernel
445 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE);
448 * Allocate second level page tables for the kernel
451 npde = howmany(NKPT, NPDEPG);
452 pdaddr = pmap_steal_memory(PAGE_SIZE * npde);
455 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt);
458 * The R[4-7]?00 stores only one copy of the Global bit in the
459 * translation lookaside buffer for each 2 page entry. Thus invalid
460 * entrys must have the Global bit set so when Entry LO and Entry HI
461 * G bits are anded together they will produce a global bit to store
464 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++)
468 for (i = 0, npt = nkpt; npt > 0; i++) {
469 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE);
470 pde = (pd_entry_t *)kernel_segmap[i];
472 for (j = 0; j < NPDEPG && npt > 0; j++, npt--)
473 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE);
476 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++)
477 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE));
480 PMAP_LOCK_INIT(kernel_pmap);
481 kernel_pmap->pm_segtab = kernel_segmap;
482 CPU_FILL(&kernel_pmap->pm_active);
483 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
484 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
485 kernel_pmap->pm_asid[0].gen = 0;
486 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE;
496 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
498 * Keep the memory aligned on page boundary.
500 phys_avail[i] = round_page(phys_avail[i]);
501 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
505 if (phys_avail[i - 2] > phys_avail[i]) {
508 ptemp[0] = phys_avail[i + 0];
509 ptemp[1] = phys_avail[i + 1];
511 phys_avail[i + 0] = phys_avail[i - 2];
512 phys_avail[i + 1] = phys_avail[i - 1];
514 phys_avail[i - 2] = ptemp[0];
515 phys_avail[i - 1] = ptemp[1];
521 * In 32 bit, we may have memory which cannot be mapped directly.
522 * This memory will need temporary mapping before it can be
525 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1))
526 need_local_mappings = 1;
529 * Copy the phys_avail[] array before we start stealing memory from it.
531 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
532 physmem_desc[i] = phys_avail[i];
533 physmem_desc[i + 1] = phys_avail[i + 1];
536 Maxmem = atop(phys_avail[i - 1]);
539 printf("Physical memory chunk(s):\n");
540 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
543 size = phys_avail[i + 1] - phys_avail[i];
544 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n",
545 (uintmax_t) phys_avail[i],
546 (uintmax_t) phys_avail[i + 1] - 1,
547 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE);
549 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem));
552 * Steal the message buffer from the beginning of memory.
554 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize);
555 msgbufinit(msgbufp, msgbufsize);
558 * Steal thread0 kstack.
560 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
562 virtual_avail = VM_MIN_KERNEL_ADDRESS;
563 virtual_end = VM_MAX_KERNEL_ADDRESS;
567 * Steal some virtual address space to map the pcpu area.
569 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2);
570 pcpup = (struct pcpu *)virtual_avail;
571 virtual_avail += PAGE_SIZE * 2;
574 * Initialize the wired TLB entry mapping the pcpu region for
575 * the BSP at 'pcpup'. Up until this point we were operating
576 * with the 'pcpup' for the BSP pointing to a virtual address
577 * in KSEG0 so there was no need for a TLB mapping.
579 mips_pcpu_tlb_init(PCPU_ADDR(0));
582 printf("pcpu is available at virtual address %p.\n", pcpup);
585 pmap_create_kernel_pagetable();
586 if (need_local_mappings)
587 pmap_alloc_lmem_map();
588 pmap_max_asid = VMNUM_PIDS;
593 * Initialize the global pv list lock.
595 rw_init(&pvh_global_lock, "pmap pv global");
599 * Initialize a vm_page's machine-dependent fields.
602 pmap_page_init(vm_page_t m)
605 TAILQ_INIT(&m->md.pv_list);
606 m->md.pv_flags = VM_MEMATTR_DEFAULT << PV_MEMATTR_SHIFT;
610 * Initialize the pmap module.
611 * Called by vm_init, to initialize any structures that the pmap
612 * system needs to map virtual memory.
619 /***************************************************
620 * Low level helper routines.....
621 ***************************************************/
625 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
627 int cpuid, cpu, self;
628 cpuset_t active_cpus;
631 if (is_kernel_pmap(pmap)) {
632 smp_rendezvous(NULL, fn, NULL, arg);
635 /* Force ASID update on inactive CPUs */
637 if (!CPU_ISSET(cpu, &pmap->pm_active))
638 pmap->pm_asid[cpu].gen = 0;
640 cpuid = PCPU_GET(cpuid);
642 * XXX: barrier/locking for active?
644 * Take a snapshot of active here, any further changes are ignored.
645 * tlb update/invalidate should be harmless on inactive CPUs
647 active_cpus = pmap->pm_active;
648 self = CPU_ISSET(cpuid, &active_cpus);
649 CPU_CLR(cpuid, &active_cpus);
650 /* Optimize for the case where this cpu is the only active one */
651 if (CPU_EMPTY(&active_cpus)) {
656 CPU_SET(cpuid, &active_cpus);
657 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg);
664 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
668 if (is_kernel_pmap(pmap)) {
672 cpuid = PCPU_GET(cpuid);
673 if (!CPU_ISSET(cpuid, &pmap->pm_active))
674 pmap->pm_asid[cpuid].gen = 0;
681 pmap_invalidate_all(pmap_t pmap)
684 pmap_call_on_active_cpus(pmap,
685 (void (*)(void *))tlb_invalidate_all_user, pmap);
688 struct pmap_invalidate_page_arg {
694 pmap_invalidate_page_action(void *arg)
696 struct pmap_invalidate_page_arg *p = arg;
698 tlb_invalidate_address(p->pmap, p->va);
702 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
704 struct pmap_invalidate_page_arg arg;
708 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg);
711 struct pmap_invalidate_range_arg {
718 pmap_invalidate_range_action(void *arg)
720 struct pmap_invalidate_range_arg *p = arg;
722 tlb_invalidate_range(p->pmap, p->sva, p->eva);
726 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
728 struct pmap_invalidate_range_arg arg;
733 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg);
736 struct pmap_update_page_arg {
743 pmap_update_page_action(void *arg)
745 struct pmap_update_page_arg *p = arg;
747 tlb_update(p->pmap, p->va, p->pte);
751 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte)
753 struct pmap_update_page_arg arg;
758 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg);
762 * Routine: pmap_extract
764 * Extract the physical page address associated
765 * with the given map/virtual_address pair.
768 pmap_extract(pmap_t pmap, vm_offset_t va)
771 vm_offset_t retval = 0;
774 pte = pmap_pte(pmap, va);
776 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK);
783 * Routine: pmap_extract_and_hold
785 * Atomically extract and hold the physical page
786 * with the given pmap and virtual address pair
787 * if that mapping permits the given protection.
790 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
792 pt_entry_t pte, *ptep;
798 ptep = pmap_pte(pmap, va);
801 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) ||
802 (prot & VM_PROT_WRITE) == 0)) {
803 pa = TLBLO_PTE_TO_PA(pte);
804 m = PHYS_TO_VM_PAGE(pa);
805 if (!vm_page_wire_mapped(m))
813 /***************************************************
814 * Low level mapping routines.....
815 ***************************************************/
818 * add a wired page to the kva
821 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
824 pt_entry_t opte, npte;
827 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
830 pte = pmap_pte(kernel_pmap, va);
832 npte = TLBLO_PA_TO_PFN(pa) | PTE_C(ma) | PTE_D | PTE_V | PTE_G;
834 if (pte_test(&opte, PTE_V) && opte != npte)
835 pmap_update_page(kernel_pmap, va, npte);
839 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
842 KASSERT(is_cacheable_mem(pa),
843 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa));
845 pmap_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
849 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
852 KASSERT((size & PAGE_MASK) == 0,
853 ("%s: device mapping not page-sized", __func__));
855 for (; size > 0; size -= PAGE_SIZE) {
857 * XXXCEM: this is somewhat inefficient on SMP systems in that
858 * every single page is individually TLB-invalidated via
859 * rendezvous (pmap_update_page()), instead of invalidating the
860 * entire range via a single rendezvous.
862 pmap_kenter_attr(va, pa, VM_MEMATTR_UNCACHEABLE);
869 pmap_kremove_device(vm_offset_t va, vm_size_t size)
872 KASSERT((size & PAGE_MASK) == 0,
873 ("%s: device mapping not page-sized", __func__));
876 * XXXCEM: Similar to pmap_kenter_device, this is inefficient on SMP,
877 * in that pages are invalidated individually instead of a single range
880 for (; size > 0; size -= PAGE_SIZE) {
887 * remove a page from the kernel pagetables
889 /* PMAP_INLINE */ void
890 pmap_kremove(vm_offset_t va)
895 * Write back all caches from the page being destroyed
897 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
899 pte = pmap_pte(kernel_pmap, va);
901 pmap_invalidate_page(kernel_pmap, va);
905 * Used to map a range of physical addresses into kernel
906 * virtual address space.
908 * The value passed in '*virt' is a suggested virtual address for
909 * the mapping. Architectures which can support a direct-mapped
910 * physical to virtual region can return the appropriate address
911 * within that region, leaving '*virt' unchanged. Other
912 * architectures should map the pages starting at '*virt' and
913 * update '*virt' with the first usable address after the mapped
916 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
919 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
923 if (MIPS_DIRECT_MAPPABLE(end - 1))
924 return (MIPS_PHYS_TO_DIRECT(start));
927 while (start < end) {
928 pmap_kenter(va, start);
937 * Add a list of wired pages to the kva
938 * this routine is only used for temporary
939 * kernel mappings that do not need to have
940 * page modification or references recorded.
941 * Note that old mappings are simply written
942 * over. The page *must* be wired.
945 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
948 vm_offset_t origva = va;
950 for (i = 0; i < count; i++) {
951 pmap_flush_pvcache(m[i]);
952 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i]));
956 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count);
960 * this routine jerks page mappings from the
961 * kernel -- it is meant only for temporary mappings.
964 pmap_qremove(vm_offset_t va, int count)
971 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count);
974 pte = pmap_pte(kernel_pmap, va);
977 } while (--count > 0);
978 pmap_invalidate_range(kernel_pmap, origva, va);
981 /***************************************************
982 * Page table page management routines.....
983 ***************************************************/
986 * Decrements a page table page's reference count, which is used to record the
987 * number of valid page table entries within the page. If the reference count
988 * drops to zero, then the page table page is unmapped. Returns TRUE if the
989 * page table page was unmapped and FALSE otherwise.
991 static PMAP_INLINE boolean_t
992 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
996 if (m->ref_count == 0) {
997 _pmap_unwire_ptp(pmap, va, m);
1004 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
1007 vm_offset_t sva, eva;
1009 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1011 * unmap the page table page
1014 if (m->pindex < NUPDE) {
1015 pde = pmap_pde(pmap, va);
1016 sva = va & ~PDRMASK;
1019 pde = pmap_segmap(pmap, va);
1020 sva = va & ~SEGMASK;
1024 pde = pmap_pde(pmap, va);
1025 sva = va & ~SEGMASK;
1029 pmap->pm_stats.resident_count--;
1032 if (m->pindex < NUPDE) {
1037 * Recursively decrement next level pagetable refcount.
1038 * Either that shoots down a larger range from TLBs (below)
1039 * or we're to shoot down just the page in question.
1041 pdp = (pd_entry_t *)*pmap_segmap(pmap, va);
1042 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp));
1043 if (!pmap_unwire_ptp(pmap, va, pdpg)) {
1044 pmap_invalidate_range(pmap, sva, eva);
1047 /* Segmap entry shootdown */
1048 pmap_invalidate_range(pmap, sva, eva);
1051 /* Segmap entry shootdown */
1052 pmap_invalidate_range(pmap, sva, eva);
1056 * If the page is finally unwired, simply free it.
1058 vm_page_free_zero(m);
1063 * After removing a page table entry, this routine is used to
1064 * conditionally free the page, and manage the reference count.
1067 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1071 if (va >= VM_MAXUSER_ADDRESS)
1073 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0"));
1074 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde));
1075 return (pmap_unwire_ptp(pmap, va, mpte));
1079 pmap_pinit0(pmap_t pmap)
1083 PMAP_LOCK_INIT(pmap);
1084 pmap->pm_segtab = kernel_segmap;
1085 CPU_ZERO(&pmap->pm_active);
1086 for (i = 0; i < MAXCPU; i++) {
1087 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1088 pmap->pm_asid[i].gen = 0;
1090 PCPU_SET(curpmap, pmap);
1091 TAILQ_INIT(&pmap->pm_pvchunk);
1092 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1096 pmap_grow_direct_page(int req)
1102 if (!vm_page_reclaim_contig(req, 1, 0, MIPS_KSEG0_LARGEST_PHYS,
1109 pmap_alloc_direct_page(unsigned int index, int req)
1113 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED |
1118 if ((m->flags & PG_ZERO) == 0)
1126 * Initialize a preallocated and zeroed pmap structure,
1127 * such as one in a vmspace structure.
1130 pmap_pinit(pmap_t pmap)
1137 * allocate the page directory page
1139 req_class = VM_ALLOC_NORMAL;
1140 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, req_class)) ==
1142 pmap_grow_direct_page(req_class);
1144 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg));
1145 pmap->pm_segtab = (pd_entry_t *)ptdva;
1146 CPU_ZERO(&pmap->pm_active);
1147 for (i = 0; i < MAXCPU; i++) {
1148 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1149 pmap->pm_asid[i].gen = 0;
1151 TAILQ_INIT(&pmap->pm_pvchunk);
1152 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1158 * this routine is called if the page table page is not
1162 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags)
1169 * Find or fabricate a new pagetable page
1171 req_class = VM_ALLOC_NORMAL;
1172 if ((m = pmap_alloc_direct_page(ptepindex, req_class)) == NULL) {
1173 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1175 rw_wunlock(&pvh_global_lock);
1176 pmap_grow_direct_page(req_class);
1177 rw_wlock(&pvh_global_lock);
1182 * Indicate the need to retry. While waiting, the page
1183 * table page may have been allocated.
1189 * Map the pagetable page into the process address space, if it
1190 * isn't already there.
1192 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1195 if (ptepindex >= NUPDE) {
1196 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva;
1198 pd_entry_t *pdep, *pde;
1199 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT);
1200 int pdeindex = ptepindex & (NPDEPG - 1);
1203 pdep = &pmap->pm_segtab[segindex];
1204 if (*pdep == NULL) {
1205 /* recurse for allocating page dir */
1206 if (_pmap_allocpte(pmap, NUPDE + segindex,
1208 /* alloc failed, release current */
1209 vm_page_unwire_noq(m);
1210 vm_page_free_zero(m);
1214 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep));
1217 /* Next level entry */
1218 pde = (pd_entry_t *)*pdep;
1219 pde[pdeindex] = (pd_entry_t)pageva;
1222 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva;
1224 pmap->pm_stats.resident_count++;
1229 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1236 * Calculate pagetable page index
1238 ptepindex = pmap_pde_pindex(va);
1241 * Get the page directory entry
1243 pde = pmap_pde(pmap, va);
1246 * If the page table page is mapped, we just increment the hold
1247 * count, and activate it.
1249 if (pde != NULL && *pde != NULL) {
1250 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde));
1254 * Here if the pte page isn't mapped, or if it has been
1257 m = _pmap_allocpte(pmap, ptepindex, flags);
1258 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1264 /***************************************************
1265 * Pmap allocation/deallocation routines.
1266 ***************************************************/
1269 * Release any resources held by the given physical map.
1270 * Called when a pmap initialized by pmap_pinit is being released.
1271 * Should only be called if the map contains no valid mappings.
1274 pmap_release(pmap_t pmap)
1279 KASSERT(pmap->pm_stats.resident_count == 0,
1280 ("pmap_release: pmap resident count %ld != 0",
1281 pmap->pm_stats.resident_count));
1283 ptdva = (vm_offset_t)pmap->pm_segtab;
1284 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva));
1286 vm_page_unwire_noq(ptdpg);
1287 vm_page_free_zero(ptdpg);
1291 * grow the number of kernel page table entries, if needed
1294 pmap_growkernel(vm_offset_t addr)
1297 pd_entry_t *pde, *pdpe;
1301 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1302 req_class = VM_ALLOC_INTERRUPT;
1303 addr = roundup2(addr, NBSEG);
1304 if (addr - 1 >= vm_map_max(kernel_map))
1305 addr = vm_map_max(kernel_map);
1306 while (kernel_vm_end < addr) {
1307 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end);
1310 /* new intermediate page table entry */
1311 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1313 panic("pmap_growkernel: no memory to grow kernel");
1314 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1315 continue; /* try again */
1318 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
1320 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1321 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1322 kernel_vm_end = vm_map_max(kernel_map);
1329 * This index is bogus, but out of the way
1331 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1333 if (nkpg == NULL && vm_page_reclaim_contig(req_class, 1,
1334 0, MIPS_KSEG0_LARGEST_PHYS, PAGE_SIZE, 0))
1335 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1338 panic("pmap_growkernel: no memory to grow kernel");
1340 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1343 * The R[4-7]?00 stores only one copy of the Global bit in
1344 * the translation lookaside buffer for each 2 page entry.
1345 * Thus invalid entrys must have the Global bit set so when
1346 * Entry LO and Entry HI G bits are anded together they will
1347 * produce a global bit to store in the tlb.
1349 pte = (pt_entry_t *)*pde;
1350 for (i = 0; i < NPTEPG; i++)
1353 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1354 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1355 kernel_vm_end = vm_map_max(kernel_map);
1361 /***************************************************
1362 * page management routines.
1363 ***************************************************/
1365 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1367 CTASSERT(_NPCM == 3);
1368 CTASSERT(_NPCPV == 168);
1370 CTASSERT(_NPCM == 11);
1371 CTASSERT(_NPCPV == 336);
1374 static __inline struct pv_chunk *
1375 pv_to_chunk(pv_entry_t pv)
1378 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1381 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1384 #define PC_FREE0_1 0xfffffffffffffffful
1385 #define PC_FREE2 0x000000fffffffffful
1387 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
1388 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
1391 static const u_long pc_freemask[_NPCM] = {
1393 PC_FREE0_1, PC_FREE0_1, PC_FREE2
1395 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1396 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1397 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1398 PC_FREE0_9, PC_FREE10
1402 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
1403 "VM/pmap parameters");
1405 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1406 "Current number of pv entries");
1409 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1411 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1412 "Current number of pv entry chunks");
1413 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1414 "Current number of pv entry chunks allocated");
1415 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1416 "Current number of pv entry chunks frees");
1417 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1418 "Number of times tried to get a chunk page but failed.");
1420 static long pv_entry_frees, pv_entry_allocs;
1421 static int pv_entry_spare;
1423 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1424 "Current number of pv entry frees");
1425 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1426 "Current number of pv entry allocs");
1427 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1428 "Current number of spare pv entries");
1432 * We are in a serious low memory condition. Resort to
1433 * drastic measures to free some pages so we can allocate
1434 * another pv entry chunk.
1437 pmap_pv_reclaim(pmap_t locked_pmap)
1440 struct pv_chunk *pc;
1443 pt_entry_t *pte, oldpte;
1448 int bit, field, freed, idx;
1450 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1453 TAILQ_INIT(&newtail);
1454 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) {
1455 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1456 if (pmap != pc->pc_pmap) {
1458 pmap_invalidate_all(pmap);
1459 if (pmap != locked_pmap)
1463 /* Avoid deadlock and lock recursion. */
1464 if (pmap > locked_pmap)
1466 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
1468 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1474 * Destroy every non-wired, 4 KB page mapping in the chunk.
1477 for (field = 0; field < _NPCM; field++) {
1478 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1479 inuse != 0; inuse &= ~(1UL << bit)) {
1480 bit = ffsl(inuse) - 1;
1481 idx = field * sizeof(inuse) * NBBY + bit;
1482 pv = &pc->pc_pventry[idx];
1484 pde = pmap_pde(pmap, va);
1485 KASSERT(pde != NULL && *pde != 0,
1486 ("pmap_pv_reclaim: pde"));
1487 pte = pmap_pde_to_pte(pde, va);
1489 if (pte_test(&oldpte, PTE_W))
1491 if (is_kernel_pmap(pmap))
1495 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte));
1496 if (pte_test(&oldpte, PTE_D))
1498 if (m->md.pv_flags & PV_TABLE_REF)
1499 vm_page_aflag_set(m, PGA_REFERENCED);
1500 m->md.pv_flags &= ~PV_TABLE_REF;
1501 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1502 if (TAILQ_EMPTY(&m->md.pv_list))
1503 vm_page_aflag_clear(m, PGA_WRITEABLE);
1504 pc->pc_map[field] |= 1UL << bit;
1507 * For simplicity, we will unconditionally shoot
1508 * down TLBs either at the end of this function
1509 * or at the top of the loop above if we switch
1510 * to a different pmap.
1512 (void)pmap_unuse_pt(pmap, va, *pde);
1518 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1521 /* Every freed mapping is for a 4 KB page. */
1522 pmap->pm_stats.resident_count -= freed;
1523 PV_STAT(pv_entry_frees += freed);
1524 PV_STAT(pv_entry_spare += freed);
1525 pv_entry_count -= freed;
1526 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1527 for (field = 0; field < _NPCM; field++)
1528 if (pc->pc_map[field] != pc_freemask[field]) {
1529 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1531 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1534 * One freed pv entry in locked_pmap is
1537 if (pmap == locked_pmap)
1541 if (field == _NPCM) {
1542 PV_STAT(pv_entry_spare -= _NPCPV);
1543 PV_STAT(pc_chunk_count--);
1544 PV_STAT(pc_chunk_frees++);
1545 /* Entire chunk is free; return it. */
1546 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(
1548 dump_drop_page(m_pc->phys_addr);
1553 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
1555 pmap_invalidate_all(pmap);
1556 if (pmap != locked_pmap)
1563 * free the pv_entry back to the free list
1566 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1568 struct pv_chunk *pc;
1569 int bit, field, idx;
1571 rw_assert(&pvh_global_lock, RA_WLOCKED);
1572 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1573 PV_STAT(pv_entry_frees++);
1574 PV_STAT(pv_entry_spare++);
1576 pc = pv_to_chunk(pv);
1577 idx = pv - &pc->pc_pventry[0];
1578 field = idx / (sizeof(u_long) * NBBY);
1579 bit = idx % (sizeof(u_long) * NBBY);
1580 pc->pc_map[field] |= 1ul << bit;
1581 for (idx = 0; idx < _NPCM; idx++)
1582 if (pc->pc_map[idx] != pc_freemask[idx]) {
1584 * 98% of the time, pc is already at the head of the
1585 * list. If it isn't already, move it to the head.
1587 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
1589 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1590 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1595 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1600 free_pv_chunk(struct pv_chunk *pc)
1604 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1605 PV_STAT(pv_entry_spare -= _NPCPV);
1606 PV_STAT(pc_chunk_count--);
1607 PV_STAT(pc_chunk_frees++);
1608 /* entire chunk is free, return it */
1609 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc));
1610 dump_drop_page(m->phys_addr);
1611 vm_page_unwire_noq(m);
1616 * get a new pv_entry, allocating a block from the system
1620 get_pv_entry(pmap_t pmap, boolean_t try)
1622 struct pv_chunk *pc;
1625 int bit, field, idx;
1627 rw_assert(&pvh_global_lock, RA_WLOCKED);
1628 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1629 PV_STAT(pv_entry_allocs++);
1632 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1634 for (field = 0; field < _NPCM; field++) {
1635 if (pc->pc_map[field]) {
1636 bit = ffsl(pc->pc_map[field]) - 1;
1640 if (field < _NPCM) {
1641 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
1642 pv = &pc->pc_pventry[idx];
1643 pc->pc_map[field] &= ~(1ul << bit);
1644 /* If this was the last item, move it to tail */
1645 for (field = 0; field < _NPCM; field++)
1646 if (pc->pc_map[field] != 0) {
1647 PV_STAT(pv_entry_spare--);
1648 return (pv); /* not full, return */
1650 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1651 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
1652 PV_STAT(pv_entry_spare--);
1656 /* No free items, allocate another chunk */
1657 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL |
1662 PV_STAT(pc_chunk_tryfail++);
1665 m = pmap_pv_reclaim(pmap);
1669 PV_STAT(pc_chunk_count++);
1670 PV_STAT(pc_chunk_allocs++);
1671 dump_add_page(m->phys_addr);
1672 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1674 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
1675 for (field = 1; field < _NPCM; field++)
1676 pc->pc_map[field] = pc_freemask[field];
1677 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1678 pv = &pc->pc_pventry[0];
1679 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1680 PV_STAT(pv_entry_spare += _NPCPV - 1);
1685 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1689 rw_assert(&pvh_global_lock, RA_WLOCKED);
1690 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
1691 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1692 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
1700 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1704 pv = pmap_pvh_remove(pvh, pmap, va);
1705 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx",
1706 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)),
1708 free_pv_entry(pmap, pv);
1712 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
1715 rw_assert(&pvh_global_lock, RA_WLOCKED);
1716 pmap_pvh_free(&m->md, pmap, va);
1717 if (TAILQ_EMPTY(&m->md.pv_list))
1718 vm_page_aflag_clear(m, PGA_WRITEABLE);
1722 * Conditionally create a pv entry.
1725 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va,
1730 rw_assert(&pvh_global_lock, RA_WLOCKED);
1731 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1732 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
1734 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
1741 * pmap_remove_pte: do the things to unmap a page in a process
1743 * Returns true if this was the last PTE in the PT (and possibly the last PT in
1744 * the PD, and possibly the last PD in the segmap), in which case...
1746 * 1) the TLB has been invalidated for the whole PT's span (at least),
1747 * already, to ensure that MipsDoTLBMiss does not attempt to follow a
1748 * dangling pointer into a freed page. No additional TLB shootdown is
1751 * 2) if this removal was part of a sweep to remove PTEs, it is safe to jump
1752 * to the PT span boundary and continue.
1754 * 3) The given pde may now point onto a freed page and must not be
1757 * If the return value is false, the TLB has not been shot down (and the segmap
1758 * entry, PD, and PT all remain in place).
1761 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
1768 rw_assert(&pvh_global_lock, RA_WLOCKED);
1769 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1772 * Write back all cache lines from the page being unmapped.
1774 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
1777 if (is_kernel_pmap(pmap))
1782 if (pte_test(&oldpte, PTE_W))
1783 pmap->pm_stats.wired_count -= 1;
1785 pmap->pm_stats.resident_count -= 1;
1787 if (pte_test(&oldpte, PTE_MANAGED)) {
1788 pa = TLBLO_PTE_TO_PA(oldpte);
1789 m = PHYS_TO_VM_PAGE(pa);
1790 if (pte_test(&oldpte, PTE_D)) {
1791 KASSERT(!pte_test(&oldpte, PTE_RO),
1792 ("%s: modified page not writable: va: %p, pte: %#jx",
1793 __func__, (void *)va, (uintmax_t)oldpte));
1796 if (m->md.pv_flags & PV_TABLE_REF)
1797 vm_page_aflag_set(m, PGA_REFERENCED);
1798 m->md.pv_flags &= ~PV_TABLE_REF;
1800 pmap_remove_entry(pmap, m, va);
1802 return (pmap_unuse_pt(pmap, va, pde));
1806 * Remove a single page from a process address space
1809 pmap_remove_page(struct pmap *pmap, vm_offset_t va)
1814 rw_assert(&pvh_global_lock, RA_WLOCKED);
1815 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1816 pde = pmap_pde(pmap, va);
1817 if (pde == NULL || *pde == 0)
1819 ptq = pmap_pde_to_pte(pde, va);
1822 * If there is no pte for this address, just skip it!
1824 if (!pte_test(ptq, PTE_V))
1828 * Remove this PTE from the PT. If this is the last one, then
1829 * the TLB has already been shot down, so don't bother again
1831 if (!pmap_remove_pte(pmap, ptq, va, *pde))
1832 pmap_invalidate_page(pmap, va);
1836 * Remove the given range of addresses from the specified map.
1838 * It is assumed that the start and end are properly
1839 * rounded to the page size.
1842 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1844 pd_entry_t *pde, *pdpe;
1846 vm_offset_t va_next;
1847 vm_offset_t va_init, va_fini;
1848 bool need_tlb_shootdown;
1851 * Perform an unsynchronized read. This is, however, safe.
1853 if (pmap->pm_stats.resident_count == 0)
1856 rw_wlock(&pvh_global_lock);
1860 * special handling of removing one page. a very common operation
1861 * and easy to short circuit some code.
1863 if ((sva + PAGE_SIZE) == eva) {
1864 pmap_remove_page(pmap, sva);
1867 for (; sva < eva; sva = va_next) {
1868 pdpe = pmap_segmap(pmap, sva);
1871 va_next = (sva + NBSEG) & ~SEGMASK;
1878 /* Scan up to the end of the page table pointed to by pde */
1879 va_next = (sva + NBPDR) & ~PDRMASK;
1883 pde = pmap_pdpe_to_pde(pdpe, sva);
1888 * Limit our scan to either the end of the va represented
1889 * by the current page table page, or to the end of the
1890 * range being removed.
1895 need_tlb_shootdown = false;
1898 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1900 /* Skip over invalid entries; no need to shootdown */
1901 if (!pte_test(pte, PTE_V)) {
1903 * If we have not yet found a valid entry, then
1904 * we can move the lower edge of the region to
1905 * invalidate to the next PTE.
1907 if (!need_tlb_shootdown)
1908 va_init = sva + PAGE_SIZE;
1913 * A valid entry; the range we are shooting down must
1914 * include this page. va_fini is used instead of sva
1915 * so that if the range ends with a run of !PTE_V PTEs,
1916 * but doesn't clear out so much that pmap_remove_pte
1917 * removes the entire PT, we won't include these !PTE_V
1918 * entries in the region to be shot down.
1920 va_fini = sva + PAGE_SIZE;
1922 if (pmap_remove_pte(pmap, pte, sva, *pde)) {
1923 /* Entire PT removed and TLBs shot down. */
1924 need_tlb_shootdown = false;
1927 need_tlb_shootdown = true;
1930 if (need_tlb_shootdown)
1931 pmap_invalidate_range(pmap, va_init, va_fini);
1934 rw_wunlock(&pvh_global_lock);
1939 * Routine: pmap_remove_all
1941 * Removes this physical page from
1942 * all physical maps in which it resides.
1943 * Reflects back modify bits to the pager.
1946 * Original versions of this routine were very
1947 * inefficient because they iteratively called
1948 * pmap_remove (slow...)
1952 pmap_remove_all(vm_page_t m)
1957 pt_entry_t *pte, tpte;
1959 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1960 ("pmap_remove_all: page %p is not managed", m));
1961 rw_wlock(&pvh_global_lock);
1963 if (m->md.pv_flags & PV_TABLE_REF)
1964 vm_page_aflag_set(m, PGA_REFERENCED);
1966 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
1971 * If it's last mapping writeback all caches from
1972 * the page being destroyed
1974 if (TAILQ_NEXT(pv, pv_list) == NULL)
1975 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
1977 pmap->pm_stats.resident_count--;
1979 pde = pmap_pde(pmap, pv->pv_va);
1980 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde"));
1981 pte = pmap_pde_to_pte(pde, pv->pv_va);
1984 if (is_kernel_pmap(pmap))
1989 if (pte_test(&tpte, PTE_W))
1990 pmap->pm_stats.wired_count--;
1993 * Update the vm_page_t clean and reference bits.
1995 if (pte_test(&tpte, PTE_D)) {
1996 KASSERT(!pte_test(&tpte, PTE_RO),
1997 ("%s: modified page not writable: va: %p, pte: %#jx",
1998 __func__, (void *)pv->pv_va, (uintmax_t)tpte));
2002 if (!pmap_unuse_pt(pmap, pv->pv_va, *pde))
2003 pmap_invalidate_page(pmap, pv->pv_va);
2005 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2006 free_pv_entry(pmap, pv);
2010 vm_page_aflag_clear(m, PGA_WRITEABLE);
2011 m->md.pv_flags &= ~PV_TABLE_REF;
2012 rw_wunlock(&pvh_global_lock);
2016 * Set the physical protection on the
2017 * specified range of this map as requested.
2020 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
2022 pt_entry_t pbits, *pte;
2023 pd_entry_t *pde, *pdpe;
2024 vm_offset_t va, va_next;
2028 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
2029 pmap_remove(pmap, sva, eva);
2032 if (prot & VM_PROT_WRITE)
2036 for (; sva < eva; sva = va_next) {
2037 pdpe = pmap_segmap(pmap, sva);
2040 va_next = (sva + NBSEG) & ~SEGMASK;
2046 va_next = (sva + NBPDR) & ~PDRMASK;
2050 pde = pmap_pdpe_to_pde(pdpe, sva);
2055 * Limit our scan to either the end of the va represented
2056 * by the current page table page, or to the end of the
2057 * range being write protected.
2063 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2066 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits,
2068 if (va != va_next) {
2069 pmap_invalidate_range(pmap, va, sva);
2074 pte_set(&pbits, PTE_RO);
2075 if (pte_test(&pbits, PTE_D)) {
2076 pte_clear(&pbits, PTE_D);
2077 if (pte_test(&pbits, PTE_MANAGED)) {
2078 pa = TLBLO_PTE_TO_PA(pbits);
2079 m = PHYS_TO_VM_PAGE(pa);
2086 * Unless PTE_D is set, any TLB entries
2087 * mapping "sva" don't allow write access, so
2088 * they needn't be invalidated.
2090 if (va != va_next) {
2091 pmap_invalidate_range(pmap, va, sva);
2098 pmap_invalidate_range(pmap, va, sva);
2104 * Insert the given physical page (p) at
2105 * the specified virtual address (v) in the
2106 * target physical map with the protection requested.
2108 * If specified, the page will be wired down, meaning
2109 * that the related pte can not be reclaimed.
2111 * NB: This is the only routine which MAY NOT lazy-evaluate
2112 * or lose information. That is, this routine must actually
2113 * insert this page into the given map NOW.
2116 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2117 u_int flags, int8_t psind __unused)
2121 pt_entry_t origpte, newpte;
2126 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2127 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
2128 va >= kmi.clean_eva,
2129 ("pmap_enter: managed mapping within the clean submap"));
2130 if ((m->oflags & VPO_UNMANAGED) == 0)
2131 VM_PAGE_OBJECT_BUSY_ASSERT(m);
2132 pa = VM_PAGE_TO_PHYS(m);
2133 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot);
2134 if ((flags & PMAP_ENTER_WIRED) != 0)
2136 if (is_kernel_pmap(pmap))
2138 PMAP_PTE_SET_CACHE_BITS(newpte, pa, m);
2139 if ((m->oflags & VPO_UNMANAGED) == 0)
2140 newpte |= PTE_MANAGED;
2144 rw_wlock(&pvh_global_lock);
2148 * In the case that a page table page is not resident, we are
2151 if (va < VM_MAXUSER_ADDRESS) {
2152 mpte = pmap_allocpte(pmap, va, flags);
2154 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
2155 ("pmap_allocpte failed with sleep allowed"));
2156 rw_wunlock(&pvh_global_lock);
2158 return (KERN_RESOURCE_SHORTAGE);
2161 pte = pmap_pte(pmap, va);
2164 * Page Directory table entry not valid, we need a new PT page
2167 panic("pmap_enter: invalid page directory, pdir=%p, va=%p",
2168 (void *)pmap->pm_segtab, (void *)va);
2172 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO | PTE_V),
2173 ("pmap_enter: modified page not writable: va: %p, pte: %#jx",
2174 (void *)va, (uintmax_t)origpte));
2175 opa = TLBLO_PTE_TO_PA(origpte);
2178 * Mapping has not changed, must be protection or wiring change.
2180 if (pte_test(&origpte, PTE_V) && opa == pa) {
2182 * Wiring change, just update stats. We don't worry about
2183 * wiring PT pages as they remain resident as long as there
2184 * are valid mappings in them. Hence, if a user page is
2185 * wired, the PT page will be also.
2187 if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W))
2188 pmap->pm_stats.wired_count++;
2189 else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte,
2191 pmap->pm_stats.wired_count--;
2194 * Remove extra pte reference
2199 if (pte_test(&origpte, PTE_MANAGED)) {
2200 m->md.pv_flags |= PV_TABLE_REF;
2201 if (!pte_test(&newpte, PTE_RO))
2202 vm_page_aflag_set(m, PGA_WRITEABLE);
2210 * Mapping has changed, invalidate old range and fall through to
2211 * handle validating new mapping.
2214 if (is_kernel_pmap(pmap))
2218 if (pte_test(&origpte, PTE_W))
2219 pmap->pm_stats.wired_count--;
2220 if (pte_test(&origpte, PTE_MANAGED)) {
2221 om = PHYS_TO_VM_PAGE(opa);
2222 if (pte_test(&origpte, PTE_D))
2224 if ((om->md.pv_flags & PV_TABLE_REF) != 0) {
2225 om->md.pv_flags &= ~PV_TABLE_REF;
2226 vm_page_aflag_set(om, PGA_REFERENCED);
2228 pv = pmap_pvh_remove(&om->md, pmap, va);
2229 if (!pte_test(&newpte, PTE_MANAGED))
2230 free_pv_entry(pmap, pv);
2231 if ((om->a.flags & PGA_WRITEABLE) != 0 &&
2232 TAILQ_EMPTY(&om->md.pv_list))
2233 vm_page_aflag_clear(om, PGA_WRITEABLE);
2235 pmap_invalidate_page(pmap, va);
2239 KASSERT(mpte->ref_count > 0,
2240 ("pmap_enter: missing reference to page table page,"
2241 " va: %p", (void *)va));
2244 pmap->pm_stats.resident_count++;
2247 * Enter on the PV list if part of our managed memory.
2249 if (pte_test(&newpte, PTE_MANAGED)) {
2250 m->md.pv_flags |= PV_TABLE_REF;
2252 pv = get_pv_entry(pmap, FALSE);
2255 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2256 if (!pte_test(&newpte, PTE_RO))
2257 vm_page_aflag_set(m, PGA_WRITEABLE);
2261 * Increment counters
2263 if (pte_test(&newpte, PTE_W))
2264 pmap->pm_stats.wired_count++;
2269 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
2273 * if the mapping or permission bits are different, we need to
2276 if (origpte != newpte) {
2278 if (pte_test(&origpte, PTE_V)) {
2279 KASSERT(opa == pa, ("pmap_enter: invalid update"));
2280 if (pte_test(&origpte, PTE_D)) {
2281 if (pte_test(&origpte, PTE_MANAGED))
2284 pmap_update_page(pmap, va, newpte);
2289 * Sync I & D caches for executable pages. Do this only if the
2290 * target pmap belongs to the current process. Otherwise, an
2291 * unresolvable TLB miss may occur.
2293 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
2294 (prot & VM_PROT_EXECUTE)) {
2295 mips_icache_sync_range(va, PAGE_SIZE);
2296 mips_dcache_wbinv_range(va, PAGE_SIZE);
2298 rw_wunlock(&pvh_global_lock);
2300 return (KERN_SUCCESS);
2304 * this code makes some *MAJOR* assumptions:
2305 * 1. Current pmap & pmap exists.
2308 * 4. No page table pages.
2309 * but is *MUCH* faster than pmap_enter...
2313 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2316 rw_wlock(&pvh_global_lock);
2318 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
2319 rw_wunlock(&pvh_global_lock);
2324 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2325 vm_prot_t prot, vm_page_t mpte)
2327 pt_entry_t *pte, npte;
2330 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2331 (m->oflags & VPO_UNMANAGED) != 0,
2332 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2333 rw_assert(&pvh_global_lock, RA_WLOCKED);
2334 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2337 * In the case that a page table page is not resident, we are
2340 if (va < VM_MAXUSER_ADDRESS) {
2345 * Calculate pagetable page index
2347 ptepindex = pmap_pde_pindex(va);
2348 if (mpte && (mpte->pindex == ptepindex)) {
2352 * Get the page directory entry
2354 pde = pmap_pde(pmap, va);
2357 * If the page table page is mapped, we just
2358 * increment the hold count, and activate it.
2360 if (pde && *pde != 0) {
2361 mpte = PHYS_TO_VM_PAGE(
2362 MIPS_DIRECT_TO_PHYS(*pde));
2365 mpte = _pmap_allocpte(pmap, ptepindex,
2366 PMAP_ENTER_NOSLEEP);
2375 pte = pmap_pte(pmap, va);
2376 if (pte_test(pte, PTE_V)) {
2385 * Enter on the PV list if part of our managed memory.
2387 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2388 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) {
2390 pmap_unwire_ptp(pmap, va, mpte);
2397 * Increment counters
2399 pmap->pm_stats.resident_count++;
2401 pa = VM_PAGE_TO_PHYS(m);
2404 * Now validate mapping with RO protection
2406 npte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V;
2407 if ((m->oflags & VPO_UNMANAGED) == 0)
2408 npte |= PTE_MANAGED;
2410 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2412 if (is_kernel_pmap(pmap))
2413 *pte = npte | PTE_G;
2417 * Sync I & D caches. Do this only if the target pmap
2418 * belongs to the current process. Otherwise, an
2419 * unresolvable TLB miss may occur. */
2420 if (pmap == &curproc->p_vmspace->vm_pmap) {
2422 mips_icache_sync_range(va, PAGE_SIZE);
2423 mips_dcache_wbinv_range(va, PAGE_SIZE);
2430 * Make a temporary mapping for a physical address. This is only intended
2431 * to be used for panic dumps.
2433 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2436 pmap_kenter_temporary(vm_paddr_t pa, int i)
2441 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
2444 if (MIPS_DIRECT_MAPPABLE(pa)) {
2445 va = MIPS_PHYS_TO_DIRECT(pa);
2447 #ifndef __mips_n64 /* XXX : to be converted to new style */
2448 pt_entry_t *pte, npte;
2450 pte = pmap_pte(kernel_pmap, crashdumpva);
2452 /* Since this is for the debugger, no locks or any other fun */
2453 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
2456 pmap_update_page(kernel_pmap, crashdumpva, npte);
2460 return ((void *)va);
2464 pmap_kenter_temporary_free(vm_paddr_t pa)
2466 #ifndef __mips_n64 /* XXX : to be converted to new style */
2469 if (MIPS_DIRECT_MAPPABLE(pa)) {
2470 /* nothing to do for this case */
2473 #ifndef __mips_n64 /* XXX : to be converted to new style */
2474 pte = pmap_pte(kernel_pmap, crashdumpva);
2476 pmap_invalidate_page(kernel_pmap, crashdumpva);
2481 * Maps a sequence of resident pages belonging to the same object.
2482 * The sequence begins with the given page m_start. This page is
2483 * mapped at the given virtual address start. Each subsequent page is
2484 * mapped at a virtual address that is offset from start by the same
2485 * amount as the page is offset from m_start within the object. The
2486 * last page in the sequence is the page with the largest offset from
2487 * m_start that can be mapped at a virtual address less than the given
2488 * virtual address end. Not every virtual page between start and end
2489 * is mapped; only those for which a resident page exists with the
2490 * corresponding offset from m_start are mapped.
2493 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2494 vm_page_t m_start, vm_prot_t prot)
2497 vm_pindex_t diff, psize;
2499 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2501 psize = atop(end - start);
2504 rw_wlock(&pvh_global_lock);
2506 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2507 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m,
2509 m = TAILQ_NEXT(m, listq);
2511 rw_wunlock(&pvh_global_lock);
2516 * pmap_object_init_pt preloads the ptes for a given object
2517 * into the specified pmap. This eliminates the blast of soft
2518 * faults on process startup and immediately after an mmap.
2521 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
2522 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2524 VM_OBJECT_ASSERT_WLOCKED(object);
2525 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2526 ("pmap_object_init_pt: non-device object"));
2530 * Clear the wired attribute from the mappings for the specified range of
2531 * addresses in the given pmap. Every valid mapping within that range
2532 * must have the wired attribute set. In contrast, invalid mappings
2533 * cannot have the wired attribute set, so they are ignored.
2535 * The wired attribute of the page table entry is not a hardware feature,
2536 * so there is no need to invalidate any TLB entries.
2539 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2541 pd_entry_t *pde, *pdpe;
2543 vm_offset_t va_next;
2546 for (; sva < eva; sva = va_next) {
2547 pdpe = pmap_segmap(pmap, sva);
2549 if (*pdpe == NULL) {
2550 va_next = (sva + NBSEG) & ~SEGMASK;
2556 va_next = (sva + NBPDR) & ~PDRMASK;
2559 pde = pmap_pdpe_to_pde(pdpe, sva);
2564 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2566 if (!pte_test(pte, PTE_V))
2568 if (!pte_test(pte, PTE_W))
2569 panic("pmap_unwire: pte %#jx is missing PG_W",
2571 pte_clear(pte, PTE_W);
2572 pmap->pm_stats.wired_count--;
2579 * Copy the range specified by src_addr/len
2580 * from the source map to the range dst_addr/len
2581 * in the destination map.
2583 * This routine is only advisory and need not do anything.
2587 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2588 vm_size_t len, vm_offset_t src_addr)
2593 * pmap_zero_page zeros the specified hardware page by mapping
2594 * the page into KVM and using bzero to clear its contents.
2596 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2599 pmap_zero_page(vm_page_t m)
2602 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2604 if (MIPS_DIRECT_MAPPABLE(phys)) {
2605 va = MIPS_PHYS_TO_DIRECT(phys);
2606 bzero((caddr_t)va, PAGE_SIZE);
2607 mips_dcache_wbinv_range(va, PAGE_SIZE);
2609 va = pmap_lmem_map1(phys);
2610 bzero((caddr_t)va, PAGE_SIZE);
2611 mips_dcache_wbinv_range(va, PAGE_SIZE);
2617 * pmap_zero_page_area zeros the specified hardware page by mapping
2618 * the page into KVM and using bzero to clear its contents.
2620 * off and size may not cover an area beyond a single hardware page.
2623 pmap_zero_page_area(vm_page_t m, int off, int size)
2626 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2628 if (MIPS_DIRECT_MAPPABLE(phys)) {
2629 va = MIPS_PHYS_TO_DIRECT(phys);
2630 bzero((char *)(caddr_t)va + off, size);
2631 mips_dcache_wbinv_range(va + off, size);
2633 va = pmap_lmem_map1(phys);
2634 bzero((char *)va + off, size);
2635 mips_dcache_wbinv_range(va + off, size);
2641 * pmap_copy_page copies the specified (machine independent)
2642 * page by mapping the page into virtual memory and using
2643 * bcopy to copy the page, one machine dependent page at a
2646 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2649 pmap_copy_page(vm_page_t src, vm_page_t dst)
2651 vm_offset_t va_src, va_dst;
2652 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src);
2653 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst);
2655 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) {
2656 /* easy case, all can be accessed via KSEG0 */
2658 * Flush all caches for VA that are mapped to this page
2659 * to make sure that data in SDRAM is up to date
2661 pmap_flush_pvcache(src);
2662 mips_dcache_wbinv_range_index(
2663 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE);
2664 va_src = MIPS_PHYS_TO_DIRECT(phys_src);
2665 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst);
2666 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
2667 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2669 va_src = pmap_lmem_map2(phys_src, phys_dst);
2670 va_dst = va_src + PAGE_SIZE;
2671 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE);
2672 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2677 int unmapped_buf_allowed;
2680 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2681 vm_offset_t b_offset, int xfersize)
2685 vm_offset_t a_pg_offset, b_pg_offset;
2686 vm_paddr_t a_phys, b_phys;
2689 while (xfersize > 0) {
2690 a_pg_offset = a_offset & PAGE_MASK;
2691 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2692 a_m = ma[a_offset >> PAGE_SHIFT];
2693 a_phys = VM_PAGE_TO_PHYS(a_m);
2694 b_pg_offset = b_offset & PAGE_MASK;
2695 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2696 b_m = mb[b_offset >> PAGE_SHIFT];
2697 b_phys = VM_PAGE_TO_PHYS(b_m);
2698 if (MIPS_DIRECT_MAPPABLE(a_phys) &&
2699 MIPS_DIRECT_MAPPABLE(b_phys)) {
2700 pmap_flush_pvcache(a_m);
2701 mips_dcache_wbinv_range_index(
2702 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE);
2703 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) +
2705 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) +
2707 bcopy(a_cp, b_cp, cnt);
2708 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2710 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys);
2711 b_cp = (char *)a_cp + PAGE_SIZE;
2712 a_cp += a_pg_offset;
2713 b_cp += b_pg_offset;
2714 bcopy(a_cp, b_cp, cnt);
2715 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2725 pmap_quick_enter_page(vm_page_t m)
2727 #if defined(__mips_n64)
2728 return MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
2732 pt_entry_t *pte, npte;
2734 pa = VM_PAGE_TO_PHYS(m);
2736 if (MIPS_DIRECT_MAPPABLE(pa)) {
2737 if (pmap_page_get_memattr(m) != VM_MEMATTR_WRITE_BACK)
2738 return (MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
2740 return (MIPS_PHYS_TO_DIRECT(pa));
2743 qaddr = PCPU_GET(qmap_addr);
2744 pte = PCPU_GET(qmap_ptep);
2746 KASSERT(*pte == PTE_G, ("pmap_quick_enter_page: PTE busy"));
2748 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G;
2749 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2757 pmap_quick_remove_page(vm_offset_t addr)
2759 mips_dcache_wbinv_range(addr, PAGE_SIZE);
2761 #if !defined(__mips_n64)
2764 if (addr >= MIPS_KSEG0_START && addr < MIPS_KSEG0_END)
2767 pte = PCPU_GET(qmap_ptep);
2769 KASSERT(*pte != PTE_G,
2770 ("pmap_quick_remove_page: PTE not in use"));
2771 KASSERT(PCPU_GET(qmap_addr) == addr,
2772 ("pmap_quick_remove_page: invalid address"));
2775 tlb_invalidate_address(kernel_pmap, addr);
2781 * Returns true if the pmap's pv is one of the first
2782 * 16 pvs linked to from this page. This count may
2783 * be changed upwards or downwards in the future; it
2784 * is only necessary that true be returned for a small
2785 * subset of pmaps for proper page aging.
2788 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2794 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2795 ("pmap_page_exists_quick: page %p is not managed", m));
2797 rw_wlock(&pvh_global_lock);
2798 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2799 if (PV_PMAP(pv) == pmap) {
2807 rw_wunlock(&pvh_global_lock);
2812 * Remove all pages from specified address space
2813 * this aids process exit speeds. Also, this code
2814 * is special cased for current process only, but
2815 * can have the more generic (and slightly slower)
2816 * mode enabled. This is much faster than pmap_remove
2817 * in the case of running down an entire address space.
2820 pmap_remove_pages(pmap_t pmap)
2823 pt_entry_t *pte, tpte;
2826 struct pv_chunk *pc, *npc;
2827 u_long inuse, bitmask;
2828 int allfree, bit, field, idx;
2830 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
2831 printf("warning: pmap_remove_pages called with non-current pmap\n");
2834 rw_wlock(&pvh_global_lock);
2836 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2838 for (field = 0; field < _NPCM; field++) {
2839 inuse = ~pc->pc_map[field] & pc_freemask[field];
2840 while (inuse != 0) {
2841 bit = ffsl(inuse) - 1;
2842 bitmask = 1UL << bit;
2843 idx = field * sizeof(inuse) * NBBY + bit;
2844 pv = &pc->pc_pventry[idx];
2847 pde = pmap_pde(pmap, pv->pv_va);
2848 KASSERT(pde != NULL && *pde != 0,
2849 ("pmap_remove_pages: pde"));
2850 pte = pmap_pde_to_pte(pde, pv->pv_va);
2851 if (!pte_test(pte, PTE_V))
2852 panic("pmap_remove_pages: bad pte");
2856 * We cannot remove wired pages from a process' mapping at this time
2858 if (pte_test(&tpte, PTE_W)) {
2862 *pte = is_kernel_pmap(pmap) ? PTE_G : 0;
2864 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte));
2866 ("pmap_remove_pages: bad tpte %#jx",
2870 * Update the vm_page_t clean and reference bits.
2872 if (pte_test(&tpte, PTE_D))
2876 PV_STAT(pv_entry_frees++);
2877 PV_STAT(pv_entry_spare++);
2879 pc->pc_map[field] |= bitmask;
2880 pmap->pm_stats.resident_count--;
2881 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2882 if (TAILQ_EMPTY(&m->md.pv_list))
2883 vm_page_aflag_clear(m, PGA_WRITEABLE);
2886 * For simplicity, unconditionally call
2887 * pmap_invalidate_all(), below.
2889 (void)pmap_unuse_pt(pmap, pv->pv_va, *pde);
2893 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2897 pmap_invalidate_all(pmap);
2899 rw_wunlock(&pvh_global_lock);
2903 * pmap_testbit tests bits in pte's
2906 pmap_testbit(vm_page_t m, int bit)
2911 boolean_t rv = FALSE;
2913 if (m->oflags & VPO_UNMANAGED)
2916 rw_assert(&pvh_global_lock, RA_WLOCKED);
2917 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2920 pte = pmap_pte(pmap, pv->pv_va);
2921 rv = pte_test(pte, bit);
2930 * pmap_page_wired_mappings:
2932 * Return the number of managed mappings to the given physical page
2936 pmap_page_wired_mappings(vm_page_t m)
2944 if ((m->oflags & VPO_UNMANAGED) != 0)
2946 rw_wlock(&pvh_global_lock);
2947 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2950 pte = pmap_pte(pmap, pv->pv_va);
2951 if (pte_test(pte, PTE_W))
2955 rw_wunlock(&pvh_global_lock);
2960 * Clear the write and modified bits in each of the given page's mappings.
2963 pmap_remove_write(vm_page_t m)
2966 pt_entry_t pbits, *pte;
2969 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2970 ("pmap_remove_write: page %p is not managed", m));
2971 vm_page_assert_busied(m);
2973 if (!pmap_page_is_write_mapped(m))
2975 rw_wlock(&pvh_global_lock);
2976 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2979 pte = pmap_pte(pmap, pv->pv_va);
2980 KASSERT(pte != NULL && pte_test(pte, PTE_V),
2981 ("page on pv_list has no pte"));
2983 if (pte_test(&pbits, PTE_D)) {
2984 pte_clear(&pbits, PTE_D);
2987 pte_set(&pbits, PTE_RO);
2988 if (pbits != *pte) {
2990 pmap_update_page(pmap, pv->pv_va, pbits);
2994 vm_page_aflag_clear(m, PGA_WRITEABLE);
2995 rw_wunlock(&pvh_global_lock);
2999 * pmap_ts_referenced:
3001 * Return the count of reference bits for a page, clearing all of them.
3004 pmap_ts_referenced(vm_page_t m)
3007 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3008 ("pmap_ts_referenced: page %p is not managed", m));
3009 if (m->md.pv_flags & PV_TABLE_REF) {
3010 rw_wlock(&pvh_global_lock);
3011 m->md.pv_flags &= ~PV_TABLE_REF;
3012 rw_wunlock(&pvh_global_lock);
3021 * Return whether or not the specified physical page was modified
3022 * in any physical maps.
3025 pmap_is_modified(vm_page_t m)
3029 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3030 ("pmap_is_modified: page %p is not managed", m));
3033 * If the page is not busied then this check is racy.
3035 if (!pmap_page_is_write_mapped(m))
3038 rw_wlock(&pvh_global_lock);
3039 rv = pmap_testbit(m, PTE_D);
3040 rw_wunlock(&pvh_global_lock);
3047 * pmap_is_prefaultable:
3049 * Return whether or not the specified virtual address is elgible
3053 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3061 pde = pmap_pde(pmap, addr);
3062 if (pde != NULL && *pde != 0) {
3063 pte = pmap_pde_to_pte(pde, addr);
3071 * Apply the given advice to the specified range of addresses within the
3072 * given pmap. Depending on the advice, clear the referenced and/or
3073 * modified flags in each mapping and set the mapped page's dirty field.
3076 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3078 pd_entry_t *pde, *pdpe;
3080 vm_offset_t va, va_next;
3084 if (advice != MADV_DONTNEED && advice != MADV_FREE)
3086 rw_wlock(&pvh_global_lock);
3088 for (; sva < eva; sva = va_next) {
3089 pdpe = pmap_segmap(pmap, sva);
3092 va_next = (sva + NBSEG) & ~SEGMASK;
3098 va_next = (sva + NBPDR) & ~PDRMASK;
3102 pde = pmap_pdpe_to_pde(pdpe, sva);
3107 * Limit our scan to either the end of the va represented
3108 * by the current page table page, or to the end of the
3109 * range being write protected.
3115 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3117 if (!pte_test(pte, PTE_MANAGED | PTE_V)) {
3118 if (va != va_next) {
3119 pmap_invalidate_range(pmap, va, sva);
3124 pa = TLBLO_PTE_TO_PA(*pte);
3125 m = PHYS_TO_VM_PAGE(pa);
3126 m->md.pv_flags &= ~PV_TABLE_REF;
3127 if (pte_test(pte, PTE_D)) {
3128 if (advice == MADV_DONTNEED) {
3130 * Future calls to pmap_is_modified()
3131 * can be avoided by making the page
3136 pte_clear(pte, PTE_D);
3142 * Unless PTE_D is set, any TLB entries
3143 * mapping "sva" don't allow write access, so
3144 * they needn't be invalidated.
3146 if (va != va_next) {
3147 pmap_invalidate_range(pmap, va, sva);
3153 pmap_invalidate_range(pmap, va, sva);
3155 rw_wunlock(&pvh_global_lock);
3160 * Clear the modify bits on the specified physical page.
3163 pmap_clear_modify(vm_page_t m)
3169 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3170 ("pmap_clear_modify: page %p is not managed", m));
3171 vm_page_assert_busied(m);
3173 if (!pmap_page_is_write_mapped(m))
3175 rw_wlock(&pvh_global_lock);
3176 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3179 pte = pmap_pte(pmap, pv->pv_va);
3180 if (pte_test(pte, PTE_D)) {
3181 pte_clear(pte, PTE_D);
3182 pmap_update_page(pmap, pv->pv_va, *pte);
3186 rw_wunlock(&pvh_global_lock);
3190 * pmap_is_referenced:
3192 * Return whether or not the specified physical page was referenced
3193 * in any physical maps.
3196 pmap_is_referenced(vm_page_t m)
3199 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3200 ("pmap_is_referenced: page %p is not managed", m));
3201 return ((m->md.pv_flags & PV_TABLE_REF) != 0);
3205 * Miscellaneous support routines follow
3209 * Map a set of physical memory pages into the kernel virtual
3210 * address space. Return a pointer to where it is mapped. This
3211 * routine is intended to be used for mapping device memory,
3214 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit.
3217 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3219 vm_offset_t va, tmpva, offset;
3222 * KSEG1 maps only first 512M of phys address space. For
3223 * pa > 0x20000000 we should make proper mapping * using pmap_kenter.
3225 if (MIPS_DIRECT_MAPPABLE(pa + size - 1) && ma == VM_MEMATTR_UNCACHEABLE)
3226 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
3228 offset = pa & PAGE_MASK;
3229 size = roundup(size + offset, PAGE_SIZE);
3231 va = kva_alloc(size);
3233 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3234 pa = trunc_page(pa);
3235 for (tmpva = va; size > 0;) {
3236 pmap_kenter_attr(tmpva, pa, ma);
3243 return ((void *)(va + offset));
3247 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3249 return pmap_mapdev_attr(pa, size, VM_MEMATTR_UNCACHEABLE);
3253 pmap_unmapdev(vm_offset_t va, vm_size_t size)
3256 vm_offset_t base, offset;
3258 /* If the address is within KSEG1 then there is nothing to do */
3259 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
3262 base = trunc_page(va);
3263 offset = va & PAGE_MASK;
3264 size = roundup(size + offset, PAGE_SIZE);
3265 pmap_qremove(base, atop(size));
3266 kva_free(base, size);
3271 * Perform the pmap work for mincore(2). If the page is not both referenced and
3272 * modified by this pmap, returns its physical address so that the caller can
3273 * find other mappings.
3276 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
3278 pt_entry_t *ptep, pte;
3284 ptep = pmap_pte(pmap, addr);
3285 pte = (ptep != NULL) ? *ptep : 0;
3286 if (!pte_test(&pte, PTE_V)) {
3290 val = MINCORE_INCORE;
3291 if (pte_test(&pte, PTE_D))
3292 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3293 pa = TLBLO_PTE_TO_PA(pte);
3294 if (pte_test(&pte, PTE_MANAGED)) {
3296 * This may falsely report the given address as
3297 * MINCORE_REFERENCED. Unfortunately, due to the lack of
3298 * per-PTE reference information, it is impossible to
3299 * determine if the address is MINCORE_REFERENCED.
3301 m = PHYS_TO_VM_PAGE(pa);
3302 if ((m->a.flags & PGA_REFERENCED) != 0)
3303 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3305 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3306 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
3307 pte_test(&pte, PTE_MANAGED)) {
3315 pmap_activate(struct thread *td)
3317 pmap_t pmap, oldpmap;
3318 struct proc *p = td->td_proc;
3323 pmap = vmspace_pmap(p->p_vmspace);
3324 oldpmap = PCPU_GET(curpmap);
3325 cpuid = PCPU_GET(cpuid);
3328 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
3329 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
3330 pmap_asid_alloc(pmap);
3331 if (td == curthread) {
3332 PCPU_SET(segbase, pmap->pm_segtab);
3333 mips_wr_entryhi(pmap->pm_asid[cpuid].asid);
3336 PCPU_SET(curpmap, pmap);
3341 pmap_sync_icache_one(void *arg __unused)
3344 mips_icache_sync_all();
3345 mips_dcache_wbinv_all();
3349 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3352 smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
3356 * Increase the starting virtual address of the given mapping if a
3357 * different alignment might result in more superpage mappings.
3360 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3361 vm_offset_t *addr, vm_size_t size)
3363 vm_offset_t superpage_offset;
3367 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
3368 offset += ptoa(object->pg_color);
3369 superpage_offset = offset & PDRMASK;
3370 if (size - ((PDRSIZE - superpage_offset) & PDRMASK) < PDRSIZE ||
3371 (*addr & PDRMASK) == superpage_offset)
3373 if ((*addr & PDRMASK) < superpage_offset)
3374 *addr = (*addr & ~PDRMASK) + superpage_offset;
3376 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
3380 DB_SHOW_COMMAND(ptable, ddb_pid_dump)
3383 struct thread *td = NULL;
3390 td = db_lookup_thread(addr, true);
3392 db_printf("Invalid pid or tid");
3396 if (p->p_vmspace == NULL) {
3397 db_printf("No vmspace for process");
3400 pmap = vmspace_pmap(p->p_vmspace);
3404 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n",
3405 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid,
3406 pmap->pm_asid[0].gen);
3407 for (i = 0; i < NPDEPG; i++) {
3412 pdpe = (pd_entry_t *)pmap->pm_segtab[i];
3415 db_printf("[%4d] %p\n", i, pdpe);
3417 for (j = 0; j < NPDEPG; j++) {
3418 pde = (pt_entry_t *)pdpe[j];
3421 db_printf("\t[%4d] %p\n", j, pde);
3425 pde = (pt_entry_t *)pdpe;
3427 for (k = 0; k < NPTEPG; k++) {
3429 if (pte == 0 || !pte_test(&pte, PTE_V))
3431 pa = TLBLO_PTE_TO_PA(pte);
3432 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT);
3433 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n",
3434 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa);
3442 * Allocate TLB address space tag (called ASID or TLBPID) and return it.
3443 * It takes almost as much or more time to search the TLB for a
3444 * specific ASID and flush those entries as it does to flush the entire TLB.
3445 * Therefore, when we allocate a new ASID, we just take the next number. When
3446 * we run out of numbers, we flush the TLB, increment the generation count
3447 * and start over. ASID zero is reserved for kernel use.
3450 pmap_asid_alloc(pmap)
3453 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED &&
3454 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
3456 if (PCPU_GET(next_asid) == pmap_max_asid) {
3457 tlb_invalidate_all_user(NULL);
3458 PCPU_SET(asid_generation,
3459 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
3460 if (PCPU_GET(asid_generation) == 0) {
3461 PCPU_SET(asid_generation, 1);
3463 PCPU_SET(next_asid, 1); /* 0 means invalid */
3465 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid);
3466 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation);
3467 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1);
3472 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot)
3476 if (!(prot & VM_PROT_WRITE))
3477 rw = PTE_V | PTE_RO;
3478 else if ((m->oflags & VPO_UNMANAGED) == 0) {
3479 if ((access & VM_PROT_WRITE) != 0)
3484 /* Needn't emulate a modified bit for unmanaged pages. */
3490 * pmap_emulate_modified : do dirty bit emulation
3492 * On SMP, update just the local TLB, other CPUs will update their
3493 * TLBs from PTE lazily, if they get the exception.
3494 * Returns 0 in case of sucess, 1 if the page is read only and we
3498 pmap_emulate_modified(pmap_t pmap, vm_offset_t va)
3503 pte = pmap_pte(pmap, va);
3506 * It is possible that some other CPU or thread changed the pmap while
3507 * we weren't looking; in the SMP case, this is readily apparent, but
3508 * it can even happen in the UP case, because we may have been blocked
3509 * on PMAP_LOCK(pmap) above while someone changed this out from
3515 * This PTE's PTP (or one of its ancestors) has been reclaimed;
3516 * trigger a full fault to reconstruct it via pmap_enter.
3522 if (!pte_test(pte, PTE_V)) {
3524 * This PTE is no longer valid; the other thread or other
3525 * processor must have arranged for our TLB to no longer
3526 * have this entry, possibly by IPI, so no tlb_update is
3527 * required. Fall out of the fast path and go take a
3528 * general fault before retrying the instruction (or taking
3535 if (pte_test(pte, PTE_D)) {
3537 * This PTE is valid and has the PTE_D bit asserted; since
3538 * this is an increase in permission, we may have been expected
3539 * to update the TLB lazily. Do so here and return, on the
3540 * fast path, to retry the instruction.
3542 tlb_update(pmap, va, *pte);
3547 if (pte_test(pte, PTE_RO)) {
3549 * This PTE is valid, not dirty, and read-only. Go take a
3550 * full fault (most likely to upgrade this part of the address
3551 * space to writeable).
3557 if (!pte_test(pte, PTE_MANAGED))
3558 panic("pmap_emulate_modified: unmanaged page");
3561 * PTE is valid, managed, not dirty, and not read-only. Set PTE_D
3562 * and eagerly update the local TLB, returning on the fast path.
3565 pte_set(pte, PTE_D);
3566 tlb_update(pmap, va, *pte);
3573 * Routine: pmap_kextract
3575 * Extract the physical page address associated
3579 pmap_kextract(vm_offset_t va)
3584 * First, the direct-mapped regions.
3586 #if defined(__mips_n64)
3587 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
3588 return (MIPS_XKPHYS_TO_PHYS(va));
3590 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
3591 return (MIPS_KSEG0_TO_PHYS(va));
3593 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
3594 return (MIPS_KSEG1_TO_PHYS(va));
3597 * User virtual addresses.
3599 if (va < VM_MAXUSER_ADDRESS) {
3602 if (curproc && curproc->p_vmspace) {
3603 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
3605 return (TLBLO_PTE_TO_PA(*ptep) |
3613 * Should be kernel virtual here, otherwise fail
3615 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
3616 #if defined(__mips_n64)
3617 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
3626 /* Is the kernel pmap initialized? */
3627 if (!CPU_EMPTY(&kernel_pmap->pm_active)) {
3628 /* It's inside the virtual address range */
3629 ptep = pmap_pte(kernel_pmap, va);
3631 return (TLBLO_PTE_TO_PA(*ptep) |
3638 panic("%s for unknown address space %p.", __func__, (void *)va);
3642 pmap_flush_pvcache(vm_page_t m)
3647 for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
3648 pv = TAILQ_NEXT(pv, pv_list)) {
3649 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
3655 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3659 * It appears that this function can only be called before any mappings
3660 * for the page are established. If this ever changes, this code will
3661 * need to walk the pv_list and make each of the existing mappings
3662 * uncacheable, being careful to sync caches and PTEs (and maybe
3663 * invalidate TLB?) for any current mapping it modifies.
3665 if (TAILQ_FIRST(&m->md.pv_list) != NULL)
3666 panic("Can't change memattr on page with existing mappings");
3668 /* Clean memattr portion of pv_flags */
3669 m->md.pv_flags &= ~PV_MEMATTR_MASK;
3670 m->md.pv_flags |= (ma << PV_MEMATTR_SHIFT) & PV_MEMATTR_MASK;
3673 static __inline void
3674 pmap_pte_attr(pt_entry_t *pte, vm_memattr_t ma)
3678 npte = *(u_int *)pte;
3679 npte &= ~PTE_C_MASK;
3685 pmap_change_attr(vm_offset_t sva, vm_size_t size, vm_memattr_t ma)
3687 pd_entry_t *pde, *pdpe;
3689 vm_offset_t ova, eva, va, va_next;
3700 for (; sva < eva; sva = va_next) {
3701 pdpe = pmap_segmap(pmap, sva);
3704 va_next = (sva + NBSEG) & ~SEGMASK;
3710 va_next = (sva + NBPDR) & ~PDRMASK;
3714 pde = pmap_pdpe_to_pde(pdpe, sva);
3719 * Limit our scan to either the end of the va represented
3720 * by the current page table page, or to the end of the
3721 * range being removed.
3727 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3729 if (!pte_test(pte, PTE_V) || pte_cache_bits(pte) == ma) {
3730 if (va != va_next) {
3731 pmap_invalidate_range(pmap, va, sva);
3739 pmap_pte_attr(pte, ma);
3742 pmap_invalidate_range(pmap, va, sva);
3746 /* Flush caches to be in the safe side */
3747 mips_dcache_wbinv_range(ova, size);
3752 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
3756 case VM_MEMATTR_UNCACHEABLE:
3757 case VM_MEMATTR_WRITE_BACK:
3759 case VM_MEMATTR_WRITE_COMBINING: