2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 3. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps
39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish
43 * Manages physical address maps.
45 * Since the information managed by this module is
46 * also stored by the logical address mapping module,
47 * this module may throw away valid virtual-to-physical
48 * mappings at almost any time. However, invalidations
49 * of virtual-to-physical mappings must be done as
52 * In order to cope with hardware architectures which
53 * make virtual-to-physical map invalidates expensive,
54 * this module may delay invalidate or reduced protection
55 * operations until such time as they are actually
56 * necessary. This module is given full information as
57 * to which processors are currently using which maps,
58 * and to when physical maps must be made correct.
61 #include <sys/cdefs.h>
62 __FBSDID("$FreeBSD$");
67 #include <sys/param.h>
68 #include <sys/systm.h>
71 #include <sys/msgbuf.h>
72 #include <sys/mutex.h>
75 #include <sys/rwlock.h>
76 #include <sys/sched.h>
78 #include <sys/sysctl.h>
79 #include <sys/vmmeter.h>
86 #include <vm/vm_param.h>
87 #include <vm/vm_kern.h>
88 #include <vm/vm_page.h>
89 #include <vm/vm_map.h>
90 #include <vm/vm_object.h>
91 #include <vm/vm_extern.h>
92 #include <vm/vm_pageout.h>
93 #include <vm/vm_pager.h>
96 #include <machine/cache.h>
97 #include <machine/md_var.h>
98 #include <machine/tlb.h>
102 #if !defined(DIAGNOSTIC)
103 #define PMAP_INLINE __inline
109 #define PV_STAT(x) do { x ; } while (0)
111 #define PV_STAT(x) do { } while (0)
115 * Get PDEs and PTEs for user/kernel address space
117 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
118 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1))
119 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1))
120 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT)
123 #define NUPDE (NPDEPG * NPDEPG)
124 #define NUSERPGTBLS (NUPDE + NPDEPG)
126 #define NUPDE (NPDEPG)
127 #define NUSERPGTBLS (NUPDE)
130 #define is_kernel_pmap(x) ((x) == kernel_pmap)
132 struct pmap kernel_pmap_store;
133 pd_entry_t *kernel_segmap;
135 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
136 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
139 unsigned pmap_max_asid; /* max ASID supported by the system */
141 #define PMAP_ASID_RESERVED 0
143 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
145 static void pmap_asid_alloc(pmap_t pmap);
147 static struct rwlock_padalign pvh_global_lock;
150 * Data for the pv entry allocation mechanism
152 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
153 static int pv_entry_count;
155 static void free_pv_chunk(struct pv_chunk *pc);
156 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
157 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
158 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
159 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
160 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
162 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req);
163 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
164 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
165 static void pmap_grow_direct_page(int req);
166 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
168 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
169 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
170 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
171 vm_offset_t va, vm_page_t m);
172 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
173 static void pmap_invalidate_all(pmap_t pmap);
174 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
175 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m);
177 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
178 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags);
179 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t);
180 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot);
182 static void pmap_invalidate_page_action(void *arg);
183 static void pmap_invalidate_range_action(void *arg);
184 static void pmap_update_page_action(void *arg);
188 * This structure is for high memory (memory above 512Meg in 32 bit) support.
189 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to
190 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc.
192 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To
193 * access a highmem physical address on a CPU, we map the physical address to
194 * the reserved virtual address for the CPU in the kernel pagetable. This is
195 * done with interrupts disabled(although a spinlock and sched_pin would be
198 struct local_sysmaps {
201 uint16_t valid1, valid2;
203 static struct local_sysmaps sysmap_lmem[MAXCPU];
206 pmap_alloc_lmem_map(void)
210 for (i = 0; i < MAXCPU; i++) {
211 sysmap_lmem[i].base = virtual_avail;
212 virtual_avail += PAGE_SIZE * 2;
213 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0;
217 static __inline vm_offset_t
218 pmap_lmem_map1(vm_paddr_t phys)
220 struct local_sysmaps *sysm;
221 pt_entry_t *pte, npte;
226 intr = intr_disable();
227 cpu = PCPU_GET(cpuid);
228 sysm = &sysmap_lmem[cpu];
229 sysm->saved_intr = intr;
231 npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
232 pte = pmap_pte(kernel_pmap, va);
238 static __inline vm_offset_t
239 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
241 struct local_sysmaps *sysm;
242 pt_entry_t *pte, npte;
243 vm_offset_t va1, va2;
247 intr = intr_disable();
248 cpu = PCPU_GET(cpuid);
249 sysm = &sysmap_lmem[cpu];
250 sysm->saved_intr = intr;
252 va2 = sysm->base + PAGE_SIZE;
253 npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
254 pte = pmap_pte(kernel_pmap, va1);
256 npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
257 pte = pmap_pte(kernel_pmap, va2);
265 pmap_lmem_unmap(void)
267 struct local_sysmaps *sysm;
271 cpu = PCPU_GET(cpuid);
272 sysm = &sysmap_lmem[cpu];
273 pte = pmap_pte(kernel_pmap, sysm->base);
275 tlb_invalidate_address(kernel_pmap, sysm->base);
278 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE);
280 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE);
283 intr_restore(sysm->saved_intr);
285 #else /* __mips_n64 */
288 pmap_alloc_lmem_map(void)
292 static __inline vm_offset_t
293 pmap_lmem_map1(vm_paddr_t phys)
299 static __inline vm_offset_t
300 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
306 static __inline vm_offset_t
307 pmap_lmem_unmap(void)
312 #endif /* !__mips_n64 */
315 pmap_pte_cache_bits(vm_paddr_t pa, vm_page_t m)
319 ma = pmap_page_get_memattr(m);
320 if (ma == VM_MEMATTR_WRITE_BACK && !is_cacheable_mem(pa))
321 ma = VM_MEMATTR_UNCACHEABLE;
324 #define PMAP_PTE_SET_CACHE_BITS(pte, ps, m) { \
325 pte &= ~PTE_C_MASK; \
326 pte |= pmap_pte_cache_bits(pa, m); \
330 * Page table entry lookup routines.
332 static __inline pd_entry_t *
333 pmap_segmap(pmap_t pmap, vm_offset_t va)
336 return (&pmap->pm_segtab[pmap_seg_index(va)]);
340 static __inline pd_entry_t *
341 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
345 pde = (pd_entry_t *)*pdpe;
346 return (&pde[pmap_pde_index(va)]);
349 static __inline pd_entry_t *
350 pmap_pde(pmap_t pmap, vm_offset_t va)
354 pdpe = pmap_segmap(pmap, va);
358 return (pmap_pdpe_to_pde(pdpe, va));
361 static __inline pd_entry_t *
362 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
369 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va)
372 return (pmap_segmap(pmap, va));
376 static __inline pt_entry_t *
377 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
381 pte = (pt_entry_t *)*pde;
382 return (&pte[pmap_pte_index(va)]);
386 pmap_pte(pmap_t pmap, vm_offset_t va)
390 pde = pmap_pde(pmap, va);
391 if (pde == NULL || *pde == NULL)
394 return (pmap_pde_to_pte(pde, va));
398 pmap_steal_memory(vm_size_t size)
400 vm_paddr_t bank_size, pa;
403 size = round_page(size);
404 bank_size = phys_avail[1] - phys_avail[0];
405 while (size > bank_size) {
408 for (i = 0; phys_avail[i + 2]; i += 2) {
409 phys_avail[i] = phys_avail[i + 2];
410 phys_avail[i + 1] = phys_avail[i + 3];
413 phys_avail[i + 1] = 0;
415 panic("pmap_steal_memory: out of memory");
416 bank_size = phys_avail[1] - phys_avail[0];
420 phys_avail[0] += size;
421 if (MIPS_DIRECT_MAPPABLE(pa) == 0)
422 panic("Out of memory below 512Meg?");
423 va = MIPS_PHYS_TO_DIRECT(pa);
424 bzero((caddr_t)va, size);
429 * Bootstrap the system enough to run with virtual memory. This
430 * assumes that the phys_avail array has been initialized.
433 pmap_create_kernel_pagetable(void)
445 * Allocate segment table for the kernel
447 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE);
450 * Allocate second level page tables for the kernel
453 npde = howmany(NKPT, NPDEPG);
454 pdaddr = pmap_steal_memory(PAGE_SIZE * npde);
457 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt);
460 * The R[4-7]?00 stores only one copy of the Global bit in the
461 * translation lookaside buffer for each 2 page entry. Thus invalid
462 * entrys must have the Global bit set so when Entry LO and Entry HI
463 * G bits are anded together they will produce a global bit to store
466 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++)
470 for (i = 0, npt = nkpt; npt > 0; i++) {
471 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE);
472 pde = (pd_entry_t *)kernel_segmap[i];
474 for (j = 0; j < NPDEPG && npt > 0; j++, npt--)
475 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE);
478 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++)
479 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE));
482 PMAP_LOCK_INIT(kernel_pmap);
483 kernel_pmap->pm_segtab = kernel_segmap;
484 CPU_FILL(&kernel_pmap->pm_active);
485 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
486 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
487 kernel_pmap->pm_asid[0].gen = 0;
488 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE;
495 int need_local_mappings = 0;
499 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
501 * Keep the memory aligned on page boundary.
503 phys_avail[i] = round_page(phys_avail[i]);
504 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
508 if (phys_avail[i - 2] > phys_avail[i]) {
511 ptemp[0] = phys_avail[i + 0];
512 ptemp[1] = phys_avail[i + 1];
514 phys_avail[i + 0] = phys_avail[i - 2];
515 phys_avail[i + 1] = phys_avail[i - 1];
517 phys_avail[i - 2] = ptemp[0];
518 phys_avail[i - 1] = ptemp[1];
524 * In 32 bit, we may have memory which cannot be mapped directly.
525 * This memory will need temporary mapping before it can be
528 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1))
529 need_local_mappings = 1;
532 * Copy the phys_avail[] array before we start stealing memory from it.
534 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
535 physmem_desc[i] = phys_avail[i];
536 physmem_desc[i + 1] = phys_avail[i + 1];
539 Maxmem = atop(phys_avail[i - 1]);
542 printf("Physical memory chunk(s):\n");
543 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
546 size = phys_avail[i + 1] - phys_avail[i];
547 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n",
548 (uintmax_t) phys_avail[i],
549 (uintmax_t) phys_avail[i + 1] - 1,
550 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE);
552 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem));
555 * Steal the message buffer from the beginning of memory.
557 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize);
558 msgbufinit(msgbufp, msgbufsize);
561 * Steal thread0 kstack.
563 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
565 virtual_avail = VM_MIN_KERNEL_ADDRESS;
566 virtual_end = VM_MAX_KERNEL_ADDRESS;
570 * Steal some virtual address space to map the pcpu area.
572 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2);
573 pcpup = (struct pcpu *)virtual_avail;
574 virtual_avail += PAGE_SIZE * 2;
577 * Initialize the wired TLB entry mapping the pcpu region for
578 * the BSP at 'pcpup'. Up until this point we were operating
579 * with the 'pcpup' for the BSP pointing to a virtual address
580 * in KSEG0 so there was no need for a TLB mapping.
582 mips_pcpu_tlb_init(PCPU_ADDR(0));
585 printf("pcpu is available at virtual address %p.\n", pcpup);
588 if (need_local_mappings)
589 pmap_alloc_lmem_map();
590 pmap_create_kernel_pagetable();
591 pmap_max_asid = VMNUM_PIDS;
596 * Initialize the global pv list lock.
598 rw_init(&pvh_global_lock, "pmap pv global");
602 * Initialize a vm_page's machine-dependent fields.
605 pmap_page_init(vm_page_t m)
608 TAILQ_INIT(&m->md.pv_list);
609 m->md.pv_flags = VM_MEMATTR_DEFAULT << PV_MEMATTR_SHIFT;
613 * Initialize the pmap module.
614 * Called by vm_init, to initialize any structures that the pmap
615 * system needs to map virtual memory.
622 /***************************************************
623 * Low level helper routines.....
624 ***************************************************/
628 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
630 int cpuid, cpu, self;
631 cpuset_t active_cpus;
634 if (is_kernel_pmap(pmap)) {
635 smp_rendezvous(NULL, fn, NULL, arg);
638 /* Force ASID update on inactive CPUs */
640 if (!CPU_ISSET(cpu, &pmap->pm_active))
641 pmap->pm_asid[cpu].gen = 0;
643 cpuid = PCPU_GET(cpuid);
645 * XXX: barrier/locking for active?
647 * Take a snapshot of active here, any further changes are ignored.
648 * tlb update/invalidate should be harmless on inactive CPUs
650 active_cpus = pmap->pm_active;
651 self = CPU_ISSET(cpuid, &active_cpus);
652 CPU_CLR(cpuid, &active_cpus);
653 /* Optimize for the case where this cpu is the only active one */
654 if (CPU_EMPTY(&active_cpus)) {
659 CPU_SET(cpuid, &active_cpus);
660 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg);
667 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
671 if (is_kernel_pmap(pmap)) {
675 cpuid = PCPU_GET(cpuid);
676 if (!CPU_ISSET(cpuid, &pmap->pm_active))
677 pmap->pm_asid[cpuid].gen = 0;
684 pmap_invalidate_all(pmap_t pmap)
687 pmap_call_on_active_cpus(pmap,
688 (void (*)(void *))tlb_invalidate_all_user, pmap);
691 struct pmap_invalidate_page_arg {
697 pmap_invalidate_page_action(void *arg)
699 struct pmap_invalidate_page_arg *p = arg;
701 tlb_invalidate_address(p->pmap, p->va);
705 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
707 struct pmap_invalidate_page_arg arg;
711 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg);
714 struct pmap_invalidate_range_arg {
721 pmap_invalidate_range_action(void *arg)
723 struct pmap_invalidate_range_arg *p = arg;
725 tlb_invalidate_range(p->pmap, p->sva, p->eva);
729 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
731 struct pmap_invalidate_range_arg arg;
736 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg);
739 struct pmap_update_page_arg {
746 pmap_update_page_action(void *arg)
748 struct pmap_update_page_arg *p = arg;
750 tlb_update(p->pmap, p->va, p->pte);
754 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte)
756 struct pmap_update_page_arg arg;
761 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg);
765 * Routine: pmap_extract
767 * Extract the physical page address associated
768 * with the given map/virtual_address pair.
771 pmap_extract(pmap_t pmap, vm_offset_t va)
774 vm_offset_t retval = 0;
777 pte = pmap_pte(pmap, va);
779 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK);
786 * Routine: pmap_extract_and_hold
788 * Atomically extract and hold the physical page
789 * with the given pmap and virtual address pair
790 * if that mapping permits the given protection.
793 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
795 pt_entry_t pte, *ptep;
796 vm_paddr_t pa, pte_pa;
803 ptep = pmap_pte(pmap, va);
806 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) ||
807 (prot & VM_PROT_WRITE) == 0)) {
808 pte_pa = TLBLO_PTE_TO_PA(pte);
809 if (vm_page_pa_tryrelock(pmap, pte_pa, &pa))
811 m = PHYS_TO_VM_PAGE(pte_pa);
820 /***************************************************
821 * Low level mapping routines.....
822 ***************************************************/
825 * add a wired page to the kva
828 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
831 pt_entry_t opte, npte;
834 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
837 pte = pmap_pte(kernel_pmap, va);
839 npte = TLBLO_PA_TO_PFN(pa) | PTE_C(ma) | PTE_D | PTE_V | PTE_G;
841 if (pte_test(&opte, PTE_V) && opte != npte)
842 pmap_update_page(kernel_pmap, va, npte);
846 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
849 KASSERT(is_cacheable_mem(pa),
850 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa));
852 pmap_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
856 * remove a page from the kernel pagetables
858 /* PMAP_INLINE */ void
859 pmap_kremove(vm_offset_t va)
864 * Write back all caches from the page being destroyed
866 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
868 pte = pmap_pte(kernel_pmap, va);
870 pmap_invalidate_page(kernel_pmap, va);
874 * Used to map a range of physical addresses into kernel
875 * virtual address space.
877 * The value passed in '*virt' is a suggested virtual address for
878 * the mapping. Architectures which can support a direct-mapped
879 * physical to virtual region can return the appropriate address
880 * within that region, leaving '*virt' unchanged. Other
881 * architectures should map the pages starting at '*virt' and
882 * update '*virt' with the first usable address after the mapped
885 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
888 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
892 if (MIPS_DIRECT_MAPPABLE(end - 1))
893 return (MIPS_PHYS_TO_DIRECT(start));
896 while (start < end) {
897 pmap_kenter(va, start);
906 * Add a list of wired pages to the kva
907 * this routine is only used for temporary
908 * kernel mappings that do not need to have
909 * page modification or references recorded.
910 * Note that old mappings are simply written
911 * over. The page *must* be wired.
914 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
917 vm_offset_t origva = va;
919 for (i = 0; i < count; i++) {
920 pmap_flush_pvcache(m[i]);
921 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i]));
925 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count);
929 * this routine jerks page mappings from the
930 * kernel -- it is meant only for temporary mappings.
933 pmap_qremove(vm_offset_t va, int count)
940 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count);
943 pte = pmap_pte(kernel_pmap, va);
946 } while (--count > 0);
947 pmap_invalidate_range(kernel_pmap, origva, va);
950 /***************************************************
951 * Page table page management routines.....
952 ***************************************************/
955 * Decrements a page table page's wire count, which is used to record the
956 * number of valid page table entries within the page. If the wire count
957 * drops to zero, then the page table page is unmapped. Returns TRUE if the
958 * page table page was unmapped and FALSE otherwise.
960 static PMAP_INLINE boolean_t
961 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
965 if (m->wire_count == 0) {
966 _pmap_unwire_ptp(pmap, va, m);
973 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
977 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
979 * unmap the page table page
982 if (m->pindex < NUPDE)
983 pde = pmap_pde(pmap, va);
985 pde = pmap_segmap(pmap, va);
987 pde = pmap_pde(pmap, va);
990 pmap->pm_stats.resident_count--;
993 if (m->pindex < NUPDE) {
998 * Recursively decrement next level pagetable refcount
1000 pdp = (pd_entry_t *)*pmap_segmap(pmap, va);
1001 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp));
1002 pmap_unwire_ptp(pmap, va, pdpg);
1007 * If the page is finally unwired, simply free it.
1009 vm_page_free_zero(m);
1010 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1014 * After removing a page table entry, this routine is used to
1015 * conditionally free the page, and manage the hold/wire counts.
1018 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1022 if (va >= VM_MAXUSER_ADDRESS)
1024 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0"));
1025 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde));
1026 return (pmap_unwire_ptp(pmap, va, mpte));
1030 pmap_pinit0(pmap_t pmap)
1034 PMAP_LOCK_INIT(pmap);
1035 pmap->pm_segtab = kernel_segmap;
1036 CPU_ZERO(&pmap->pm_active);
1037 for (i = 0; i < MAXCPU; i++) {
1038 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1039 pmap->pm_asid[i].gen = 0;
1041 PCPU_SET(curpmap, pmap);
1042 TAILQ_INIT(&pmap->pm_pvchunk);
1043 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1047 pmap_grow_direct_page(int req)
1053 if (!vm_page_reclaim_contig(req, 1, 0, MIPS_KSEG0_LARGEST_PHYS,
1060 pmap_alloc_direct_page(unsigned int index, int req)
1064 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED |
1069 if ((m->flags & PG_ZERO) == 0)
1077 * Initialize a preallocated and zeroed pmap structure,
1078 * such as one in a vmspace structure.
1081 pmap_pinit(pmap_t pmap)
1088 * allocate the page directory page
1090 req_class = VM_ALLOC_NORMAL;
1091 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, req_class)) ==
1093 pmap_grow_direct_page(req_class);
1095 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg));
1096 pmap->pm_segtab = (pd_entry_t *)ptdva;
1097 CPU_ZERO(&pmap->pm_active);
1098 for (i = 0; i < MAXCPU; i++) {
1099 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1100 pmap->pm_asid[i].gen = 0;
1102 TAILQ_INIT(&pmap->pm_pvchunk);
1103 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1109 * this routine is called if the page table page is not
1113 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags)
1120 * Find or fabricate a new pagetable page
1122 req_class = VM_ALLOC_NORMAL;
1123 if ((m = pmap_alloc_direct_page(ptepindex, req_class)) == NULL) {
1124 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1126 rw_wunlock(&pvh_global_lock);
1127 pmap_grow_direct_page(req_class);
1128 rw_wlock(&pvh_global_lock);
1133 * Indicate the need to retry. While waiting, the page
1134 * table page may have been allocated.
1140 * Map the pagetable page into the process address space, if it
1141 * isn't already there.
1143 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1146 if (ptepindex >= NUPDE) {
1147 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva;
1149 pd_entry_t *pdep, *pde;
1150 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT);
1151 int pdeindex = ptepindex & (NPDEPG - 1);
1154 pdep = &pmap->pm_segtab[segindex];
1155 if (*pdep == NULL) {
1156 /* recurse for allocating page dir */
1157 if (_pmap_allocpte(pmap, NUPDE + segindex,
1159 /* alloc failed, release current */
1161 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1162 vm_page_free_zero(m);
1166 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep));
1169 /* Next level entry */
1170 pde = (pd_entry_t *)*pdep;
1171 pde[pdeindex] = (pd_entry_t)pageva;
1174 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva;
1176 pmap->pm_stats.resident_count++;
1181 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1188 * Calculate pagetable page index
1190 ptepindex = pmap_pde_pindex(va);
1193 * Get the page directory entry
1195 pde = pmap_pde(pmap, va);
1198 * If the page table page is mapped, we just increment the hold
1199 * count, and activate it.
1201 if (pde != NULL && *pde != NULL) {
1202 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde));
1206 * Here if the pte page isn't mapped, or if it has been
1209 m = _pmap_allocpte(pmap, ptepindex, flags);
1210 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1217 /***************************************************
1218 * Pmap allocation/deallocation routines.
1219 ***************************************************/
1222 * Release any resources held by the given physical map.
1223 * Called when a pmap initialized by pmap_pinit is being released.
1224 * Should only be called if the map contains no valid mappings.
1227 pmap_release(pmap_t pmap)
1232 KASSERT(pmap->pm_stats.resident_count == 0,
1233 ("pmap_release: pmap resident count %ld != 0",
1234 pmap->pm_stats.resident_count));
1236 ptdva = (vm_offset_t)pmap->pm_segtab;
1237 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva));
1239 ptdpg->wire_count--;
1240 atomic_subtract_int(&vm_cnt.v_wire_count, 1);
1241 vm_page_free_zero(ptdpg);
1245 * grow the number of kernel page table entries, if needed
1248 pmap_growkernel(vm_offset_t addr)
1251 pd_entry_t *pde, *pdpe;
1255 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1256 req_class = VM_ALLOC_INTERRUPT;
1257 addr = roundup2(addr, NBSEG);
1258 if (addr - 1 >= kernel_map->max_offset)
1259 addr = kernel_map->max_offset;
1260 while (kernel_vm_end < addr) {
1261 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end);
1264 /* new intermediate page table entry */
1265 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1267 panic("pmap_growkernel: no memory to grow kernel");
1268 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1269 continue; /* try again */
1272 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
1274 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1275 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1276 kernel_vm_end = kernel_map->max_offset;
1283 * This index is bogus, but out of the way
1285 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1287 if (nkpg == NULL && vm_page_reclaim_contig(req_class, 1,
1288 0, MIPS_KSEG0_LARGEST_PHYS, PAGE_SIZE, 0))
1289 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1292 panic("pmap_growkernel: no memory to grow kernel");
1294 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1297 * The R[4-7]?00 stores only one copy of the Global bit in
1298 * the translation lookaside buffer for each 2 page entry.
1299 * Thus invalid entrys must have the Global bit set so when
1300 * Entry LO and Entry HI G bits are anded together they will
1301 * produce a global bit to store in the tlb.
1303 pte = (pt_entry_t *)*pde;
1304 for (i = 0; i < NPTEPG; i++)
1307 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1308 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1309 kernel_vm_end = kernel_map->max_offset;
1315 /***************************************************
1316 * page management routines.
1317 ***************************************************/
1319 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1321 CTASSERT(_NPCM == 3);
1322 CTASSERT(_NPCPV == 168);
1324 CTASSERT(_NPCM == 11);
1325 CTASSERT(_NPCPV == 336);
1328 static __inline struct pv_chunk *
1329 pv_to_chunk(pv_entry_t pv)
1332 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1335 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1338 #define PC_FREE0_1 0xfffffffffffffffful
1339 #define PC_FREE2 0x000000fffffffffful
1341 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
1342 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
1345 static const u_long pc_freemask[_NPCM] = {
1347 PC_FREE0_1, PC_FREE0_1, PC_FREE2
1349 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1350 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1351 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1352 PC_FREE0_9, PC_FREE10
1356 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1358 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1359 "Current number of pv entries");
1362 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1364 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1365 "Current number of pv entry chunks");
1366 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1367 "Current number of pv entry chunks allocated");
1368 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1369 "Current number of pv entry chunks frees");
1370 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1371 "Number of times tried to get a chunk page but failed.");
1373 static long pv_entry_frees, pv_entry_allocs;
1374 static int pv_entry_spare;
1376 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1377 "Current number of pv entry frees");
1378 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1379 "Current number of pv entry allocs");
1380 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1381 "Current number of spare pv entries");
1385 * We are in a serious low memory condition. Resort to
1386 * drastic measures to free some pages so we can allocate
1387 * another pv entry chunk.
1390 pmap_pv_reclaim(pmap_t locked_pmap)
1393 struct pv_chunk *pc;
1396 pt_entry_t *pte, oldpte;
1401 int bit, field, freed, idx;
1403 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1406 TAILQ_INIT(&newtail);
1407 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) {
1408 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1409 if (pmap != pc->pc_pmap) {
1411 pmap_invalidate_all(pmap);
1412 if (pmap != locked_pmap)
1416 /* Avoid deadlock and lock recursion. */
1417 if (pmap > locked_pmap)
1419 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
1421 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1427 * Destroy every non-wired, 4 KB page mapping in the chunk.
1430 for (field = 0; field < _NPCM; field++) {
1431 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1432 inuse != 0; inuse &= ~(1UL << bit)) {
1433 bit = ffsl(inuse) - 1;
1434 idx = field * sizeof(inuse) * NBBY + bit;
1435 pv = &pc->pc_pventry[idx];
1437 pde = pmap_pde(pmap, va);
1438 KASSERT(pde != NULL && *pde != 0,
1439 ("pmap_pv_reclaim: pde"));
1440 pte = pmap_pde_to_pte(pde, va);
1442 if (pte_test(&oldpte, PTE_W))
1444 if (is_kernel_pmap(pmap))
1448 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte));
1449 if (pte_test(&oldpte, PTE_D))
1451 if (m->md.pv_flags & PV_TABLE_REF)
1452 vm_page_aflag_set(m, PGA_REFERENCED);
1453 m->md.pv_flags &= ~PV_TABLE_REF;
1454 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1455 if (TAILQ_EMPTY(&m->md.pv_list))
1456 vm_page_aflag_clear(m, PGA_WRITEABLE);
1457 pc->pc_map[field] |= 1UL << bit;
1458 pmap_unuse_pt(pmap, va, *pde);
1463 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1466 /* Every freed mapping is for a 4 KB page. */
1467 pmap->pm_stats.resident_count -= freed;
1468 PV_STAT(pv_entry_frees += freed);
1469 PV_STAT(pv_entry_spare += freed);
1470 pv_entry_count -= freed;
1471 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1472 for (field = 0; field < _NPCM; field++)
1473 if (pc->pc_map[field] != pc_freemask[field]) {
1474 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1476 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1479 * One freed pv entry in locked_pmap is
1482 if (pmap == locked_pmap)
1486 if (field == _NPCM) {
1487 PV_STAT(pv_entry_spare -= _NPCPV);
1488 PV_STAT(pc_chunk_count--);
1489 PV_STAT(pc_chunk_frees++);
1490 /* Entire chunk is free; return it. */
1491 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(
1493 dump_drop_page(m_pc->phys_addr);
1498 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
1500 pmap_invalidate_all(pmap);
1501 if (pmap != locked_pmap)
1508 * free the pv_entry back to the free list
1511 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1513 struct pv_chunk *pc;
1514 int bit, field, idx;
1516 rw_assert(&pvh_global_lock, RA_WLOCKED);
1517 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1518 PV_STAT(pv_entry_frees++);
1519 PV_STAT(pv_entry_spare++);
1521 pc = pv_to_chunk(pv);
1522 idx = pv - &pc->pc_pventry[0];
1523 field = idx / (sizeof(u_long) * NBBY);
1524 bit = idx % (sizeof(u_long) * NBBY);
1525 pc->pc_map[field] |= 1ul << bit;
1526 for (idx = 0; idx < _NPCM; idx++)
1527 if (pc->pc_map[idx] != pc_freemask[idx]) {
1529 * 98% of the time, pc is already at the head of the
1530 * list. If it isn't already, move it to the head.
1532 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
1534 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1535 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1540 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1545 free_pv_chunk(struct pv_chunk *pc)
1549 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1550 PV_STAT(pv_entry_spare -= _NPCPV);
1551 PV_STAT(pc_chunk_count--);
1552 PV_STAT(pc_chunk_frees++);
1553 /* entire chunk is free, return it */
1554 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc));
1555 dump_drop_page(m->phys_addr);
1556 vm_page_unwire(m, PQ_NONE);
1561 * get a new pv_entry, allocating a block from the system
1565 get_pv_entry(pmap_t pmap, boolean_t try)
1567 struct pv_chunk *pc;
1570 int bit, field, idx;
1572 rw_assert(&pvh_global_lock, RA_WLOCKED);
1573 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1574 PV_STAT(pv_entry_allocs++);
1577 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1579 for (field = 0; field < _NPCM; field++) {
1580 if (pc->pc_map[field]) {
1581 bit = ffsl(pc->pc_map[field]) - 1;
1585 if (field < _NPCM) {
1586 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
1587 pv = &pc->pc_pventry[idx];
1588 pc->pc_map[field] &= ~(1ul << bit);
1589 /* If this was the last item, move it to tail */
1590 for (field = 0; field < _NPCM; field++)
1591 if (pc->pc_map[field] != 0) {
1592 PV_STAT(pv_entry_spare--);
1593 return (pv); /* not full, return */
1595 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1596 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
1597 PV_STAT(pv_entry_spare--);
1601 /* No free items, allocate another chunk */
1602 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL |
1607 PV_STAT(pc_chunk_tryfail++);
1610 m = pmap_pv_reclaim(pmap);
1614 PV_STAT(pc_chunk_count++);
1615 PV_STAT(pc_chunk_allocs++);
1616 dump_add_page(m->phys_addr);
1617 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1619 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
1620 for (field = 1; field < _NPCM; field++)
1621 pc->pc_map[field] = pc_freemask[field];
1622 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1623 pv = &pc->pc_pventry[0];
1624 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1625 PV_STAT(pv_entry_spare += _NPCPV - 1);
1630 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1634 rw_assert(&pvh_global_lock, RA_WLOCKED);
1635 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
1636 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1637 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
1645 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1649 pv = pmap_pvh_remove(pvh, pmap, va);
1650 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx",
1651 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)),
1653 free_pv_entry(pmap, pv);
1657 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
1660 rw_assert(&pvh_global_lock, RA_WLOCKED);
1661 pmap_pvh_free(&m->md, pmap, va);
1662 if (TAILQ_EMPTY(&m->md.pv_list))
1663 vm_page_aflag_clear(m, PGA_WRITEABLE);
1667 * Conditionally create a pv entry.
1670 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va,
1675 rw_assert(&pvh_global_lock, RA_WLOCKED);
1676 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1677 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
1679 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
1686 * pmap_remove_pte: do the things to unmap a page in a process
1689 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
1696 rw_assert(&pvh_global_lock, RA_WLOCKED);
1697 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1700 * Write back all cache lines from the page being unmapped.
1702 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
1705 if (is_kernel_pmap(pmap))
1710 if (pte_test(&oldpte, PTE_W))
1711 pmap->pm_stats.wired_count -= 1;
1713 pmap->pm_stats.resident_count -= 1;
1715 if (pte_test(&oldpte, PTE_MANAGED)) {
1716 pa = TLBLO_PTE_TO_PA(oldpte);
1717 m = PHYS_TO_VM_PAGE(pa);
1718 if (pte_test(&oldpte, PTE_D)) {
1719 KASSERT(!pte_test(&oldpte, PTE_RO),
1720 ("%s: modified page not writable: va: %p, pte: %#jx",
1721 __func__, (void *)va, (uintmax_t)oldpte));
1724 if (m->md.pv_flags & PV_TABLE_REF)
1725 vm_page_aflag_set(m, PGA_REFERENCED);
1726 m->md.pv_flags &= ~PV_TABLE_REF;
1728 pmap_remove_entry(pmap, m, va);
1730 return (pmap_unuse_pt(pmap, va, pde));
1734 * Remove a single page from a process address space
1737 pmap_remove_page(struct pmap *pmap, vm_offset_t va)
1742 rw_assert(&pvh_global_lock, RA_WLOCKED);
1743 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1744 pde = pmap_pde(pmap, va);
1745 if (pde == NULL || *pde == 0)
1747 ptq = pmap_pde_to_pte(pde, va);
1750 * If there is no pte for this address, just skip it!
1752 if (!pte_test(ptq, PTE_V))
1755 (void)pmap_remove_pte(pmap, ptq, va, *pde);
1756 pmap_invalidate_page(pmap, va);
1760 * Remove the given range of addresses from the specified map.
1762 * It is assumed that the start and end are properly
1763 * rounded to the page size.
1766 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1768 pd_entry_t *pde, *pdpe;
1770 vm_offset_t va, va_next;
1773 * Perform an unsynchronized read. This is, however, safe.
1775 if (pmap->pm_stats.resident_count == 0)
1778 rw_wlock(&pvh_global_lock);
1782 * special handling of removing one page. a very common operation
1783 * and easy to short circuit some code.
1785 if ((sva + PAGE_SIZE) == eva) {
1786 pmap_remove_page(pmap, sva);
1789 for (; sva < eva; sva = va_next) {
1790 pdpe = pmap_segmap(pmap, sva);
1793 va_next = (sva + NBSEG) & ~SEGMASK;
1799 va_next = (sva + NBPDR) & ~PDRMASK;
1803 pde = pmap_pdpe_to_pde(pdpe, sva);
1808 * Limit our scan to either the end of the va represented
1809 * by the current page table page, or to the end of the
1810 * range being removed.
1816 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1818 if (!pte_test(pte, PTE_V)) {
1819 if (va != va_next) {
1820 pmap_invalidate_range(pmap, va, sva);
1827 if (pmap_remove_pte(pmap, pte, sva, *pde)) {
1833 pmap_invalidate_range(pmap, va, sva);
1836 rw_wunlock(&pvh_global_lock);
1841 * Routine: pmap_remove_all
1843 * Removes this physical page from
1844 * all physical maps in which it resides.
1845 * Reflects back modify bits to the pager.
1848 * Original versions of this routine were very
1849 * inefficient because they iteratively called
1850 * pmap_remove (slow...)
1854 pmap_remove_all(vm_page_t m)
1859 pt_entry_t *pte, tpte;
1861 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1862 ("pmap_remove_all: page %p is not managed", m));
1863 rw_wlock(&pvh_global_lock);
1865 if (m->md.pv_flags & PV_TABLE_REF)
1866 vm_page_aflag_set(m, PGA_REFERENCED);
1868 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
1873 * If it's last mapping writeback all caches from
1874 * the page being destroyed
1876 if (TAILQ_NEXT(pv, pv_list) == NULL)
1877 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
1879 pmap->pm_stats.resident_count--;
1881 pde = pmap_pde(pmap, pv->pv_va);
1882 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde"));
1883 pte = pmap_pde_to_pte(pde, pv->pv_va);
1886 if (is_kernel_pmap(pmap))
1891 if (pte_test(&tpte, PTE_W))
1892 pmap->pm_stats.wired_count--;
1895 * Update the vm_page_t clean and reference bits.
1897 if (pte_test(&tpte, PTE_D)) {
1898 KASSERT(!pte_test(&tpte, PTE_RO),
1899 ("%s: modified page not writable: va: %p, pte: %#jx",
1900 __func__, (void *)pv->pv_va, (uintmax_t)tpte));
1903 pmap_invalidate_page(pmap, pv->pv_va);
1905 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1906 pmap_unuse_pt(pmap, pv->pv_va, *pde);
1907 free_pv_entry(pmap, pv);
1911 vm_page_aflag_clear(m, PGA_WRITEABLE);
1912 m->md.pv_flags &= ~PV_TABLE_REF;
1913 rw_wunlock(&pvh_global_lock);
1917 * Set the physical protection on the
1918 * specified range of this map as requested.
1921 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1923 pt_entry_t pbits, *pte;
1924 pd_entry_t *pde, *pdpe;
1925 vm_offset_t va, va_next;
1929 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1930 pmap_remove(pmap, sva, eva);
1933 if (prot & VM_PROT_WRITE)
1937 for (; sva < eva; sva = va_next) {
1938 pdpe = pmap_segmap(pmap, sva);
1941 va_next = (sva + NBSEG) & ~SEGMASK;
1947 va_next = (sva + NBPDR) & ~PDRMASK;
1951 pde = pmap_pdpe_to_pde(pdpe, sva);
1956 * Limit our scan to either the end of the va represented
1957 * by the current page table page, or to the end of the
1958 * range being write protected.
1964 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1967 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits,
1969 if (va != va_next) {
1970 pmap_invalidate_range(pmap, va, sva);
1975 pte_set(&pbits, PTE_RO);
1976 if (pte_test(&pbits, PTE_D)) {
1977 pte_clear(&pbits, PTE_D);
1978 if (pte_test(&pbits, PTE_MANAGED)) {
1979 pa = TLBLO_PTE_TO_PA(pbits);
1980 m = PHYS_TO_VM_PAGE(pa);
1987 * Unless PTE_D is set, any TLB entries
1988 * mapping "sva" don't allow write access, so
1989 * they needn't be invalidated.
1991 if (va != va_next) {
1992 pmap_invalidate_range(pmap, va, sva);
1999 pmap_invalidate_range(pmap, va, sva);
2005 * Insert the given physical page (p) at
2006 * the specified virtual address (v) in the
2007 * target physical map with the protection requested.
2009 * If specified, the page will be wired down, meaning
2010 * that the related pte can not be reclaimed.
2012 * NB: This is the only routine which MAY NOT lazy-evaluate
2013 * or lose information. That is, this routine must actually
2014 * insert this page into the given map NOW.
2017 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2018 u_int flags, int8_t psind __unused)
2022 pt_entry_t origpte, newpte;
2027 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2028 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
2029 va >= kmi.clean_eva,
2030 ("pmap_enter: managed mapping within the clean submap"));
2031 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2032 VM_OBJECT_ASSERT_LOCKED(m->object);
2033 pa = VM_PAGE_TO_PHYS(m);
2034 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot);
2035 if ((flags & PMAP_ENTER_WIRED) != 0)
2037 if (is_kernel_pmap(pmap))
2039 PMAP_PTE_SET_CACHE_BITS(newpte, pa, m);
2043 rw_wlock(&pvh_global_lock);
2047 * In the case that a page table page is not resident, we are
2050 if (va < VM_MAXUSER_ADDRESS) {
2051 mpte = pmap_allocpte(pmap, va, flags);
2053 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
2054 ("pmap_allocpte failed with sleep allowed"));
2055 rw_wunlock(&pvh_global_lock);
2057 return (KERN_RESOURCE_SHORTAGE);
2060 pte = pmap_pte(pmap, va);
2063 * Page Directory table entry not valid, we need a new PT page
2066 panic("pmap_enter: invalid page directory, pdir=%p, va=%p",
2067 (void *)pmap->pm_segtab, (void *)va);
2071 opa = TLBLO_PTE_TO_PA(origpte);
2074 * Mapping has not changed, must be protection or wiring change.
2076 if (pte_test(&origpte, PTE_V) && opa == pa) {
2078 * Wiring change, just update stats. We don't worry about
2079 * wiring PT pages as they remain resident as long as there
2080 * are valid mappings in them. Hence, if a user page is
2081 * wired, the PT page will be also.
2083 if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W))
2084 pmap->pm_stats.wired_count++;
2085 else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte,
2087 pmap->pm_stats.wired_count--;
2089 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO),
2090 ("%s: modified page not writable: va: %p, pte: %#jx",
2091 __func__, (void *)va, (uintmax_t)origpte));
2094 * Remove extra pte reference
2099 if (pte_test(&origpte, PTE_MANAGED)) {
2100 m->md.pv_flags |= PV_TABLE_REF;
2102 newpte |= PTE_MANAGED;
2103 if (!pte_test(&newpte, PTE_RO))
2104 vm_page_aflag_set(m, PGA_WRITEABLE);
2112 * Mapping has changed, invalidate old range and fall through to
2113 * handle validating new mapping.
2116 if (pte_test(&origpte, PTE_W))
2117 pmap->pm_stats.wired_count--;
2119 if (pte_test(&origpte, PTE_MANAGED)) {
2120 om = PHYS_TO_VM_PAGE(opa);
2121 pv = pmap_pvh_remove(&om->md, pmap, va);
2125 KASSERT(mpte->wire_count > 0,
2126 ("pmap_enter: missing reference to page table page,"
2127 " va: %p", (void *)va));
2130 pmap->pm_stats.resident_count++;
2133 * Enter on the PV list if part of our managed memory.
2135 if ((m->oflags & VPO_UNMANAGED) == 0) {
2136 m->md.pv_flags |= PV_TABLE_REF;
2138 pv = get_pv_entry(pmap, FALSE);
2140 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2141 newpte |= PTE_MANAGED;
2142 if (!pte_test(&newpte, PTE_RO))
2143 vm_page_aflag_set(m, PGA_WRITEABLE);
2144 } else if (pv != NULL)
2145 free_pv_entry(pmap, pv);
2148 * Increment counters
2150 if (pte_test(&newpte, PTE_W))
2151 pmap->pm_stats.wired_count++;
2156 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
2160 * if the mapping or permission bits are different, we need to
2163 if (origpte != newpte) {
2165 if (pte_test(&origpte, PTE_V)) {
2166 if (pte_test(&origpte, PTE_MANAGED) && opa != pa) {
2167 if (om->md.pv_flags & PV_TABLE_REF)
2168 vm_page_aflag_set(om, PGA_REFERENCED);
2169 om->md.pv_flags &= ~PV_TABLE_REF;
2171 if (pte_test(&origpte, PTE_D)) {
2172 KASSERT(!pte_test(&origpte, PTE_RO),
2173 ("pmap_enter: modified page not writable:"
2174 " va: %p, pte: %#jx", (void *)va, (uintmax_t)origpte));
2175 if (pte_test(&origpte, PTE_MANAGED))
2178 if (pte_test(&origpte, PTE_MANAGED) &&
2179 TAILQ_EMPTY(&om->md.pv_list))
2180 vm_page_aflag_clear(om, PGA_WRITEABLE);
2181 pmap_update_page(pmap, va, newpte);
2186 * Sync I & D caches for executable pages. Do this only if the
2187 * target pmap belongs to the current process. Otherwise, an
2188 * unresolvable TLB miss may occur.
2190 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
2191 (prot & VM_PROT_EXECUTE)) {
2192 mips_icache_sync_range(va, PAGE_SIZE);
2193 mips_dcache_wbinv_range(va, PAGE_SIZE);
2195 rw_wunlock(&pvh_global_lock);
2197 return (KERN_SUCCESS);
2201 * this code makes some *MAJOR* assumptions:
2202 * 1. Current pmap & pmap exists.
2205 * 4. No page table pages.
2206 * but is *MUCH* faster than pmap_enter...
2210 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2213 rw_wlock(&pvh_global_lock);
2215 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
2216 rw_wunlock(&pvh_global_lock);
2221 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2222 vm_prot_t prot, vm_page_t mpte)
2224 pt_entry_t *pte, npte;
2227 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2228 (m->oflags & VPO_UNMANAGED) != 0,
2229 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2230 rw_assert(&pvh_global_lock, RA_WLOCKED);
2231 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2234 * In the case that a page table page is not resident, we are
2237 if (va < VM_MAXUSER_ADDRESS) {
2242 * Calculate pagetable page index
2244 ptepindex = pmap_pde_pindex(va);
2245 if (mpte && (mpte->pindex == ptepindex)) {
2249 * Get the page directory entry
2251 pde = pmap_pde(pmap, va);
2254 * If the page table page is mapped, we just
2255 * increment the hold count, and activate it.
2257 if (pde && *pde != 0) {
2258 mpte = PHYS_TO_VM_PAGE(
2259 MIPS_DIRECT_TO_PHYS(*pde));
2262 mpte = _pmap_allocpte(pmap, ptepindex,
2263 PMAP_ENTER_NOSLEEP);
2272 pte = pmap_pte(pmap, va);
2273 if (pte_test(pte, PTE_V)) {
2282 * Enter on the PV list if part of our managed memory.
2284 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2285 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) {
2287 pmap_unwire_ptp(pmap, va, mpte);
2294 * Increment counters
2296 pmap->pm_stats.resident_count++;
2298 pa = VM_PAGE_TO_PHYS(m);
2301 * Now validate mapping with RO protection
2303 npte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V;
2304 if ((m->oflags & VPO_UNMANAGED) == 0)
2305 npte |= PTE_MANAGED;
2307 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2309 if (is_kernel_pmap(pmap))
2310 *pte = npte | PTE_G;
2314 * Sync I & D caches. Do this only if the target pmap
2315 * belongs to the current process. Otherwise, an
2316 * unresolvable TLB miss may occur. */
2317 if (pmap == &curproc->p_vmspace->vm_pmap) {
2319 mips_icache_sync_range(va, PAGE_SIZE);
2320 mips_dcache_wbinv_range(va, PAGE_SIZE);
2327 * Make a temporary mapping for a physical address. This is only intended
2328 * to be used for panic dumps.
2330 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2333 pmap_kenter_temporary(vm_paddr_t pa, int i)
2338 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
2341 if (MIPS_DIRECT_MAPPABLE(pa)) {
2342 va = MIPS_PHYS_TO_DIRECT(pa);
2344 #ifndef __mips_n64 /* XXX : to be converted to new style */
2347 struct local_sysmaps *sysm;
2348 pt_entry_t *pte, npte;
2350 /* If this is used other than for dumps, we may need to leave
2351 * interrupts disasbled on return. If crash dumps don't work when
2352 * we get to this point, we might want to consider this (leaving things
2353 * disabled as a starting point ;-)
2355 intr = intr_disable();
2356 cpu = PCPU_GET(cpuid);
2357 sysm = &sysmap_lmem[cpu];
2358 /* Since this is for the debugger, no locks or any other fun */
2359 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
2361 pte = pmap_pte(kernel_pmap, sysm->base);
2364 pmap_update_page(kernel_pmap, sysm->base, npte);
2369 return ((void *)va);
2373 pmap_kenter_temporary_free(vm_paddr_t pa)
2375 #ifndef __mips_n64 /* XXX : to be converted to new style */
2378 struct local_sysmaps *sysm;
2381 if (MIPS_DIRECT_MAPPABLE(pa)) {
2382 /* nothing to do for this case */
2385 #ifndef __mips_n64 /* XXX : to be converted to new style */
2386 cpu = PCPU_GET(cpuid);
2387 sysm = &sysmap_lmem[cpu];
2391 intr = intr_disable();
2392 pte = pmap_pte(kernel_pmap, sysm->base);
2394 pmap_invalidate_page(kernel_pmap, sysm->base);
2402 * Maps a sequence of resident pages belonging to the same object.
2403 * The sequence begins with the given page m_start. This page is
2404 * mapped at the given virtual address start. Each subsequent page is
2405 * mapped at a virtual address that is offset from start by the same
2406 * amount as the page is offset from m_start within the object. The
2407 * last page in the sequence is the page with the largest offset from
2408 * m_start that can be mapped at a virtual address less than the given
2409 * virtual address end. Not every virtual page between start and end
2410 * is mapped; only those for which a resident page exists with the
2411 * corresponding offset from m_start are mapped.
2414 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2415 vm_page_t m_start, vm_prot_t prot)
2418 vm_pindex_t diff, psize;
2420 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2422 psize = atop(end - start);
2425 rw_wlock(&pvh_global_lock);
2427 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2428 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m,
2430 m = TAILQ_NEXT(m, listq);
2432 rw_wunlock(&pvh_global_lock);
2437 * pmap_object_init_pt preloads the ptes for a given object
2438 * into the specified pmap. This eliminates the blast of soft
2439 * faults on process startup and immediately after an mmap.
2442 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
2443 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2445 VM_OBJECT_ASSERT_WLOCKED(object);
2446 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2447 ("pmap_object_init_pt: non-device object"));
2451 * Clear the wired attribute from the mappings for the specified range of
2452 * addresses in the given pmap. Every valid mapping within that range
2453 * must have the wired attribute set. In contrast, invalid mappings
2454 * cannot have the wired attribute set, so they are ignored.
2456 * The wired attribute of the page table entry is not a hardware feature,
2457 * so there is no need to invalidate any TLB entries.
2460 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2462 pd_entry_t *pde, *pdpe;
2464 vm_offset_t va_next;
2467 for (; sva < eva; sva = va_next) {
2468 pdpe = pmap_segmap(pmap, sva);
2470 if (*pdpe == NULL) {
2471 va_next = (sva + NBSEG) & ~SEGMASK;
2477 va_next = (sva + NBPDR) & ~PDRMASK;
2480 pde = pmap_pdpe_to_pde(pdpe, sva);
2485 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2487 if (!pte_test(pte, PTE_V))
2489 if (!pte_test(pte, PTE_W))
2490 panic("pmap_unwire: pte %#jx is missing PG_W",
2492 pte_clear(pte, PTE_W);
2493 pmap->pm_stats.wired_count--;
2500 * Copy the range specified by src_addr/len
2501 * from the source map to the range dst_addr/len
2502 * in the destination map.
2504 * This routine is only advisory and need not do anything.
2508 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2509 vm_size_t len, vm_offset_t src_addr)
2514 * pmap_zero_page zeros the specified hardware page by mapping
2515 * the page into KVM and using bzero to clear its contents.
2517 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2520 pmap_zero_page(vm_page_t m)
2523 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2525 if (MIPS_DIRECT_MAPPABLE(phys)) {
2526 va = MIPS_PHYS_TO_DIRECT(phys);
2527 bzero((caddr_t)va, PAGE_SIZE);
2528 mips_dcache_wbinv_range(va, PAGE_SIZE);
2530 va = pmap_lmem_map1(phys);
2531 bzero((caddr_t)va, PAGE_SIZE);
2532 mips_dcache_wbinv_range(va, PAGE_SIZE);
2538 * pmap_zero_page_area zeros the specified hardware page by mapping
2539 * the page into KVM and using bzero to clear its contents.
2541 * off and size may not cover an area beyond a single hardware page.
2544 pmap_zero_page_area(vm_page_t m, int off, int size)
2547 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2549 if (MIPS_DIRECT_MAPPABLE(phys)) {
2550 va = MIPS_PHYS_TO_DIRECT(phys);
2551 bzero((char *)(caddr_t)va + off, size);
2552 mips_dcache_wbinv_range(va + off, size);
2554 va = pmap_lmem_map1(phys);
2555 bzero((char *)va + off, size);
2556 mips_dcache_wbinv_range(va + off, size);
2562 * pmap_copy_page copies the specified (machine independent)
2563 * page by mapping the page into virtual memory and using
2564 * bcopy to copy the page, one machine dependent page at a
2567 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2570 pmap_copy_page(vm_page_t src, vm_page_t dst)
2572 vm_offset_t va_src, va_dst;
2573 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src);
2574 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst);
2576 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) {
2577 /* easy case, all can be accessed via KSEG0 */
2579 * Flush all caches for VA that are mapped to this page
2580 * to make sure that data in SDRAM is up to date
2582 pmap_flush_pvcache(src);
2583 mips_dcache_wbinv_range_index(
2584 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE);
2585 va_src = MIPS_PHYS_TO_DIRECT(phys_src);
2586 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst);
2587 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
2588 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2590 va_src = pmap_lmem_map2(phys_src, phys_dst);
2591 va_dst = va_src + PAGE_SIZE;
2592 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE);
2593 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2598 int unmapped_buf_allowed;
2601 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2602 vm_offset_t b_offset, int xfersize)
2606 vm_offset_t a_pg_offset, b_pg_offset;
2607 vm_paddr_t a_phys, b_phys;
2610 while (xfersize > 0) {
2611 a_pg_offset = a_offset & PAGE_MASK;
2612 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2613 a_m = ma[a_offset >> PAGE_SHIFT];
2614 a_phys = VM_PAGE_TO_PHYS(a_m);
2615 b_pg_offset = b_offset & PAGE_MASK;
2616 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2617 b_m = mb[b_offset >> PAGE_SHIFT];
2618 b_phys = VM_PAGE_TO_PHYS(b_m);
2619 if (MIPS_DIRECT_MAPPABLE(a_phys) &&
2620 MIPS_DIRECT_MAPPABLE(b_phys)) {
2621 pmap_flush_pvcache(a_m);
2622 mips_dcache_wbinv_range_index(
2623 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE);
2624 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) +
2626 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) +
2628 bcopy(a_cp, b_cp, cnt);
2629 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2631 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys);
2632 b_cp = (char *)a_cp + PAGE_SIZE;
2633 a_cp += a_pg_offset;
2634 b_cp += b_pg_offset;
2635 bcopy(a_cp, b_cp, cnt);
2636 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2646 pmap_quick_enter_page(vm_page_t m)
2648 #if defined(__mips_n64)
2649 return MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
2652 struct local_sysmaps *sysm;
2653 pt_entry_t *pte, npte;
2655 pa = VM_PAGE_TO_PHYS(m);
2657 if (MIPS_DIRECT_MAPPABLE(pa)) {
2658 if (pmap_page_get_memattr(m) != VM_MEMATTR_WRITE_BACK)
2659 return (MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
2661 return (MIPS_PHYS_TO_DIRECT(pa));
2664 sysm = &sysmap_lmem[PCPU_GET(cpuid)];
2666 KASSERT(sysm->valid1 == 0, ("pmap_quick_enter_page: PTE busy"));
2668 pte = pmap_pte(kernel_pmap, sysm->base);
2669 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G;
2670 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2674 return (sysm->base);
2679 pmap_quick_remove_page(vm_offset_t addr)
2681 mips_dcache_wbinv_range(addr, PAGE_SIZE);
2683 #if !defined(__mips_n64)
2684 struct local_sysmaps *sysm;
2687 if (addr >= MIPS_KSEG0_START && addr < MIPS_KSEG0_END)
2690 sysm = &sysmap_lmem[PCPU_GET(cpuid)];
2692 KASSERT(sysm->valid1 != 0,
2693 ("pmap_quick_remove_page: PTE not in use"));
2694 KASSERT(sysm->base == addr,
2695 ("pmap_quick_remove_page: invalid address"));
2697 pte = pmap_pte(kernel_pmap, addr);
2699 tlb_invalidate_address(kernel_pmap, addr);
2706 * Returns true if the pmap's pv is one of the first
2707 * 16 pvs linked to from this page. This count may
2708 * be changed upwards or downwards in the future; it
2709 * is only necessary that true be returned for a small
2710 * subset of pmaps for proper page aging.
2713 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2719 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2720 ("pmap_page_exists_quick: page %p is not managed", m));
2722 rw_wlock(&pvh_global_lock);
2723 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2724 if (PV_PMAP(pv) == pmap) {
2732 rw_wunlock(&pvh_global_lock);
2737 * Remove all pages from specified address space
2738 * this aids process exit speeds. Also, this code
2739 * is special cased for current process only, but
2740 * can have the more generic (and slightly slower)
2741 * mode enabled. This is much faster than pmap_remove
2742 * in the case of running down an entire address space.
2745 pmap_remove_pages(pmap_t pmap)
2748 pt_entry_t *pte, tpte;
2751 struct pv_chunk *pc, *npc;
2752 u_long inuse, bitmask;
2753 int allfree, bit, field, idx;
2755 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
2756 printf("warning: pmap_remove_pages called with non-current pmap\n");
2759 rw_wlock(&pvh_global_lock);
2761 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2763 for (field = 0; field < _NPCM; field++) {
2764 inuse = ~pc->pc_map[field] & pc_freemask[field];
2765 while (inuse != 0) {
2766 bit = ffsl(inuse) - 1;
2767 bitmask = 1UL << bit;
2768 idx = field * sizeof(inuse) * NBBY + bit;
2769 pv = &pc->pc_pventry[idx];
2772 pde = pmap_pde(pmap, pv->pv_va);
2773 KASSERT(pde != NULL && *pde != 0,
2774 ("pmap_remove_pages: pde"));
2775 pte = pmap_pde_to_pte(pde, pv->pv_va);
2776 if (!pte_test(pte, PTE_V))
2777 panic("pmap_remove_pages: bad pte");
2781 * We cannot remove wired pages from a process' mapping at this time
2783 if (pte_test(&tpte, PTE_W)) {
2787 *pte = is_kernel_pmap(pmap) ? PTE_G : 0;
2789 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte));
2791 ("pmap_remove_pages: bad tpte %#jx",
2795 * Update the vm_page_t clean and reference bits.
2797 if (pte_test(&tpte, PTE_D))
2801 PV_STAT(pv_entry_frees++);
2802 PV_STAT(pv_entry_spare++);
2804 pc->pc_map[field] |= bitmask;
2805 pmap->pm_stats.resident_count--;
2806 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2807 if (TAILQ_EMPTY(&m->md.pv_list))
2808 vm_page_aflag_clear(m, PGA_WRITEABLE);
2809 pmap_unuse_pt(pmap, pv->pv_va, *pde);
2813 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2817 pmap_invalidate_all(pmap);
2819 rw_wunlock(&pvh_global_lock);
2823 * pmap_testbit tests bits in pte's
2826 pmap_testbit(vm_page_t m, int bit)
2831 boolean_t rv = FALSE;
2833 if (m->oflags & VPO_UNMANAGED)
2836 rw_assert(&pvh_global_lock, RA_WLOCKED);
2837 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2840 pte = pmap_pte(pmap, pv->pv_va);
2841 rv = pte_test(pte, bit);
2850 * pmap_page_wired_mappings:
2852 * Return the number of managed mappings to the given physical page
2856 pmap_page_wired_mappings(vm_page_t m)
2864 if ((m->oflags & VPO_UNMANAGED) != 0)
2866 rw_wlock(&pvh_global_lock);
2867 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2870 pte = pmap_pte(pmap, pv->pv_va);
2871 if (pte_test(pte, PTE_W))
2875 rw_wunlock(&pvh_global_lock);
2880 * Clear the write and modified bits in each of the given page's mappings.
2883 pmap_remove_write(vm_page_t m)
2886 pt_entry_t pbits, *pte;
2889 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2890 ("pmap_remove_write: page %p is not managed", m));
2893 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2894 * set by another thread while the object is locked. Thus,
2895 * if PGA_WRITEABLE is clear, no page table entries need updating.
2897 VM_OBJECT_ASSERT_WLOCKED(m->object);
2898 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2900 rw_wlock(&pvh_global_lock);
2901 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2904 pte = pmap_pte(pmap, pv->pv_va);
2905 KASSERT(pte != NULL && pte_test(pte, PTE_V),
2906 ("page on pv_list has no pte"));
2908 if (pte_test(&pbits, PTE_D)) {
2909 pte_clear(&pbits, PTE_D);
2912 pte_set(&pbits, PTE_RO);
2913 if (pbits != *pte) {
2915 pmap_update_page(pmap, pv->pv_va, pbits);
2919 vm_page_aflag_clear(m, PGA_WRITEABLE);
2920 rw_wunlock(&pvh_global_lock);
2924 * pmap_ts_referenced:
2926 * Return the count of reference bits for a page, clearing all of them.
2929 pmap_ts_referenced(vm_page_t m)
2932 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2933 ("pmap_ts_referenced: page %p is not managed", m));
2934 if (m->md.pv_flags & PV_TABLE_REF) {
2935 rw_wlock(&pvh_global_lock);
2936 m->md.pv_flags &= ~PV_TABLE_REF;
2937 rw_wunlock(&pvh_global_lock);
2946 * Return whether or not the specified physical page was modified
2947 * in any physical maps.
2950 pmap_is_modified(vm_page_t m)
2954 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2955 ("pmap_is_modified: page %p is not managed", m));
2958 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2959 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2960 * is clear, no PTEs can have PTE_D set.
2962 VM_OBJECT_ASSERT_WLOCKED(m->object);
2963 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2965 rw_wlock(&pvh_global_lock);
2966 rv = pmap_testbit(m, PTE_D);
2967 rw_wunlock(&pvh_global_lock);
2974 * pmap_is_prefaultable:
2976 * Return whether or not the specified virtual address is elgible
2980 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2988 pde = pmap_pde(pmap, addr);
2989 if (pde != NULL && *pde != 0) {
2990 pte = pmap_pde_to_pte(pde, addr);
2998 * Apply the given advice to the specified range of addresses within the
2999 * given pmap. Depending on the advice, clear the referenced and/or
3000 * modified flags in each mapping and set the mapped page's dirty field.
3003 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3005 pd_entry_t *pde, *pdpe;
3007 vm_offset_t va, va_next;
3011 if (advice != MADV_DONTNEED && advice != MADV_FREE)
3013 rw_wlock(&pvh_global_lock);
3015 for (; sva < eva; sva = va_next) {
3016 pdpe = pmap_segmap(pmap, sva);
3019 va_next = (sva + NBSEG) & ~SEGMASK;
3025 va_next = (sva + NBPDR) & ~PDRMASK;
3029 pde = pmap_pdpe_to_pde(pdpe, sva);
3034 * Limit our scan to either the end of the va represented
3035 * by the current page table page, or to the end of the
3036 * range being write protected.
3042 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3044 if (!pte_test(pte, PTE_MANAGED | PTE_V)) {
3045 if (va != va_next) {
3046 pmap_invalidate_range(pmap, va, sva);
3051 pa = TLBLO_PTE_TO_PA(*pte);
3052 m = PHYS_TO_VM_PAGE(pa);
3053 m->md.pv_flags &= ~PV_TABLE_REF;
3054 if (pte_test(pte, PTE_D)) {
3055 if (advice == MADV_DONTNEED) {
3057 * Future calls to pmap_is_modified()
3058 * can be avoided by making the page
3063 pte_clear(pte, PTE_D);
3069 * Unless PTE_D is set, any TLB entries
3070 * mapping "sva" don't allow write access, so
3071 * they needn't be invalidated.
3073 if (va != va_next) {
3074 pmap_invalidate_range(pmap, va, sva);
3080 pmap_invalidate_range(pmap, va, sva);
3082 rw_wunlock(&pvh_global_lock);
3087 * Clear the modify bits on the specified physical page.
3090 pmap_clear_modify(vm_page_t m)
3096 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3097 ("pmap_clear_modify: page %p is not managed", m));
3098 VM_OBJECT_ASSERT_WLOCKED(m->object);
3099 KASSERT(!vm_page_xbusied(m),
3100 ("pmap_clear_modify: page %p is exclusive busied", m));
3103 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set.
3104 * If the object containing the page is locked and the page is not
3105 * write busied, then PGA_WRITEABLE cannot be concurrently set.
3107 if ((m->aflags & PGA_WRITEABLE) == 0)
3109 rw_wlock(&pvh_global_lock);
3110 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3113 pte = pmap_pte(pmap, pv->pv_va);
3114 if (pte_test(pte, PTE_D)) {
3115 pte_clear(pte, PTE_D);
3116 pmap_update_page(pmap, pv->pv_va, *pte);
3120 rw_wunlock(&pvh_global_lock);
3124 * pmap_is_referenced:
3126 * Return whether or not the specified physical page was referenced
3127 * in any physical maps.
3130 pmap_is_referenced(vm_page_t m)
3133 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3134 ("pmap_is_referenced: page %p is not managed", m));
3135 return ((m->md.pv_flags & PV_TABLE_REF) != 0);
3139 * Miscellaneous support routines follow
3143 * Map a set of physical memory pages into the kernel virtual
3144 * address space. Return a pointer to where it is mapped. This
3145 * routine is intended to be used for mapping device memory,
3148 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit.
3151 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3153 vm_offset_t va, tmpva, offset;
3156 * KSEG1 maps only first 512M of phys address space. For
3157 * pa > 0x20000000 we should make proper mapping * using pmap_kenter.
3159 if (MIPS_DIRECT_MAPPABLE(pa + size - 1) && ma == VM_MEMATTR_UNCACHEABLE)
3160 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
3162 offset = pa & PAGE_MASK;
3163 size = roundup(size + offset, PAGE_SIZE);
3165 va = kva_alloc(size);
3167 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3168 pa = trunc_page(pa);
3169 for (tmpva = va; size > 0;) {
3170 pmap_kenter_attr(tmpva, pa, ma);
3177 return ((void *)(va + offset));
3181 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3183 return pmap_mapdev_attr(pa, size, VM_MEMATTR_UNCACHEABLE);
3187 pmap_unmapdev(vm_offset_t va, vm_size_t size)
3190 vm_offset_t base, offset;
3192 /* If the address is within KSEG1 then there is nothing to do */
3193 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
3196 base = trunc_page(va);
3197 offset = va & PAGE_MASK;
3198 size = roundup(size + offset, PAGE_SIZE);
3199 kva_free(base, size);
3204 * perform the pmap work for mincore
3207 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3209 pt_entry_t *ptep, pte;
3216 ptep = pmap_pte(pmap, addr);
3217 pte = (ptep != NULL) ? *ptep : 0;
3218 if (!pte_test(&pte, PTE_V)) {
3222 val = MINCORE_INCORE;
3223 if (pte_test(&pte, PTE_D))
3224 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3225 pa = TLBLO_PTE_TO_PA(pte);
3226 if (pte_test(&pte, PTE_MANAGED)) {
3228 * This may falsely report the given address as
3229 * MINCORE_REFERENCED. Unfortunately, due to the lack of
3230 * per-PTE reference information, it is impossible to
3231 * determine if the address is MINCORE_REFERENCED.
3233 m = PHYS_TO_VM_PAGE(pa);
3234 if ((m->aflags & PGA_REFERENCED) != 0)
3235 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3237 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3238 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
3239 pte_test(&pte, PTE_MANAGED)) {
3240 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3241 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3245 PA_UNLOCK_COND(*locked_pa);
3251 pmap_activate(struct thread *td)
3253 pmap_t pmap, oldpmap;
3254 struct proc *p = td->td_proc;
3259 pmap = vmspace_pmap(p->p_vmspace);
3260 oldpmap = PCPU_GET(curpmap);
3261 cpuid = PCPU_GET(cpuid);
3264 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
3265 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
3266 pmap_asid_alloc(pmap);
3267 if (td == curthread) {
3268 PCPU_SET(segbase, pmap->pm_segtab);
3269 mips_wr_entryhi(pmap->pm_asid[cpuid].asid);
3272 PCPU_SET(curpmap, pmap);
3277 pmap_sync_icache_one(void *arg __unused)
3280 mips_icache_sync_all();
3281 mips_dcache_wbinv_all();
3285 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3288 smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
3292 * Increase the starting virtual address of the given mapping if a
3293 * different alignment might result in more superpage mappings.
3296 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3297 vm_offset_t *addr, vm_size_t size)
3299 vm_offset_t superpage_offset;
3303 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
3304 offset += ptoa(object->pg_color);
3305 superpage_offset = offset & PDRMASK;
3306 if (size - ((PDRSIZE - superpage_offset) & PDRMASK) < PDRSIZE ||
3307 (*addr & PDRMASK) == superpage_offset)
3309 if ((*addr & PDRMASK) < superpage_offset)
3310 *addr = (*addr & ~PDRMASK) + superpage_offset;
3312 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
3316 DB_SHOW_COMMAND(ptable, ddb_pid_dump)
3319 struct thread *td = NULL;
3326 td = db_lookup_thread(addr, true);
3328 db_printf("Invalid pid or tid");
3332 if (p->p_vmspace == NULL) {
3333 db_printf("No vmspace for process");
3336 pmap = vmspace_pmap(p->p_vmspace);
3340 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n",
3341 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid,
3342 pmap->pm_asid[0].gen);
3343 for (i = 0; i < NPDEPG; i++) {
3348 pdpe = (pd_entry_t *)pmap->pm_segtab[i];
3351 db_printf("[%4d] %p\n", i, pdpe);
3353 for (j = 0; j < NPDEPG; j++) {
3354 pde = (pt_entry_t *)pdpe[j];
3357 db_printf("\t[%4d] %p\n", j, pde);
3361 pde = (pt_entry_t *)pdpe;
3363 for (k = 0; k < NPTEPG; k++) {
3365 if (pte == 0 || !pte_test(&pte, PTE_V))
3367 pa = TLBLO_PTE_TO_PA(pte);
3368 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT);
3369 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n",
3370 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa);
3378 * Allocate TLB address space tag (called ASID or TLBPID) and return it.
3379 * It takes almost as much or more time to search the TLB for a
3380 * specific ASID and flush those entries as it does to flush the entire TLB.
3381 * Therefore, when we allocate a new ASID, we just take the next number. When
3382 * we run out of numbers, we flush the TLB, increment the generation count
3383 * and start over. ASID zero is reserved for kernel use.
3386 pmap_asid_alloc(pmap)
3389 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED &&
3390 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
3392 if (PCPU_GET(next_asid) == pmap_max_asid) {
3393 tlb_invalidate_all_user(NULL);
3394 PCPU_SET(asid_generation,
3395 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
3396 if (PCPU_GET(asid_generation) == 0) {
3397 PCPU_SET(asid_generation, 1);
3399 PCPU_SET(next_asid, 1); /* 0 means invalid */
3401 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid);
3402 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation);
3403 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1);
3408 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot)
3412 if (!(prot & VM_PROT_WRITE))
3413 rw = PTE_V | PTE_RO;
3414 else if ((m->oflags & VPO_UNMANAGED) == 0) {
3415 if ((access & VM_PROT_WRITE) != 0)
3420 /* Needn't emulate a modified bit for unmanaged pages. */
3426 * pmap_emulate_modified : do dirty bit emulation
3428 * On SMP, update just the local TLB, other CPUs will update their
3429 * TLBs from PTE lazily, if they get the exception.
3430 * Returns 0 in case of sucess, 1 if the page is read only and we
3434 pmap_emulate_modified(pmap_t pmap, vm_offset_t va)
3439 pte = pmap_pte(pmap, va);
3441 panic("pmap_emulate_modified: can't find PTE");
3443 /* It is possible that some other CPU changed m-bit */
3444 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) {
3445 tlb_update(pmap, va, *pte);
3450 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D))
3451 panic("pmap_emulate_modified: invalid pte");
3453 if (pte_test(pte, PTE_RO)) {
3457 pte_set(pte, PTE_D);
3458 tlb_update(pmap, va, *pte);
3459 if (!pte_test(pte, PTE_MANAGED))
3460 panic("pmap_emulate_modified: unmanaged page");
3466 * Routine: pmap_kextract
3468 * Extract the physical page address associated
3472 pmap_kextract(vm_offset_t va)
3477 * First, the direct-mapped regions.
3479 #if defined(__mips_n64)
3480 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
3481 return (MIPS_XKPHYS_TO_PHYS(va));
3483 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
3484 return (MIPS_KSEG0_TO_PHYS(va));
3486 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
3487 return (MIPS_KSEG1_TO_PHYS(va));
3490 * User virtual addresses.
3492 if (va < VM_MAXUSER_ADDRESS) {
3495 if (curproc && curproc->p_vmspace) {
3496 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
3498 return (TLBLO_PTE_TO_PA(*ptep) |
3506 * Should be kernel virtual here, otherwise fail
3508 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
3509 #if defined(__mips_n64)
3510 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
3519 /* Is the kernel pmap initialized? */
3520 if (!CPU_EMPTY(&kernel_pmap->pm_active)) {
3521 /* It's inside the virtual address range */
3522 ptep = pmap_pte(kernel_pmap, va);
3524 return (TLBLO_PTE_TO_PA(*ptep) |
3531 panic("%s for unknown address space %p.", __func__, (void *)va);
3536 pmap_flush_pvcache(vm_page_t m)
3541 for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
3542 pv = TAILQ_NEXT(pv, pv_list)) {
3543 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
3549 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3553 * It appears that this function can only be called before any mappings
3554 * for the page are established. If this ever changes, this code will
3555 * need to walk the pv_list and make each of the existing mappings
3556 * uncacheable, being careful to sync caches and PTEs (and maybe
3557 * invalidate TLB?) for any current mapping it modifies.
3559 if (TAILQ_FIRST(&m->md.pv_list) != NULL)
3560 panic("Can't change memattr on page with existing mappings");
3562 /* Clean memattr portion of pv_flags */
3563 m->md.pv_flags &= ~PV_MEMATTR_MASK;
3564 m->md.pv_flags |= (ma << PV_MEMATTR_SHIFT) & PV_MEMATTR_MASK;
3567 static __inline void
3568 pmap_pte_attr(pt_entry_t *pte, vm_memattr_t ma)
3572 npte = *(u_int *)pte;
3573 npte &= ~PTE_C_MASK;
3579 pmap_change_attr(vm_offset_t sva, vm_size_t size, vm_memattr_t ma)
3581 pd_entry_t *pde, *pdpe;
3583 vm_offset_t ova, eva, va, va_next;
3594 for (; sva < eva; sva = va_next) {
3595 pdpe = pmap_segmap(pmap, sva);
3598 va_next = (sva + NBSEG) & ~SEGMASK;
3604 va_next = (sva + NBPDR) & ~PDRMASK;
3608 pde = pmap_pdpe_to_pde(pdpe, sva);
3613 * Limit our scan to either the end of the va represented
3614 * by the current page table page, or to the end of the
3615 * range being removed.
3621 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3623 if (!pte_test(pte, PTE_V) || pte_cache_bits(pte) == ma) {
3624 if (va != va_next) {
3625 pmap_invalidate_range(pmap, va, sva);
3633 pmap_pte_attr(pte, ma);
3636 pmap_invalidate_range(pmap, va, sva);
3640 /* Flush caches to be in the safe side */
3641 mips_dcache_wbinv_range(ova, size);