2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps
41 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish
45 * Manages physical address maps.
47 * Since the information managed by this module is
48 * also stored by the logical address mapping module,
49 * this module may throw away valid virtual-to-physical
50 * mappings at almost any time. However, invalidations
51 * of virtual-to-physical mappings must be done as
54 * In order to cope with hardware architectures which
55 * make virtual-to-physical map invalidates expensive,
56 * this module may delay invalidate or reduced protection
57 * operations until such time as they are actually
58 * necessary. This module is given full information as
59 * to which processors are currently using which maps,
60 * and to when physical maps must be made correct.
63 #include <sys/cdefs.h>
64 __FBSDID("$FreeBSD$");
69 #include <sys/param.h>
70 #include <sys/systm.h>
73 #include <sys/msgbuf.h>
74 #include <sys/mutex.h>
77 #include <sys/rwlock.h>
78 #include <sys/sched.h>
80 #include <sys/sysctl.h>
81 #include <sys/vmmeter.h>
88 #include <vm/vm_param.h>
89 #include <vm/vm_kern.h>
90 #include <vm/vm_page.h>
91 #include <vm/vm_phys.h>
92 #include <vm/vm_map.h>
93 #include <vm/vm_object.h>
94 #include <vm/vm_extern.h>
95 #include <vm/vm_pageout.h>
96 #include <vm/vm_pager.h>
99 #include <machine/cache.h>
100 #include <machine/md_var.h>
101 #include <machine/tlb.h>
105 #if !defined(DIAGNOSTIC)
106 #define PMAP_INLINE __inline
112 #define PV_STAT(x) do { x ; } while (0)
114 #define PV_STAT(x) do { } while (0)
118 * Get PDEs and PTEs for user/kernel address space
120 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
121 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1))
122 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1))
123 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT)
126 #define NUPDE (NPDEPG * NPDEPG)
127 #define NUSERPGTBLS (NUPDE + NPDEPG)
129 #define NUPDE (NPDEPG)
130 #define NUSERPGTBLS (NUPDE)
133 #define is_kernel_pmap(x) ((x) == kernel_pmap)
135 struct pmap kernel_pmap_store;
136 pd_entry_t *kernel_segmap;
138 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
139 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
142 unsigned pmap_max_asid; /* max ASID supported by the system */
144 #define PMAP_ASID_RESERVED 0
146 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
148 static void pmap_asid_alloc(pmap_t pmap);
150 static struct rwlock_padalign pvh_global_lock;
153 * Data for the pv entry allocation mechanism
155 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
156 static int pv_entry_count;
158 static void free_pv_chunk(struct pv_chunk *pc);
159 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
160 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
161 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
162 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
163 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
165 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req);
166 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
167 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
168 static void pmap_grow_direct_page(int req);
169 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
171 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
172 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
173 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
174 vm_offset_t va, vm_page_t m);
175 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
176 static void pmap_invalidate_all(pmap_t pmap);
177 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
178 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m);
180 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
181 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags);
182 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t);
183 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot);
185 static void pmap_invalidate_page_action(void *arg);
186 static void pmap_invalidate_range_action(void *arg);
187 static void pmap_update_page_action(void *arg);
191 * This structure is for high memory (memory above 512Meg in 32 bit) support.
192 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to
193 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc.
195 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To
196 * access a highmem physical address on a CPU, we map the physical address to
197 * the reserved virtual address for the CPU in the kernel pagetable. This is
198 * done with interrupts disabled(although a spinlock and sched_pin would be
201 struct local_sysmaps {
204 uint16_t valid1, valid2;
206 static struct local_sysmaps sysmap_lmem[MAXCPU];
209 pmap_alloc_lmem_map(void)
213 for (i = 0; i < MAXCPU; i++) {
214 sysmap_lmem[i].base = virtual_avail;
215 virtual_avail += PAGE_SIZE * 2;
216 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0;
220 static __inline vm_offset_t
221 pmap_lmem_map1(vm_paddr_t phys)
223 struct local_sysmaps *sysm;
224 pt_entry_t *pte, npte;
229 intr = intr_disable();
230 cpu = PCPU_GET(cpuid);
231 sysm = &sysmap_lmem[cpu];
232 sysm->saved_intr = intr;
234 npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
235 pte = pmap_pte(kernel_pmap, va);
241 static __inline vm_offset_t
242 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
244 struct local_sysmaps *sysm;
245 pt_entry_t *pte, npte;
246 vm_offset_t va1, va2;
250 intr = intr_disable();
251 cpu = PCPU_GET(cpuid);
252 sysm = &sysmap_lmem[cpu];
253 sysm->saved_intr = intr;
255 va2 = sysm->base + PAGE_SIZE;
256 npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
257 pte = pmap_pte(kernel_pmap, va1);
259 npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
260 pte = pmap_pte(kernel_pmap, va2);
268 pmap_lmem_unmap(void)
270 struct local_sysmaps *sysm;
274 cpu = PCPU_GET(cpuid);
275 sysm = &sysmap_lmem[cpu];
276 pte = pmap_pte(kernel_pmap, sysm->base);
278 tlb_invalidate_address(kernel_pmap, sysm->base);
281 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE);
283 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE);
286 intr_restore(sysm->saved_intr);
288 #else /* __mips_n64 */
291 pmap_alloc_lmem_map(void)
295 static __inline vm_offset_t
296 pmap_lmem_map1(vm_paddr_t phys)
302 static __inline vm_offset_t
303 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
309 static __inline vm_offset_t
310 pmap_lmem_unmap(void)
315 #endif /* !__mips_n64 */
318 pmap_pte_cache_bits(vm_paddr_t pa, vm_page_t m)
322 ma = pmap_page_get_memattr(m);
323 if (ma == VM_MEMATTR_WRITE_BACK && !is_cacheable_mem(pa))
324 ma = VM_MEMATTR_UNCACHEABLE;
327 #define PMAP_PTE_SET_CACHE_BITS(pte, ps, m) { \
328 pte &= ~PTE_C_MASK; \
329 pte |= pmap_pte_cache_bits(pa, m); \
333 * Page table entry lookup routines.
335 static __inline pd_entry_t *
336 pmap_segmap(pmap_t pmap, vm_offset_t va)
339 return (&pmap->pm_segtab[pmap_seg_index(va)]);
343 static __inline pd_entry_t *
344 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
348 pde = (pd_entry_t *)*pdpe;
349 return (&pde[pmap_pde_index(va)]);
352 static __inline pd_entry_t *
353 pmap_pde(pmap_t pmap, vm_offset_t va)
357 pdpe = pmap_segmap(pmap, va);
361 return (pmap_pdpe_to_pde(pdpe, va));
364 static __inline pd_entry_t *
365 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
372 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va)
375 return (pmap_segmap(pmap, va));
379 static __inline pt_entry_t *
380 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
384 pte = (pt_entry_t *)*pde;
385 return (&pte[pmap_pte_index(va)]);
389 pmap_pte(pmap_t pmap, vm_offset_t va)
393 pde = pmap_pde(pmap, va);
394 if (pde == NULL || *pde == NULL)
397 return (pmap_pde_to_pte(pde, va));
401 pmap_steal_memory(vm_size_t size)
403 vm_paddr_t bank_size, pa;
406 size = round_page(size);
407 bank_size = phys_avail[1] - phys_avail[0];
408 while (size > bank_size) {
411 for (i = 0; phys_avail[i + 2]; i += 2) {
412 phys_avail[i] = phys_avail[i + 2];
413 phys_avail[i + 1] = phys_avail[i + 3];
416 phys_avail[i + 1] = 0;
418 panic("pmap_steal_memory: out of memory");
419 bank_size = phys_avail[1] - phys_avail[0];
423 phys_avail[0] += size;
424 if (MIPS_DIRECT_MAPPABLE(pa) == 0)
425 panic("Out of memory below 512Meg?");
426 va = MIPS_PHYS_TO_DIRECT(pa);
427 bzero((caddr_t)va, size);
432 * Bootstrap the system enough to run with virtual memory. This
433 * assumes that the phys_avail array has been initialized.
436 pmap_create_kernel_pagetable(void)
448 * Allocate segment table for the kernel
450 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE);
453 * Allocate second level page tables for the kernel
456 npde = howmany(NKPT, NPDEPG);
457 pdaddr = pmap_steal_memory(PAGE_SIZE * npde);
460 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt);
463 * The R[4-7]?00 stores only one copy of the Global bit in the
464 * translation lookaside buffer for each 2 page entry. Thus invalid
465 * entrys must have the Global bit set so when Entry LO and Entry HI
466 * G bits are anded together they will produce a global bit to store
469 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++)
473 for (i = 0, npt = nkpt; npt > 0; i++) {
474 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE);
475 pde = (pd_entry_t *)kernel_segmap[i];
477 for (j = 0; j < NPDEPG && npt > 0; j++, npt--)
478 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE);
481 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++)
482 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE));
485 PMAP_LOCK_INIT(kernel_pmap);
486 kernel_pmap->pm_segtab = kernel_segmap;
487 CPU_FILL(&kernel_pmap->pm_active);
488 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
489 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
490 kernel_pmap->pm_asid[0].gen = 0;
491 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE;
498 int need_local_mappings = 0;
502 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
504 * Keep the memory aligned on page boundary.
506 phys_avail[i] = round_page(phys_avail[i]);
507 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
511 if (phys_avail[i - 2] > phys_avail[i]) {
514 ptemp[0] = phys_avail[i + 0];
515 ptemp[1] = phys_avail[i + 1];
517 phys_avail[i + 0] = phys_avail[i - 2];
518 phys_avail[i + 1] = phys_avail[i - 1];
520 phys_avail[i - 2] = ptemp[0];
521 phys_avail[i - 1] = ptemp[1];
527 * In 32 bit, we may have memory which cannot be mapped directly.
528 * This memory will need temporary mapping before it can be
531 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1))
532 need_local_mappings = 1;
535 * Copy the phys_avail[] array before we start stealing memory from it.
537 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
538 physmem_desc[i] = phys_avail[i];
539 physmem_desc[i + 1] = phys_avail[i + 1];
542 Maxmem = atop(phys_avail[i - 1]);
545 printf("Physical memory chunk(s):\n");
546 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
549 size = phys_avail[i + 1] - phys_avail[i];
550 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n",
551 (uintmax_t) phys_avail[i],
552 (uintmax_t) phys_avail[i + 1] - 1,
553 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE);
555 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem));
558 * Steal the message buffer from the beginning of memory.
560 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize);
561 msgbufinit(msgbufp, msgbufsize);
564 * Steal thread0 kstack.
566 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
568 virtual_avail = VM_MIN_KERNEL_ADDRESS;
569 virtual_end = VM_MAX_KERNEL_ADDRESS;
573 * Steal some virtual address space to map the pcpu area.
575 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2);
576 pcpup = (struct pcpu *)virtual_avail;
577 virtual_avail += PAGE_SIZE * 2;
580 * Initialize the wired TLB entry mapping the pcpu region for
581 * the BSP at 'pcpup'. Up until this point we were operating
582 * with the 'pcpup' for the BSP pointing to a virtual address
583 * in KSEG0 so there was no need for a TLB mapping.
585 mips_pcpu_tlb_init(PCPU_ADDR(0));
588 printf("pcpu is available at virtual address %p.\n", pcpup);
591 if (need_local_mappings)
592 pmap_alloc_lmem_map();
593 pmap_create_kernel_pagetable();
594 pmap_max_asid = VMNUM_PIDS;
599 * Initialize the global pv list lock.
601 rw_init(&pvh_global_lock, "pmap pv global");
605 * Initialize a vm_page's machine-dependent fields.
608 pmap_page_init(vm_page_t m)
611 TAILQ_INIT(&m->md.pv_list);
612 m->md.pv_flags = VM_MEMATTR_DEFAULT << PV_MEMATTR_SHIFT;
616 * Initialize the pmap module.
617 * Called by vm_init, to initialize any structures that the pmap
618 * system needs to map virtual memory.
625 /***************************************************
626 * Low level helper routines.....
627 ***************************************************/
631 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
633 int cpuid, cpu, self;
634 cpuset_t active_cpus;
637 if (is_kernel_pmap(pmap)) {
638 smp_rendezvous(NULL, fn, NULL, arg);
641 /* Force ASID update on inactive CPUs */
643 if (!CPU_ISSET(cpu, &pmap->pm_active))
644 pmap->pm_asid[cpu].gen = 0;
646 cpuid = PCPU_GET(cpuid);
648 * XXX: barrier/locking for active?
650 * Take a snapshot of active here, any further changes are ignored.
651 * tlb update/invalidate should be harmless on inactive CPUs
653 active_cpus = pmap->pm_active;
654 self = CPU_ISSET(cpuid, &active_cpus);
655 CPU_CLR(cpuid, &active_cpus);
656 /* Optimize for the case where this cpu is the only active one */
657 if (CPU_EMPTY(&active_cpus)) {
662 CPU_SET(cpuid, &active_cpus);
663 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg);
670 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
674 if (is_kernel_pmap(pmap)) {
678 cpuid = PCPU_GET(cpuid);
679 if (!CPU_ISSET(cpuid, &pmap->pm_active))
680 pmap->pm_asid[cpuid].gen = 0;
687 pmap_invalidate_all(pmap_t pmap)
690 pmap_call_on_active_cpus(pmap,
691 (void (*)(void *))tlb_invalidate_all_user, pmap);
694 struct pmap_invalidate_page_arg {
700 pmap_invalidate_page_action(void *arg)
702 struct pmap_invalidate_page_arg *p = arg;
704 tlb_invalidate_address(p->pmap, p->va);
708 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
710 struct pmap_invalidate_page_arg arg;
714 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg);
717 struct pmap_invalidate_range_arg {
724 pmap_invalidate_range_action(void *arg)
726 struct pmap_invalidate_range_arg *p = arg;
728 tlb_invalidate_range(p->pmap, p->sva, p->eva);
732 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
734 struct pmap_invalidate_range_arg arg;
739 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg);
742 struct pmap_update_page_arg {
749 pmap_update_page_action(void *arg)
751 struct pmap_update_page_arg *p = arg;
753 tlb_update(p->pmap, p->va, p->pte);
757 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte)
759 struct pmap_update_page_arg arg;
764 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg);
768 * Routine: pmap_extract
770 * Extract the physical page address associated
771 * with the given map/virtual_address pair.
774 pmap_extract(pmap_t pmap, vm_offset_t va)
777 vm_offset_t retval = 0;
780 pte = pmap_pte(pmap, va);
782 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK);
789 * Routine: pmap_extract_and_hold
791 * Atomically extract and hold the physical page
792 * with the given pmap and virtual address pair
793 * if that mapping permits the given protection.
796 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
798 pt_entry_t pte, *ptep;
799 vm_paddr_t pa, pte_pa;
806 ptep = pmap_pte(pmap, va);
809 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) ||
810 (prot & VM_PROT_WRITE) == 0)) {
811 pte_pa = TLBLO_PTE_TO_PA(pte);
812 if (vm_page_pa_tryrelock(pmap, pte_pa, &pa))
814 m = PHYS_TO_VM_PAGE(pte_pa);
823 /***************************************************
824 * Low level mapping routines.....
825 ***************************************************/
828 * add a wired page to the kva
831 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
834 pt_entry_t opte, npte;
837 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
840 pte = pmap_pte(kernel_pmap, va);
842 npte = TLBLO_PA_TO_PFN(pa) | PTE_C(ma) | PTE_D | PTE_V | PTE_G;
844 if (pte_test(&opte, PTE_V) && opte != npte)
845 pmap_update_page(kernel_pmap, va, npte);
849 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
852 KASSERT(is_cacheable_mem(pa),
853 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa));
855 pmap_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
859 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
862 KASSERT((size & PAGE_MASK) == 0,
863 ("%s: device mapping not page-sized", __func__));
865 for (; size > 0; size -= PAGE_SIZE) {
867 * XXXCEM: this is somewhat inefficient on SMP systems in that
868 * every single page is individually TLB-invalidated via
869 * rendezvous (pmap_update_page()), instead of invalidating the
870 * entire range via a single rendezvous.
872 pmap_kenter_attr(va, pa, VM_MEMATTR_UNCACHEABLE);
879 pmap_kremove_device(vm_offset_t va, vm_size_t size)
882 KASSERT((size & PAGE_MASK) == 0,
883 ("%s: device mapping not page-sized", __func__));
886 * XXXCEM: Similar to pmap_kenter_device, this is inefficient on SMP,
887 * in that pages are invalidated individually instead of a single range
890 for (; size > 0; size -= PAGE_SIZE) {
897 * remove a page from the kernel pagetables
899 /* PMAP_INLINE */ void
900 pmap_kremove(vm_offset_t va)
905 * Write back all caches from the page being destroyed
907 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
909 pte = pmap_pte(kernel_pmap, va);
911 pmap_invalidate_page(kernel_pmap, va);
915 * Used to map a range of physical addresses into kernel
916 * virtual address space.
918 * The value passed in '*virt' is a suggested virtual address for
919 * the mapping. Architectures which can support a direct-mapped
920 * physical to virtual region can return the appropriate address
921 * within that region, leaving '*virt' unchanged. Other
922 * architectures should map the pages starting at '*virt' and
923 * update '*virt' with the first usable address after the mapped
926 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
929 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
933 if (MIPS_DIRECT_MAPPABLE(end - 1))
934 return (MIPS_PHYS_TO_DIRECT(start));
937 while (start < end) {
938 pmap_kenter(va, start);
947 * Add a list of wired pages to the kva
948 * this routine is only used for temporary
949 * kernel mappings that do not need to have
950 * page modification or references recorded.
951 * Note that old mappings are simply written
952 * over. The page *must* be wired.
955 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
958 vm_offset_t origva = va;
960 for (i = 0; i < count; i++) {
961 pmap_flush_pvcache(m[i]);
962 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i]));
966 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count);
970 * this routine jerks page mappings from the
971 * kernel -- it is meant only for temporary mappings.
974 pmap_qremove(vm_offset_t va, int count)
981 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count);
984 pte = pmap_pte(kernel_pmap, va);
987 } while (--count > 0);
988 pmap_invalidate_range(kernel_pmap, origva, va);
991 /***************************************************
992 * Page table page management routines.....
993 ***************************************************/
996 * Decrements a page table page's wire count, which is used to record the
997 * number of valid page table entries within the page. If the wire count
998 * drops to zero, then the page table page is unmapped. Returns TRUE if the
999 * page table page was unmapped and FALSE otherwise.
1001 static PMAP_INLINE boolean_t
1002 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
1006 if (m->wire_count == 0) {
1007 _pmap_unwire_ptp(pmap, va, m);
1014 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
1018 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1020 * unmap the page table page
1023 if (m->pindex < NUPDE)
1024 pde = pmap_pde(pmap, va);
1026 pde = pmap_segmap(pmap, va);
1028 pde = pmap_pde(pmap, va);
1031 pmap->pm_stats.resident_count--;
1034 if (m->pindex < NUPDE) {
1039 * Recursively decrement next level pagetable refcount
1041 pdp = (pd_entry_t *)*pmap_segmap(pmap, va);
1042 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp));
1043 pmap_unwire_ptp(pmap, va, pdpg);
1048 * If the page is finally unwired, simply free it.
1050 vm_page_free_zero(m);
1055 * After removing a page table entry, this routine is used to
1056 * conditionally free the page, and manage the hold/wire counts.
1059 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1063 if (va >= VM_MAXUSER_ADDRESS)
1065 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0"));
1066 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde));
1067 return (pmap_unwire_ptp(pmap, va, mpte));
1071 pmap_pinit0(pmap_t pmap)
1075 PMAP_LOCK_INIT(pmap);
1076 pmap->pm_segtab = kernel_segmap;
1077 CPU_ZERO(&pmap->pm_active);
1078 for (i = 0; i < MAXCPU; i++) {
1079 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1080 pmap->pm_asid[i].gen = 0;
1082 PCPU_SET(curpmap, pmap);
1083 TAILQ_INIT(&pmap->pm_pvchunk);
1084 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1088 pmap_grow_direct_page(int req)
1094 if (!vm_page_reclaim_contig(req, 1, 0, MIPS_KSEG0_LARGEST_PHYS,
1101 pmap_alloc_direct_page(unsigned int index, int req)
1105 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED |
1110 if ((m->flags & PG_ZERO) == 0)
1118 * Initialize a preallocated and zeroed pmap structure,
1119 * such as one in a vmspace structure.
1122 pmap_pinit(pmap_t pmap)
1129 * allocate the page directory page
1131 req_class = VM_ALLOC_NORMAL;
1132 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, req_class)) ==
1134 pmap_grow_direct_page(req_class);
1136 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg));
1137 pmap->pm_segtab = (pd_entry_t *)ptdva;
1138 CPU_ZERO(&pmap->pm_active);
1139 for (i = 0; i < MAXCPU; i++) {
1140 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1141 pmap->pm_asid[i].gen = 0;
1143 TAILQ_INIT(&pmap->pm_pvchunk);
1144 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1150 * this routine is called if the page table page is not
1154 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags)
1161 * Find or fabricate a new pagetable page
1163 req_class = VM_ALLOC_NORMAL;
1164 if ((m = pmap_alloc_direct_page(ptepindex, req_class)) == NULL) {
1165 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1167 rw_wunlock(&pvh_global_lock);
1168 pmap_grow_direct_page(req_class);
1169 rw_wlock(&pvh_global_lock);
1174 * Indicate the need to retry. While waiting, the page
1175 * table page may have been allocated.
1181 * Map the pagetable page into the process address space, if it
1182 * isn't already there.
1184 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1187 if (ptepindex >= NUPDE) {
1188 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva;
1190 pd_entry_t *pdep, *pde;
1191 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT);
1192 int pdeindex = ptepindex & (NPDEPG - 1);
1195 pdep = &pmap->pm_segtab[segindex];
1196 if (*pdep == NULL) {
1197 /* recurse for allocating page dir */
1198 if (_pmap_allocpte(pmap, NUPDE + segindex,
1200 /* alloc failed, release current */
1201 vm_page_unwire_noq(m);
1202 vm_page_free_zero(m);
1206 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep));
1209 /* Next level entry */
1210 pde = (pd_entry_t *)*pdep;
1211 pde[pdeindex] = (pd_entry_t)pageva;
1214 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva;
1216 pmap->pm_stats.resident_count++;
1221 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1228 * Calculate pagetable page index
1230 ptepindex = pmap_pde_pindex(va);
1233 * Get the page directory entry
1235 pde = pmap_pde(pmap, va);
1238 * If the page table page is mapped, we just increment the hold
1239 * count, and activate it.
1241 if (pde != NULL && *pde != NULL) {
1242 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde));
1246 * Here if the pte page isn't mapped, or if it has been
1249 m = _pmap_allocpte(pmap, ptepindex, flags);
1250 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1257 /***************************************************
1258 * Pmap allocation/deallocation routines.
1259 ***************************************************/
1262 * Release any resources held by the given physical map.
1263 * Called when a pmap initialized by pmap_pinit is being released.
1264 * Should only be called if the map contains no valid mappings.
1267 pmap_release(pmap_t pmap)
1272 KASSERT(pmap->pm_stats.resident_count == 0,
1273 ("pmap_release: pmap resident count %ld != 0",
1274 pmap->pm_stats.resident_count));
1276 ptdva = (vm_offset_t)pmap->pm_segtab;
1277 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva));
1279 vm_page_unwire_noq(ptdpg);
1280 vm_page_free_zero(ptdpg);
1284 * grow the number of kernel page table entries, if needed
1287 pmap_growkernel(vm_offset_t addr)
1290 pd_entry_t *pde, *pdpe;
1294 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1295 req_class = VM_ALLOC_INTERRUPT;
1296 addr = roundup2(addr, NBSEG);
1297 if (addr - 1 >= vm_map_max(kernel_map))
1298 addr = vm_map_max(kernel_map);
1299 while (kernel_vm_end < addr) {
1300 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end);
1303 /* new intermediate page table entry */
1304 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1306 panic("pmap_growkernel: no memory to grow kernel");
1307 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1308 continue; /* try again */
1311 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
1313 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1314 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1315 kernel_vm_end = vm_map_max(kernel_map);
1322 * This index is bogus, but out of the way
1324 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1326 if (nkpg == NULL && vm_page_reclaim_contig(req_class, 1,
1327 0, MIPS_KSEG0_LARGEST_PHYS, PAGE_SIZE, 0))
1328 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1331 panic("pmap_growkernel: no memory to grow kernel");
1333 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1336 * The R[4-7]?00 stores only one copy of the Global bit in
1337 * the translation lookaside buffer for each 2 page entry.
1338 * Thus invalid entrys must have the Global bit set so when
1339 * Entry LO and Entry HI G bits are anded together they will
1340 * produce a global bit to store in the tlb.
1342 pte = (pt_entry_t *)*pde;
1343 for (i = 0; i < NPTEPG; i++)
1346 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1347 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1348 kernel_vm_end = vm_map_max(kernel_map);
1354 /***************************************************
1355 * page management routines.
1356 ***************************************************/
1358 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1360 CTASSERT(_NPCM == 3);
1361 CTASSERT(_NPCPV == 168);
1363 CTASSERT(_NPCM == 11);
1364 CTASSERT(_NPCPV == 336);
1367 static __inline struct pv_chunk *
1368 pv_to_chunk(pv_entry_t pv)
1371 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1374 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1377 #define PC_FREE0_1 0xfffffffffffffffful
1378 #define PC_FREE2 0x000000fffffffffful
1380 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
1381 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
1384 static const u_long pc_freemask[_NPCM] = {
1386 PC_FREE0_1, PC_FREE0_1, PC_FREE2
1388 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1389 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1390 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1391 PC_FREE0_9, PC_FREE10
1395 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1397 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1398 "Current number of pv entries");
1401 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1403 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1404 "Current number of pv entry chunks");
1405 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1406 "Current number of pv entry chunks allocated");
1407 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1408 "Current number of pv entry chunks frees");
1409 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1410 "Number of times tried to get a chunk page but failed.");
1412 static long pv_entry_frees, pv_entry_allocs;
1413 static int pv_entry_spare;
1415 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1416 "Current number of pv entry frees");
1417 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1418 "Current number of pv entry allocs");
1419 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1420 "Current number of spare pv entries");
1424 * We are in a serious low memory condition. Resort to
1425 * drastic measures to free some pages so we can allocate
1426 * another pv entry chunk.
1429 pmap_pv_reclaim(pmap_t locked_pmap)
1432 struct pv_chunk *pc;
1435 pt_entry_t *pte, oldpte;
1440 int bit, field, freed, idx;
1442 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1445 TAILQ_INIT(&newtail);
1446 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) {
1447 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1448 if (pmap != pc->pc_pmap) {
1450 pmap_invalidate_all(pmap);
1451 if (pmap != locked_pmap)
1455 /* Avoid deadlock and lock recursion. */
1456 if (pmap > locked_pmap)
1458 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
1460 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1466 * Destroy every non-wired, 4 KB page mapping in the chunk.
1469 for (field = 0; field < _NPCM; field++) {
1470 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1471 inuse != 0; inuse &= ~(1UL << bit)) {
1472 bit = ffsl(inuse) - 1;
1473 idx = field * sizeof(inuse) * NBBY + bit;
1474 pv = &pc->pc_pventry[idx];
1476 pde = pmap_pde(pmap, va);
1477 KASSERT(pde != NULL && *pde != 0,
1478 ("pmap_pv_reclaim: pde"));
1479 pte = pmap_pde_to_pte(pde, va);
1481 if (pte_test(&oldpte, PTE_W))
1483 if (is_kernel_pmap(pmap))
1487 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte));
1488 if (pte_test(&oldpte, PTE_D))
1490 if (m->md.pv_flags & PV_TABLE_REF)
1491 vm_page_aflag_set(m, PGA_REFERENCED);
1492 m->md.pv_flags &= ~PV_TABLE_REF;
1493 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1494 if (TAILQ_EMPTY(&m->md.pv_list))
1495 vm_page_aflag_clear(m, PGA_WRITEABLE);
1496 pc->pc_map[field] |= 1UL << bit;
1497 pmap_unuse_pt(pmap, va, *pde);
1502 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1505 /* Every freed mapping is for a 4 KB page. */
1506 pmap->pm_stats.resident_count -= freed;
1507 PV_STAT(pv_entry_frees += freed);
1508 PV_STAT(pv_entry_spare += freed);
1509 pv_entry_count -= freed;
1510 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1511 for (field = 0; field < _NPCM; field++)
1512 if (pc->pc_map[field] != pc_freemask[field]) {
1513 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1515 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1518 * One freed pv entry in locked_pmap is
1521 if (pmap == locked_pmap)
1525 if (field == _NPCM) {
1526 PV_STAT(pv_entry_spare -= _NPCPV);
1527 PV_STAT(pc_chunk_count--);
1528 PV_STAT(pc_chunk_frees++);
1529 /* Entire chunk is free; return it. */
1530 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(
1532 dump_drop_page(m_pc->phys_addr);
1537 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
1539 pmap_invalidate_all(pmap);
1540 if (pmap != locked_pmap)
1547 * free the pv_entry back to the free list
1550 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1552 struct pv_chunk *pc;
1553 int bit, field, idx;
1555 rw_assert(&pvh_global_lock, RA_WLOCKED);
1556 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1557 PV_STAT(pv_entry_frees++);
1558 PV_STAT(pv_entry_spare++);
1560 pc = pv_to_chunk(pv);
1561 idx = pv - &pc->pc_pventry[0];
1562 field = idx / (sizeof(u_long) * NBBY);
1563 bit = idx % (sizeof(u_long) * NBBY);
1564 pc->pc_map[field] |= 1ul << bit;
1565 for (idx = 0; idx < _NPCM; idx++)
1566 if (pc->pc_map[idx] != pc_freemask[idx]) {
1568 * 98% of the time, pc is already at the head of the
1569 * list. If it isn't already, move it to the head.
1571 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
1573 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1574 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1579 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1584 free_pv_chunk(struct pv_chunk *pc)
1588 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1589 PV_STAT(pv_entry_spare -= _NPCPV);
1590 PV_STAT(pc_chunk_count--);
1591 PV_STAT(pc_chunk_frees++);
1592 /* entire chunk is free, return it */
1593 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc));
1594 dump_drop_page(m->phys_addr);
1595 vm_page_unwire_noq(m);
1600 * get a new pv_entry, allocating a block from the system
1604 get_pv_entry(pmap_t pmap, boolean_t try)
1606 struct pv_chunk *pc;
1609 int bit, field, idx;
1611 rw_assert(&pvh_global_lock, RA_WLOCKED);
1612 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1613 PV_STAT(pv_entry_allocs++);
1616 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1618 for (field = 0; field < _NPCM; field++) {
1619 if (pc->pc_map[field]) {
1620 bit = ffsl(pc->pc_map[field]) - 1;
1624 if (field < _NPCM) {
1625 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
1626 pv = &pc->pc_pventry[idx];
1627 pc->pc_map[field] &= ~(1ul << bit);
1628 /* If this was the last item, move it to tail */
1629 for (field = 0; field < _NPCM; field++)
1630 if (pc->pc_map[field] != 0) {
1631 PV_STAT(pv_entry_spare--);
1632 return (pv); /* not full, return */
1634 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1635 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
1636 PV_STAT(pv_entry_spare--);
1640 /* No free items, allocate another chunk */
1641 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL |
1646 PV_STAT(pc_chunk_tryfail++);
1649 m = pmap_pv_reclaim(pmap);
1653 PV_STAT(pc_chunk_count++);
1654 PV_STAT(pc_chunk_allocs++);
1655 dump_add_page(m->phys_addr);
1656 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1658 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
1659 for (field = 1; field < _NPCM; field++)
1660 pc->pc_map[field] = pc_freemask[field];
1661 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1662 pv = &pc->pc_pventry[0];
1663 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1664 PV_STAT(pv_entry_spare += _NPCPV - 1);
1669 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1673 rw_assert(&pvh_global_lock, RA_WLOCKED);
1674 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
1675 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1676 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
1684 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1688 pv = pmap_pvh_remove(pvh, pmap, va);
1689 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx",
1690 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)),
1692 free_pv_entry(pmap, pv);
1696 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
1699 rw_assert(&pvh_global_lock, RA_WLOCKED);
1700 pmap_pvh_free(&m->md, pmap, va);
1701 if (TAILQ_EMPTY(&m->md.pv_list))
1702 vm_page_aflag_clear(m, PGA_WRITEABLE);
1706 * Conditionally create a pv entry.
1709 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va,
1714 rw_assert(&pvh_global_lock, RA_WLOCKED);
1715 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1716 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
1718 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
1725 * pmap_remove_pte: do the things to unmap a page in a process
1728 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
1735 rw_assert(&pvh_global_lock, RA_WLOCKED);
1736 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1739 * Write back all cache lines from the page being unmapped.
1741 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
1744 if (is_kernel_pmap(pmap))
1749 if (pte_test(&oldpte, PTE_W))
1750 pmap->pm_stats.wired_count -= 1;
1752 pmap->pm_stats.resident_count -= 1;
1754 if (pte_test(&oldpte, PTE_MANAGED)) {
1755 pa = TLBLO_PTE_TO_PA(oldpte);
1756 m = PHYS_TO_VM_PAGE(pa);
1757 if (pte_test(&oldpte, PTE_D)) {
1758 KASSERT(!pte_test(&oldpte, PTE_RO),
1759 ("%s: modified page not writable: va: %p, pte: %#jx",
1760 __func__, (void *)va, (uintmax_t)oldpte));
1763 if (m->md.pv_flags & PV_TABLE_REF)
1764 vm_page_aflag_set(m, PGA_REFERENCED);
1765 m->md.pv_flags &= ~PV_TABLE_REF;
1767 pmap_remove_entry(pmap, m, va);
1769 return (pmap_unuse_pt(pmap, va, pde));
1773 * Remove a single page from a process address space
1776 pmap_remove_page(struct pmap *pmap, vm_offset_t va)
1781 rw_assert(&pvh_global_lock, RA_WLOCKED);
1782 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1783 pde = pmap_pde(pmap, va);
1784 if (pde == NULL || *pde == 0)
1786 ptq = pmap_pde_to_pte(pde, va);
1789 * If there is no pte for this address, just skip it!
1791 if (!pte_test(ptq, PTE_V))
1794 (void)pmap_remove_pte(pmap, ptq, va, *pde);
1795 pmap_invalidate_page(pmap, va);
1799 * Remove the given range of addresses from the specified map.
1801 * It is assumed that the start and end are properly
1802 * rounded to the page size.
1805 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1807 pd_entry_t *pde, *pdpe;
1809 vm_offset_t va, va_next;
1812 * Perform an unsynchronized read. This is, however, safe.
1814 if (pmap->pm_stats.resident_count == 0)
1817 rw_wlock(&pvh_global_lock);
1821 * special handling of removing one page. a very common operation
1822 * and easy to short circuit some code.
1824 if ((sva + PAGE_SIZE) == eva) {
1825 pmap_remove_page(pmap, sva);
1828 for (; sva < eva; sva = va_next) {
1829 pdpe = pmap_segmap(pmap, sva);
1832 va_next = (sva + NBSEG) & ~SEGMASK;
1838 va_next = (sva + NBPDR) & ~PDRMASK;
1842 pde = pmap_pdpe_to_pde(pdpe, sva);
1847 * Limit our scan to either the end of the va represented
1848 * by the current page table page, or to the end of the
1849 * range being removed.
1855 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1857 if (!pte_test(pte, PTE_V)) {
1858 if (va != va_next) {
1859 pmap_invalidate_range(pmap, va, sva);
1866 if (pmap_remove_pte(pmap, pte, sva, *pde)) {
1872 pmap_invalidate_range(pmap, va, sva);
1875 rw_wunlock(&pvh_global_lock);
1880 * Routine: pmap_remove_all
1882 * Removes this physical page from
1883 * all physical maps in which it resides.
1884 * Reflects back modify bits to the pager.
1887 * Original versions of this routine were very
1888 * inefficient because they iteratively called
1889 * pmap_remove (slow...)
1893 pmap_remove_all(vm_page_t m)
1898 pt_entry_t *pte, tpte;
1900 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1901 ("pmap_remove_all: page %p is not managed", m));
1902 rw_wlock(&pvh_global_lock);
1904 if (m->md.pv_flags & PV_TABLE_REF)
1905 vm_page_aflag_set(m, PGA_REFERENCED);
1907 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
1912 * If it's last mapping writeback all caches from
1913 * the page being destroyed
1915 if (TAILQ_NEXT(pv, pv_list) == NULL)
1916 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
1918 pmap->pm_stats.resident_count--;
1920 pde = pmap_pde(pmap, pv->pv_va);
1921 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde"));
1922 pte = pmap_pde_to_pte(pde, pv->pv_va);
1925 if (is_kernel_pmap(pmap))
1930 if (pte_test(&tpte, PTE_W))
1931 pmap->pm_stats.wired_count--;
1934 * Update the vm_page_t clean and reference bits.
1936 if (pte_test(&tpte, PTE_D)) {
1937 KASSERT(!pte_test(&tpte, PTE_RO),
1938 ("%s: modified page not writable: va: %p, pte: %#jx",
1939 __func__, (void *)pv->pv_va, (uintmax_t)tpte));
1942 pmap_invalidate_page(pmap, pv->pv_va);
1944 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1945 pmap_unuse_pt(pmap, pv->pv_va, *pde);
1946 free_pv_entry(pmap, pv);
1950 vm_page_aflag_clear(m, PGA_WRITEABLE);
1951 m->md.pv_flags &= ~PV_TABLE_REF;
1952 rw_wunlock(&pvh_global_lock);
1956 * Set the physical protection on the
1957 * specified range of this map as requested.
1960 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1962 pt_entry_t pbits, *pte;
1963 pd_entry_t *pde, *pdpe;
1964 vm_offset_t va, va_next;
1968 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1969 pmap_remove(pmap, sva, eva);
1972 if (prot & VM_PROT_WRITE)
1976 for (; sva < eva; sva = va_next) {
1977 pdpe = pmap_segmap(pmap, sva);
1980 va_next = (sva + NBSEG) & ~SEGMASK;
1986 va_next = (sva + NBPDR) & ~PDRMASK;
1990 pde = pmap_pdpe_to_pde(pdpe, sva);
1995 * Limit our scan to either the end of the va represented
1996 * by the current page table page, or to the end of the
1997 * range being write protected.
2003 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2006 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits,
2008 if (va != va_next) {
2009 pmap_invalidate_range(pmap, va, sva);
2014 pte_set(&pbits, PTE_RO);
2015 if (pte_test(&pbits, PTE_D)) {
2016 pte_clear(&pbits, PTE_D);
2017 if (pte_test(&pbits, PTE_MANAGED)) {
2018 pa = TLBLO_PTE_TO_PA(pbits);
2019 m = PHYS_TO_VM_PAGE(pa);
2026 * Unless PTE_D is set, any TLB entries
2027 * mapping "sva" don't allow write access, so
2028 * they needn't be invalidated.
2030 if (va != va_next) {
2031 pmap_invalidate_range(pmap, va, sva);
2038 pmap_invalidate_range(pmap, va, sva);
2044 * Insert the given physical page (p) at
2045 * the specified virtual address (v) in the
2046 * target physical map with the protection requested.
2048 * If specified, the page will be wired down, meaning
2049 * that the related pte can not be reclaimed.
2051 * NB: This is the only routine which MAY NOT lazy-evaluate
2052 * or lose information. That is, this routine must actually
2053 * insert this page into the given map NOW.
2056 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2057 u_int flags, int8_t psind __unused)
2061 pt_entry_t origpte, newpte;
2066 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2067 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
2068 va >= kmi.clean_eva,
2069 ("pmap_enter: managed mapping within the clean submap"));
2070 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2071 VM_OBJECT_ASSERT_LOCKED(m->object);
2072 pa = VM_PAGE_TO_PHYS(m);
2073 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot);
2074 if ((flags & PMAP_ENTER_WIRED) != 0)
2076 if (is_kernel_pmap(pmap))
2078 PMAP_PTE_SET_CACHE_BITS(newpte, pa, m);
2079 if ((m->oflags & VPO_UNMANAGED) == 0)
2080 newpte |= PTE_MANAGED;
2084 rw_wlock(&pvh_global_lock);
2088 * In the case that a page table page is not resident, we are
2091 if (va < VM_MAXUSER_ADDRESS) {
2092 mpte = pmap_allocpte(pmap, va, flags);
2094 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
2095 ("pmap_allocpte failed with sleep allowed"));
2096 rw_wunlock(&pvh_global_lock);
2098 return (KERN_RESOURCE_SHORTAGE);
2101 pte = pmap_pte(pmap, va);
2104 * Page Directory table entry not valid, we need a new PT page
2107 panic("pmap_enter: invalid page directory, pdir=%p, va=%p",
2108 (void *)pmap->pm_segtab, (void *)va);
2112 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO | PTE_V),
2113 ("pmap_enter: modified page not writable: va: %p, pte: %#jx",
2114 (void *)va, (uintmax_t)origpte));
2115 opa = TLBLO_PTE_TO_PA(origpte);
2118 * Mapping has not changed, must be protection or wiring change.
2120 if (pte_test(&origpte, PTE_V) && opa == pa) {
2122 * Wiring change, just update stats. We don't worry about
2123 * wiring PT pages as they remain resident as long as there
2124 * are valid mappings in them. Hence, if a user page is
2125 * wired, the PT page will be also.
2127 if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W))
2128 pmap->pm_stats.wired_count++;
2129 else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte,
2131 pmap->pm_stats.wired_count--;
2134 * Remove extra pte reference
2139 if (pte_test(&origpte, PTE_MANAGED)) {
2140 m->md.pv_flags |= PV_TABLE_REF;
2141 if (!pte_test(&newpte, PTE_RO))
2142 vm_page_aflag_set(m, PGA_WRITEABLE);
2150 * Mapping has changed, invalidate old range and fall through to
2151 * handle validating new mapping.
2154 if (is_kernel_pmap(pmap))
2158 if (pte_test(&origpte, PTE_W))
2159 pmap->pm_stats.wired_count--;
2160 if (pte_test(&origpte, PTE_MANAGED)) {
2161 om = PHYS_TO_VM_PAGE(opa);
2162 if (pte_test(&origpte, PTE_D))
2164 if ((om->md.pv_flags & PV_TABLE_REF) != 0) {
2165 om->md.pv_flags &= ~PV_TABLE_REF;
2166 vm_page_aflag_set(om, PGA_REFERENCED);
2168 pv = pmap_pvh_remove(&om->md, pmap, va);
2169 if (!pte_test(&newpte, PTE_MANAGED))
2170 free_pv_entry(pmap, pv);
2171 if ((om->aflags & PGA_WRITEABLE) != 0 &&
2172 TAILQ_EMPTY(&om->md.pv_list))
2173 vm_page_aflag_clear(om, PGA_WRITEABLE);
2175 pmap_invalidate_page(pmap, va);
2179 KASSERT(mpte->wire_count > 0,
2180 ("pmap_enter: missing reference to page table page,"
2181 " va: %p", (void *)va));
2184 pmap->pm_stats.resident_count++;
2187 * Enter on the PV list if part of our managed memory.
2189 if (pte_test(&newpte, PTE_MANAGED)) {
2190 m->md.pv_flags |= PV_TABLE_REF;
2192 pv = get_pv_entry(pmap, FALSE);
2195 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2196 if (!pte_test(&newpte, PTE_RO))
2197 vm_page_aflag_set(m, PGA_WRITEABLE);
2201 * Increment counters
2203 if (pte_test(&newpte, PTE_W))
2204 pmap->pm_stats.wired_count++;
2209 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
2213 * if the mapping or permission bits are different, we need to
2216 if (origpte != newpte) {
2218 if (pte_test(&origpte, PTE_V)) {
2219 KASSERT(opa == pa, ("pmap_enter: invalid update"));
2220 if (pte_test(&origpte, PTE_D)) {
2221 if (pte_test(&origpte, PTE_MANAGED))
2224 pmap_update_page(pmap, va, newpte);
2229 * Sync I & D caches for executable pages. Do this only if the
2230 * target pmap belongs to the current process. Otherwise, an
2231 * unresolvable TLB miss may occur.
2233 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
2234 (prot & VM_PROT_EXECUTE)) {
2235 mips_icache_sync_range(va, PAGE_SIZE);
2236 mips_dcache_wbinv_range(va, PAGE_SIZE);
2238 rw_wunlock(&pvh_global_lock);
2240 return (KERN_SUCCESS);
2244 * this code makes some *MAJOR* assumptions:
2245 * 1. Current pmap & pmap exists.
2248 * 4. No page table pages.
2249 * but is *MUCH* faster than pmap_enter...
2253 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2256 rw_wlock(&pvh_global_lock);
2258 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
2259 rw_wunlock(&pvh_global_lock);
2264 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2265 vm_prot_t prot, vm_page_t mpte)
2267 pt_entry_t *pte, npte;
2270 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2271 (m->oflags & VPO_UNMANAGED) != 0,
2272 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2273 rw_assert(&pvh_global_lock, RA_WLOCKED);
2274 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2277 * In the case that a page table page is not resident, we are
2280 if (va < VM_MAXUSER_ADDRESS) {
2285 * Calculate pagetable page index
2287 ptepindex = pmap_pde_pindex(va);
2288 if (mpte && (mpte->pindex == ptepindex)) {
2292 * Get the page directory entry
2294 pde = pmap_pde(pmap, va);
2297 * If the page table page is mapped, we just
2298 * increment the hold count, and activate it.
2300 if (pde && *pde != 0) {
2301 mpte = PHYS_TO_VM_PAGE(
2302 MIPS_DIRECT_TO_PHYS(*pde));
2305 mpte = _pmap_allocpte(pmap, ptepindex,
2306 PMAP_ENTER_NOSLEEP);
2315 pte = pmap_pte(pmap, va);
2316 if (pte_test(pte, PTE_V)) {
2325 * Enter on the PV list if part of our managed memory.
2327 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2328 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) {
2330 pmap_unwire_ptp(pmap, va, mpte);
2337 * Increment counters
2339 pmap->pm_stats.resident_count++;
2341 pa = VM_PAGE_TO_PHYS(m);
2344 * Now validate mapping with RO protection
2346 npte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V;
2347 if ((m->oflags & VPO_UNMANAGED) == 0)
2348 npte |= PTE_MANAGED;
2350 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2352 if (is_kernel_pmap(pmap))
2353 *pte = npte | PTE_G;
2357 * Sync I & D caches. Do this only if the target pmap
2358 * belongs to the current process. Otherwise, an
2359 * unresolvable TLB miss may occur. */
2360 if (pmap == &curproc->p_vmspace->vm_pmap) {
2362 mips_icache_sync_range(va, PAGE_SIZE);
2363 mips_dcache_wbinv_range(va, PAGE_SIZE);
2370 * Make a temporary mapping for a physical address. This is only intended
2371 * to be used for panic dumps.
2373 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2376 pmap_kenter_temporary(vm_paddr_t pa, int i)
2381 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
2384 if (MIPS_DIRECT_MAPPABLE(pa)) {
2385 va = MIPS_PHYS_TO_DIRECT(pa);
2387 #ifndef __mips_n64 /* XXX : to be converted to new style */
2390 struct local_sysmaps *sysm;
2391 pt_entry_t *pte, npte;
2393 /* If this is used other than for dumps, we may need to leave
2394 * interrupts disasbled on return. If crash dumps don't work when
2395 * we get to this point, we might want to consider this (leaving things
2396 * disabled as a starting point ;-)
2398 intr = intr_disable();
2399 cpu = PCPU_GET(cpuid);
2400 sysm = &sysmap_lmem[cpu];
2401 /* Since this is for the debugger, no locks or any other fun */
2402 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
2404 pte = pmap_pte(kernel_pmap, sysm->base);
2407 pmap_update_page(kernel_pmap, sysm->base, npte);
2412 return ((void *)va);
2416 pmap_kenter_temporary_free(vm_paddr_t pa)
2418 #ifndef __mips_n64 /* XXX : to be converted to new style */
2421 struct local_sysmaps *sysm;
2424 if (MIPS_DIRECT_MAPPABLE(pa)) {
2425 /* nothing to do for this case */
2428 #ifndef __mips_n64 /* XXX : to be converted to new style */
2429 cpu = PCPU_GET(cpuid);
2430 sysm = &sysmap_lmem[cpu];
2434 intr = intr_disable();
2435 pte = pmap_pte(kernel_pmap, sysm->base);
2437 pmap_invalidate_page(kernel_pmap, sysm->base);
2445 * Maps a sequence of resident pages belonging to the same object.
2446 * The sequence begins with the given page m_start. This page is
2447 * mapped at the given virtual address start. Each subsequent page is
2448 * mapped at a virtual address that is offset from start by the same
2449 * amount as the page is offset from m_start within the object. The
2450 * last page in the sequence is the page with the largest offset from
2451 * m_start that can be mapped at a virtual address less than the given
2452 * virtual address end. Not every virtual page between start and end
2453 * is mapped; only those for which a resident page exists with the
2454 * corresponding offset from m_start are mapped.
2457 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2458 vm_page_t m_start, vm_prot_t prot)
2461 vm_pindex_t diff, psize;
2463 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2465 psize = atop(end - start);
2468 rw_wlock(&pvh_global_lock);
2470 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2471 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m,
2473 m = TAILQ_NEXT(m, listq);
2475 rw_wunlock(&pvh_global_lock);
2480 * pmap_object_init_pt preloads the ptes for a given object
2481 * into the specified pmap. This eliminates the blast of soft
2482 * faults on process startup and immediately after an mmap.
2485 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
2486 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2488 VM_OBJECT_ASSERT_WLOCKED(object);
2489 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2490 ("pmap_object_init_pt: non-device object"));
2494 * Clear the wired attribute from the mappings for the specified range of
2495 * addresses in the given pmap. Every valid mapping within that range
2496 * must have the wired attribute set. In contrast, invalid mappings
2497 * cannot have the wired attribute set, so they are ignored.
2499 * The wired attribute of the page table entry is not a hardware feature,
2500 * so there is no need to invalidate any TLB entries.
2503 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2505 pd_entry_t *pde, *pdpe;
2507 vm_offset_t va_next;
2510 for (; sva < eva; sva = va_next) {
2511 pdpe = pmap_segmap(pmap, sva);
2513 if (*pdpe == NULL) {
2514 va_next = (sva + NBSEG) & ~SEGMASK;
2520 va_next = (sva + NBPDR) & ~PDRMASK;
2523 pde = pmap_pdpe_to_pde(pdpe, sva);
2528 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2530 if (!pte_test(pte, PTE_V))
2532 if (!pte_test(pte, PTE_W))
2533 panic("pmap_unwire: pte %#jx is missing PG_W",
2535 pte_clear(pte, PTE_W);
2536 pmap->pm_stats.wired_count--;
2543 * Copy the range specified by src_addr/len
2544 * from the source map to the range dst_addr/len
2545 * in the destination map.
2547 * This routine is only advisory and need not do anything.
2551 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2552 vm_size_t len, vm_offset_t src_addr)
2557 * pmap_zero_page zeros the specified hardware page by mapping
2558 * the page into KVM and using bzero to clear its contents.
2560 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2563 pmap_zero_page(vm_page_t m)
2566 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2568 if (MIPS_DIRECT_MAPPABLE(phys)) {
2569 va = MIPS_PHYS_TO_DIRECT(phys);
2570 bzero((caddr_t)va, PAGE_SIZE);
2571 mips_dcache_wbinv_range(va, PAGE_SIZE);
2573 va = pmap_lmem_map1(phys);
2574 bzero((caddr_t)va, PAGE_SIZE);
2575 mips_dcache_wbinv_range(va, PAGE_SIZE);
2581 * pmap_zero_page_area zeros the specified hardware page by mapping
2582 * the page into KVM and using bzero to clear its contents.
2584 * off and size may not cover an area beyond a single hardware page.
2587 pmap_zero_page_area(vm_page_t m, int off, int size)
2590 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2592 if (MIPS_DIRECT_MAPPABLE(phys)) {
2593 va = MIPS_PHYS_TO_DIRECT(phys);
2594 bzero((char *)(caddr_t)va + off, size);
2595 mips_dcache_wbinv_range(va + off, size);
2597 va = pmap_lmem_map1(phys);
2598 bzero((char *)va + off, size);
2599 mips_dcache_wbinv_range(va + off, size);
2605 * pmap_copy_page copies the specified (machine independent)
2606 * page by mapping the page into virtual memory and using
2607 * bcopy to copy the page, one machine dependent page at a
2610 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2613 pmap_copy_page(vm_page_t src, vm_page_t dst)
2615 vm_offset_t va_src, va_dst;
2616 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src);
2617 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst);
2619 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) {
2620 /* easy case, all can be accessed via KSEG0 */
2622 * Flush all caches for VA that are mapped to this page
2623 * to make sure that data in SDRAM is up to date
2625 pmap_flush_pvcache(src);
2626 mips_dcache_wbinv_range_index(
2627 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE);
2628 va_src = MIPS_PHYS_TO_DIRECT(phys_src);
2629 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst);
2630 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
2631 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2633 va_src = pmap_lmem_map2(phys_src, phys_dst);
2634 va_dst = va_src + PAGE_SIZE;
2635 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE);
2636 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2641 int unmapped_buf_allowed;
2644 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2645 vm_offset_t b_offset, int xfersize)
2649 vm_offset_t a_pg_offset, b_pg_offset;
2650 vm_paddr_t a_phys, b_phys;
2653 while (xfersize > 0) {
2654 a_pg_offset = a_offset & PAGE_MASK;
2655 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2656 a_m = ma[a_offset >> PAGE_SHIFT];
2657 a_phys = VM_PAGE_TO_PHYS(a_m);
2658 b_pg_offset = b_offset & PAGE_MASK;
2659 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2660 b_m = mb[b_offset >> PAGE_SHIFT];
2661 b_phys = VM_PAGE_TO_PHYS(b_m);
2662 if (MIPS_DIRECT_MAPPABLE(a_phys) &&
2663 MIPS_DIRECT_MAPPABLE(b_phys)) {
2664 pmap_flush_pvcache(a_m);
2665 mips_dcache_wbinv_range_index(
2666 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE);
2667 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) +
2669 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) +
2671 bcopy(a_cp, b_cp, cnt);
2672 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2674 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys);
2675 b_cp = (char *)a_cp + PAGE_SIZE;
2676 a_cp += a_pg_offset;
2677 b_cp += b_pg_offset;
2678 bcopy(a_cp, b_cp, cnt);
2679 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2689 pmap_quick_enter_page(vm_page_t m)
2691 #if defined(__mips_n64)
2692 return MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
2695 struct local_sysmaps *sysm;
2696 pt_entry_t *pte, npte;
2698 pa = VM_PAGE_TO_PHYS(m);
2700 if (MIPS_DIRECT_MAPPABLE(pa)) {
2701 if (pmap_page_get_memattr(m) != VM_MEMATTR_WRITE_BACK)
2702 return (MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
2704 return (MIPS_PHYS_TO_DIRECT(pa));
2707 sysm = &sysmap_lmem[PCPU_GET(cpuid)];
2709 KASSERT(sysm->valid1 == 0, ("pmap_quick_enter_page: PTE busy"));
2711 pte = pmap_pte(kernel_pmap, sysm->base);
2712 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G;
2713 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2717 return (sysm->base);
2722 pmap_quick_remove_page(vm_offset_t addr)
2724 mips_dcache_wbinv_range(addr, PAGE_SIZE);
2726 #if !defined(__mips_n64)
2727 struct local_sysmaps *sysm;
2730 if (addr >= MIPS_KSEG0_START && addr < MIPS_KSEG0_END)
2733 sysm = &sysmap_lmem[PCPU_GET(cpuid)];
2735 KASSERT(sysm->valid1 != 0,
2736 ("pmap_quick_remove_page: PTE not in use"));
2737 KASSERT(sysm->base == addr,
2738 ("pmap_quick_remove_page: invalid address"));
2740 pte = pmap_pte(kernel_pmap, addr);
2742 tlb_invalidate_address(kernel_pmap, addr);
2749 * Returns true if the pmap's pv is one of the first
2750 * 16 pvs linked to from this page. This count may
2751 * be changed upwards or downwards in the future; it
2752 * is only necessary that true be returned for a small
2753 * subset of pmaps for proper page aging.
2756 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2762 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2763 ("pmap_page_exists_quick: page %p is not managed", m));
2765 rw_wlock(&pvh_global_lock);
2766 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2767 if (PV_PMAP(pv) == pmap) {
2775 rw_wunlock(&pvh_global_lock);
2780 * Remove all pages from specified address space
2781 * this aids process exit speeds. Also, this code
2782 * is special cased for current process only, but
2783 * can have the more generic (and slightly slower)
2784 * mode enabled. This is much faster than pmap_remove
2785 * in the case of running down an entire address space.
2788 pmap_remove_pages(pmap_t pmap)
2791 pt_entry_t *pte, tpte;
2794 struct pv_chunk *pc, *npc;
2795 u_long inuse, bitmask;
2796 int allfree, bit, field, idx;
2798 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
2799 printf("warning: pmap_remove_pages called with non-current pmap\n");
2802 rw_wlock(&pvh_global_lock);
2804 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2806 for (field = 0; field < _NPCM; field++) {
2807 inuse = ~pc->pc_map[field] & pc_freemask[field];
2808 while (inuse != 0) {
2809 bit = ffsl(inuse) - 1;
2810 bitmask = 1UL << bit;
2811 idx = field * sizeof(inuse) * NBBY + bit;
2812 pv = &pc->pc_pventry[idx];
2815 pde = pmap_pde(pmap, pv->pv_va);
2816 KASSERT(pde != NULL && *pde != 0,
2817 ("pmap_remove_pages: pde"));
2818 pte = pmap_pde_to_pte(pde, pv->pv_va);
2819 if (!pte_test(pte, PTE_V))
2820 panic("pmap_remove_pages: bad pte");
2824 * We cannot remove wired pages from a process' mapping at this time
2826 if (pte_test(&tpte, PTE_W)) {
2830 *pte = is_kernel_pmap(pmap) ? PTE_G : 0;
2832 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte));
2834 ("pmap_remove_pages: bad tpte %#jx",
2838 * Update the vm_page_t clean and reference bits.
2840 if (pte_test(&tpte, PTE_D))
2844 PV_STAT(pv_entry_frees++);
2845 PV_STAT(pv_entry_spare++);
2847 pc->pc_map[field] |= bitmask;
2848 pmap->pm_stats.resident_count--;
2849 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2850 if (TAILQ_EMPTY(&m->md.pv_list))
2851 vm_page_aflag_clear(m, PGA_WRITEABLE);
2852 pmap_unuse_pt(pmap, pv->pv_va, *pde);
2856 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2860 pmap_invalidate_all(pmap);
2862 rw_wunlock(&pvh_global_lock);
2866 * pmap_testbit tests bits in pte's
2869 pmap_testbit(vm_page_t m, int bit)
2874 boolean_t rv = FALSE;
2876 if (m->oflags & VPO_UNMANAGED)
2879 rw_assert(&pvh_global_lock, RA_WLOCKED);
2880 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2883 pte = pmap_pte(pmap, pv->pv_va);
2884 rv = pte_test(pte, bit);
2893 * pmap_page_wired_mappings:
2895 * Return the number of managed mappings to the given physical page
2899 pmap_page_wired_mappings(vm_page_t m)
2907 if ((m->oflags & VPO_UNMANAGED) != 0)
2909 rw_wlock(&pvh_global_lock);
2910 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2913 pte = pmap_pte(pmap, pv->pv_va);
2914 if (pte_test(pte, PTE_W))
2918 rw_wunlock(&pvh_global_lock);
2923 * Clear the write and modified bits in each of the given page's mappings.
2926 pmap_remove_write(vm_page_t m)
2929 pt_entry_t pbits, *pte;
2932 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2933 ("pmap_remove_write: page %p is not managed", m));
2936 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2937 * set by another thread while the object is locked. Thus,
2938 * if PGA_WRITEABLE is clear, no page table entries need updating.
2940 VM_OBJECT_ASSERT_WLOCKED(m->object);
2941 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2943 rw_wlock(&pvh_global_lock);
2944 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2947 pte = pmap_pte(pmap, pv->pv_va);
2948 KASSERT(pte != NULL && pte_test(pte, PTE_V),
2949 ("page on pv_list has no pte"));
2951 if (pte_test(&pbits, PTE_D)) {
2952 pte_clear(&pbits, PTE_D);
2955 pte_set(&pbits, PTE_RO);
2956 if (pbits != *pte) {
2958 pmap_update_page(pmap, pv->pv_va, pbits);
2962 vm_page_aflag_clear(m, PGA_WRITEABLE);
2963 rw_wunlock(&pvh_global_lock);
2967 * pmap_ts_referenced:
2969 * Return the count of reference bits for a page, clearing all of them.
2972 pmap_ts_referenced(vm_page_t m)
2975 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2976 ("pmap_ts_referenced: page %p is not managed", m));
2977 if (m->md.pv_flags & PV_TABLE_REF) {
2978 rw_wlock(&pvh_global_lock);
2979 m->md.pv_flags &= ~PV_TABLE_REF;
2980 rw_wunlock(&pvh_global_lock);
2989 * Return whether or not the specified physical page was modified
2990 * in any physical maps.
2993 pmap_is_modified(vm_page_t m)
2997 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2998 ("pmap_is_modified: page %p is not managed", m));
3001 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3002 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3003 * is clear, no PTEs can have PTE_D set.
3005 VM_OBJECT_ASSERT_WLOCKED(m->object);
3006 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3008 rw_wlock(&pvh_global_lock);
3009 rv = pmap_testbit(m, PTE_D);
3010 rw_wunlock(&pvh_global_lock);
3017 * pmap_is_prefaultable:
3019 * Return whether or not the specified virtual address is elgible
3023 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3031 pde = pmap_pde(pmap, addr);
3032 if (pde != NULL && *pde != 0) {
3033 pte = pmap_pde_to_pte(pde, addr);
3041 * Apply the given advice to the specified range of addresses within the
3042 * given pmap. Depending on the advice, clear the referenced and/or
3043 * modified flags in each mapping and set the mapped page's dirty field.
3046 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3048 pd_entry_t *pde, *pdpe;
3050 vm_offset_t va, va_next;
3054 if (advice != MADV_DONTNEED && advice != MADV_FREE)
3056 rw_wlock(&pvh_global_lock);
3058 for (; sva < eva; sva = va_next) {
3059 pdpe = pmap_segmap(pmap, sva);
3062 va_next = (sva + NBSEG) & ~SEGMASK;
3068 va_next = (sva + NBPDR) & ~PDRMASK;
3072 pde = pmap_pdpe_to_pde(pdpe, sva);
3077 * Limit our scan to either the end of the va represented
3078 * by the current page table page, or to the end of the
3079 * range being write protected.
3085 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3087 if (!pte_test(pte, PTE_MANAGED | PTE_V)) {
3088 if (va != va_next) {
3089 pmap_invalidate_range(pmap, va, sva);
3094 pa = TLBLO_PTE_TO_PA(*pte);
3095 m = PHYS_TO_VM_PAGE(pa);
3096 m->md.pv_flags &= ~PV_TABLE_REF;
3097 if (pte_test(pte, PTE_D)) {
3098 if (advice == MADV_DONTNEED) {
3100 * Future calls to pmap_is_modified()
3101 * can be avoided by making the page
3106 pte_clear(pte, PTE_D);
3112 * Unless PTE_D is set, any TLB entries
3113 * mapping "sva" don't allow write access, so
3114 * they needn't be invalidated.
3116 if (va != va_next) {
3117 pmap_invalidate_range(pmap, va, sva);
3123 pmap_invalidate_range(pmap, va, sva);
3125 rw_wunlock(&pvh_global_lock);
3130 * Clear the modify bits on the specified physical page.
3133 pmap_clear_modify(vm_page_t m)
3139 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3140 ("pmap_clear_modify: page %p is not managed", m));
3141 VM_OBJECT_ASSERT_WLOCKED(m->object);
3142 KASSERT(!vm_page_xbusied(m),
3143 ("pmap_clear_modify: page %p is exclusive busied", m));
3146 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set.
3147 * If the object containing the page is locked and the page is not
3148 * write busied, then PGA_WRITEABLE cannot be concurrently set.
3150 if ((m->aflags & PGA_WRITEABLE) == 0)
3152 rw_wlock(&pvh_global_lock);
3153 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3156 pte = pmap_pte(pmap, pv->pv_va);
3157 if (pte_test(pte, PTE_D)) {
3158 pte_clear(pte, PTE_D);
3159 pmap_update_page(pmap, pv->pv_va, *pte);
3163 rw_wunlock(&pvh_global_lock);
3167 * pmap_is_referenced:
3169 * Return whether or not the specified physical page was referenced
3170 * in any physical maps.
3173 pmap_is_referenced(vm_page_t m)
3176 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3177 ("pmap_is_referenced: page %p is not managed", m));
3178 return ((m->md.pv_flags & PV_TABLE_REF) != 0);
3182 * Miscellaneous support routines follow
3186 * Map a set of physical memory pages into the kernel virtual
3187 * address space. Return a pointer to where it is mapped. This
3188 * routine is intended to be used for mapping device memory,
3191 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit.
3194 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3196 vm_offset_t va, tmpva, offset;
3199 * KSEG1 maps only first 512M of phys address space. For
3200 * pa > 0x20000000 we should make proper mapping * using pmap_kenter.
3202 if (MIPS_DIRECT_MAPPABLE(pa + size - 1) && ma == VM_MEMATTR_UNCACHEABLE)
3203 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
3205 offset = pa & PAGE_MASK;
3206 size = roundup(size + offset, PAGE_SIZE);
3208 va = kva_alloc(size);
3210 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3211 pa = trunc_page(pa);
3212 for (tmpva = va; size > 0;) {
3213 pmap_kenter_attr(tmpva, pa, ma);
3220 return ((void *)(va + offset));
3224 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3226 return pmap_mapdev_attr(pa, size, VM_MEMATTR_UNCACHEABLE);
3230 pmap_unmapdev(vm_offset_t va, vm_size_t size)
3233 vm_offset_t base, offset;
3235 /* If the address is within KSEG1 then there is nothing to do */
3236 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
3239 base = trunc_page(va);
3240 offset = va & PAGE_MASK;
3241 size = roundup(size + offset, PAGE_SIZE);
3242 kva_free(base, size);
3247 * perform the pmap work for mincore
3250 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3252 pt_entry_t *ptep, pte;
3259 ptep = pmap_pte(pmap, addr);
3260 pte = (ptep != NULL) ? *ptep : 0;
3261 if (!pte_test(&pte, PTE_V)) {
3265 val = MINCORE_INCORE;
3266 if (pte_test(&pte, PTE_D))
3267 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3268 pa = TLBLO_PTE_TO_PA(pte);
3269 if (pte_test(&pte, PTE_MANAGED)) {
3271 * This may falsely report the given address as
3272 * MINCORE_REFERENCED. Unfortunately, due to the lack of
3273 * per-PTE reference information, it is impossible to
3274 * determine if the address is MINCORE_REFERENCED.
3276 m = PHYS_TO_VM_PAGE(pa);
3277 if ((m->aflags & PGA_REFERENCED) != 0)
3278 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3280 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3281 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
3282 pte_test(&pte, PTE_MANAGED)) {
3283 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3284 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3288 PA_UNLOCK_COND(*locked_pa);
3294 pmap_activate(struct thread *td)
3296 pmap_t pmap, oldpmap;
3297 struct proc *p = td->td_proc;
3302 pmap = vmspace_pmap(p->p_vmspace);
3303 oldpmap = PCPU_GET(curpmap);
3304 cpuid = PCPU_GET(cpuid);
3307 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
3308 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
3309 pmap_asid_alloc(pmap);
3310 if (td == curthread) {
3311 PCPU_SET(segbase, pmap->pm_segtab);
3312 mips_wr_entryhi(pmap->pm_asid[cpuid].asid);
3315 PCPU_SET(curpmap, pmap);
3320 pmap_sync_icache_one(void *arg __unused)
3323 mips_icache_sync_all();
3324 mips_dcache_wbinv_all();
3328 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3331 smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
3335 * Increase the starting virtual address of the given mapping if a
3336 * different alignment might result in more superpage mappings.
3339 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3340 vm_offset_t *addr, vm_size_t size)
3342 vm_offset_t superpage_offset;
3346 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
3347 offset += ptoa(object->pg_color);
3348 superpage_offset = offset & PDRMASK;
3349 if (size - ((PDRSIZE - superpage_offset) & PDRMASK) < PDRSIZE ||
3350 (*addr & PDRMASK) == superpage_offset)
3352 if ((*addr & PDRMASK) < superpage_offset)
3353 *addr = (*addr & ~PDRMASK) + superpage_offset;
3355 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
3359 DB_SHOW_COMMAND(ptable, ddb_pid_dump)
3362 struct thread *td = NULL;
3369 td = db_lookup_thread(addr, true);
3371 db_printf("Invalid pid or tid");
3375 if (p->p_vmspace == NULL) {
3376 db_printf("No vmspace for process");
3379 pmap = vmspace_pmap(p->p_vmspace);
3383 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n",
3384 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid,
3385 pmap->pm_asid[0].gen);
3386 for (i = 0; i < NPDEPG; i++) {
3391 pdpe = (pd_entry_t *)pmap->pm_segtab[i];
3394 db_printf("[%4d] %p\n", i, pdpe);
3396 for (j = 0; j < NPDEPG; j++) {
3397 pde = (pt_entry_t *)pdpe[j];
3400 db_printf("\t[%4d] %p\n", j, pde);
3404 pde = (pt_entry_t *)pdpe;
3406 for (k = 0; k < NPTEPG; k++) {
3408 if (pte == 0 || !pte_test(&pte, PTE_V))
3410 pa = TLBLO_PTE_TO_PA(pte);
3411 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT);
3412 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n",
3413 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa);
3421 * Allocate TLB address space tag (called ASID or TLBPID) and return it.
3422 * It takes almost as much or more time to search the TLB for a
3423 * specific ASID and flush those entries as it does to flush the entire TLB.
3424 * Therefore, when we allocate a new ASID, we just take the next number. When
3425 * we run out of numbers, we flush the TLB, increment the generation count
3426 * and start over. ASID zero is reserved for kernel use.
3429 pmap_asid_alloc(pmap)
3432 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED &&
3433 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
3435 if (PCPU_GET(next_asid) == pmap_max_asid) {
3436 tlb_invalidate_all_user(NULL);
3437 PCPU_SET(asid_generation,
3438 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
3439 if (PCPU_GET(asid_generation) == 0) {
3440 PCPU_SET(asid_generation, 1);
3442 PCPU_SET(next_asid, 1); /* 0 means invalid */
3444 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid);
3445 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation);
3446 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1);
3451 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot)
3455 if (!(prot & VM_PROT_WRITE))
3456 rw = PTE_V | PTE_RO;
3457 else if ((m->oflags & VPO_UNMANAGED) == 0) {
3458 if ((access & VM_PROT_WRITE) != 0)
3463 /* Needn't emulate a modified bit for unmanaged pages. */
3469 * pmap_emulate_modified : do dirty bit emulation
3471 * On SMP, update just the local TLB, other CPUs will update their
3472 * TLBs from PTE lazily, if they get the exception.
3473 * Returns 0 in case of sucess, 1 if the page is read only and we
3477 pmap_emulate_modified(pmap_t pmap, vm_offset_t va)
3482 pte = pmap_pte(pmap, va);
3484 panic("pmap_emulate_modified: can't find PTE");
3486 /* It is possible that some other CPU changed m-bit */
3487 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) {
3488 tlb_update(pmap, va, *pte);
3493 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D))
3494 panic("pmap_emulate_modified: invalid pte");
3496 if (pte_test(pte, PTE_RO)) {
3500 pte_set(pte, PTE_D);
3501 tlb_update(pmap, va, *pte);
3502 if (!pte_test(pte, PTE_MANAGED))
3503 panic("pmap_emulate_modified: unmanaged page");
3509 * Routine: pmap_kextract
3511 * Extract the physical page address associated
3515 pmap_kextract(vm_offset_t va)
3520 * First, the direct-mapped regions.
3522 #if defined(__mips_n64)
3523 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
3524 return (MIPS_XKPHYS_TO_PHYS(va));
3526 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
3527 return (MIPS_KSEG0_TO_PHYS(va));
3529 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
3530 return (MIPS_KSEG1_TO_PHYS(va));
3533 * User virtual addresses.
3535 if (va < VM_MAXUSER_ADDRESS) {
3538 if (curproc && curproc->p_vmspace) {
3539 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
3541 return (TLBLO_PTE_TO_PA(*ptep) |
3549 * Should be kernel virtual here, otherwise fail
3551 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
3552 #if defined(__mips_n64)
3553 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
3562 /* Is the kernel pmap initialized? */
3563 if (!CPU_EMPTY(&kernel_pmap->pm_active)) {
3564 /* It's inside the virtual address range */
3565 ptep = pmap_pte(kernel_pmap, va);
3567 return (TLBLO_PTE_TO_PA(*ptep) |
3574 panic("%s for unknown address space %p.", __func__, (void *)va);
3579 pmap_flush_pvcache(vm_page_t m)
3584 for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
3585 pv = TAILQ_NEXT(pv, pv_list)) {
3586 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
3592 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3596 * It appears that this function can only be called before any mappings
3597 * for the page are established. If this ever changes, this code will
3598 * need to walk the pv_list and make each of the existing mappings
3599 * uncacheable, being careful to sync caches and PTEs (and maybe
3600 * invalidate TLB?) for any current mapping it modifies.
3602 if (TAILQ_FIRST(&m->md.pv_list) != NULL)
3603 panic("Can't change memattr on page with existing mappings");
3605 /* Clean memattr portion of pv_flags */
3606 m->md.pv_flags &= ~PV_MEMATTR_MASK;
3607 m->md.pv_flags |= (ma << PV_MEMATTR_SHIFT) & PV_MEMATTR_MASK;
3610 static __inline void
3611 pmap_pte_attr(pt_entry_t *pte, vm_memattr_t ma)
3615 npte = *(u_int *)pte;
3616 npte &= ~PTE_C_MASK;
3622 pmap_change_attr(vm_offset_t sva, vm_size_t size, vm_memattr_t ma)
3624 pd_entry_t *pde, *pdpe;
3626 vm_offset_t ova, eva, va, va_next;
3637 for (; sva < eva; sva = va_next) {
3638 pdpe = pmap_segmap(pmap, sva);
3641 va_next = (sva + NBSEG) & ~SEGMASK;
3647 va_next = (sva + NBPDR) & ~PDRMASK;
3651 pde = pmap_pdpe_to_pde(pdpe, sva);
3656 * Limit our scan to either the end of the va represented
3657 * by the current page table page, or to the end of the
3658 * range being removed.
3664 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3666 if (!pte_test(pte, PTE_V) || pte_cache_bits(pte) == ma) {
3667 if (va != va_next) {
3668 pmap_invalidate_range(pmap, va, sva);
3676 pmap_pte_attr(pte, ma);
3679 pmap_invalidate_range(pmap, va, sva);
3683 /* Flush caches to be in the safe side */
3684 mips_dcache_wbinv_range(ova, size);
3689 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
3693 case VM_MEMATTR_UNCACHEABLE:
3694 case VM_MEMATTR_WRITE_BACK:
3696 case VM_MEMATTR_WRITE_COMBINING: