2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps
41 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish
45 * Manages physical address maps.
47 * Since the information managed by this module is
48 * also stored by the logical address mapping module,
49 * this module may throw away valid virtual-to-physical
50 * mappings at almost any time. However, invalidations
51 * of virtual-to-physical mappings must be done as
54 * In order to cope with hardware architectures which
55 * make virtual-to-physical map invalidates expensive,
56 * this module may delay invalidate or reduced protection
57 * operations until such time as they are actually
58 * necessary. This module is given full information as
59 * to which processors are currently using which maps,
60 * and to when physical maps must be made correct.
63 #include <sys/cdefs.h>
64 __FBSDID("$FreeBSD$");
69 #include <sys/param.h>
70 #include <sys/systm.h>
73 #include <sys/msgbuf.h>
74 #include <sys/mutex.h>
77 #include <sys/rwlock.h>
78 #include <sys/sched.h>
80 #include <sys/sysctl.h>
81 #include <sys/vmmeter.h>
88 #include <vm/vm_param.h>
89 #include <vm/vm_kern.h>
90 #include <vm/vm_page.h>
91 #include <vm/vm_map.h>
92 #include <vm/vm_object.h>
93 #include <vm/vm_extern.h>
94 #include <vm/vm_pageout.h>
95 #include <vm/vm_pager.h>
98 #include <machine/cache.h>
99 #include <machine/md_var.h>
100 #include <machine/tlb.h>
104 #if !defined(DIAGNOSTIC)
105 #define PMAP_INLINE __inline
111 #define PV_STAT(x) do { x ; } while (0)
113 #define PV_STAT(x) do { } while (0)
117 * Get PDEs and PTEs for user/kernel address space
119 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
120 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1))
121 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1))
122 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT)
125 #define NUPDE (NPDEPG * NPDEPG)
126 #define NUSERPGTBLS (NUPDE + NPDEPG)
128 #define NUPDE (NPDEPG)
129 #define NUSERPGTBLS (NUPDE)
132 #define is_kernel_pmap(x) ((x) == kernel_pmap)
134 struct pmap kernel_pmap_store;
135 pd_entry_t *kernel_segmap;
137 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
138 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
141 unsigned pmap_max_asid; /* max ASID supported by the system */
143 #define PMAP_ASID_RESERVED 0
145 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
147 static void pmap_asid_alloc(pmap_t pmap);
149 static struct rwlock_padalign pvh_global_lock;
152 * Data for the pv entry allocation mechanism
154 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
155 static int pv_entry_count;
157 static void free_pv_chunk(struct pv_chunk *pc);
158 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
159 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
160 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
161 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
162 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
164 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req);
165 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
166 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
167 static void pmap_grow_direct_page(int req);
168 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
170 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
171 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
172 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
173 vm_offset_t va, vm_page_t m);
174 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
175 static void pmap_invalidate_all(pmap_t pmap);
176 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
177 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m);
179 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
180 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags);
181 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t);
182 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot);
184 static void pmap_invalidate_page_action(void *arg);
185 static void pmap_invalidate_range_action(void *arg);
186 static void pmap_update_page_action(void *arg);
190 * This structure is for high memory (memory above 512Meg in 32 bit) support.
191 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to
192 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc.
194 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To
195 * access a highmem physical address on a CPU, we map the physical address to
196 * the reserved virtual address for the CPU in the kernel pagetable. This is
197 * done with interrupts disabled(although a spinlock and sched_pin would be
200 struct local_sysmaps {
203 uint16_t valid1, valid2;
205 static struct local_sysmaps sysmap_lmem[MAXCPU];
208 pmap_alloc_lmem_map(void)
212 for (i = 0; i < MAXCPU; i++) {
213 sysmap_lmem[i].base = virtual_avail;
214 virtual_avail += PAGE_SIZE * 2;
215 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0;
219 static __inline vm_offset_t
220 pmap_lmem_map1(vm_paddr_t phys)
222 struct local_sysmaps *sysm;
223 pt_entry_t *pte, npte;
228 intr = intr_disable();
229 cpu = PCPU_GET(cpuid);
230 sysm = &sysmap_lmem[cpu];
231 sysm->saved_intr = intr;
233 npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
234 pte = pmap_pte(kernel_pmap, va);
240 static __inline vm_offset_t
241 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
243 struct local_sysmaps *sysm;
244 pt_entry_t *pte, npte;
245 vm_offset_t va1, va2;
249 intr = intr_disable();
250 cpu = PCPU_GET(cpuid);
251 sysm = &sysmap_lmem[cpu];
252 sysm->saved_intr = intr;
254 va2 = sysm->base + PAGE_SIZE;
255 npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
256 pte = pmap_pte(kernel_pmap, va1);
258 npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
259 pte = pmap_pte(kernel_pmap, va2);
267 pmap_lmem_unmap(void)
269 struct local_sysmaps *sysm;
273 cpu = PCPU_GET(cpuid);
274 sysm = &sysmap_lmem[cpu];
275 pte = pmap_pte(kernel_pmap, sysm->base);
277 tlb_invalidate_address(kernel_pmap, sysm->base);
280 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE);
282 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE);
285 intr_restore(sysm->saved_intr);
287 #else /* __mips_n64 */
290 pmap_alloc_lmem_map(void)
294 static __inline vm_offset_t
295 pmap_lmem_map1(vm_paddr_t phys)
301 static __inline vm_offset_t
302 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
308 static __inline vm_offset_t
309 pmap_lmem_unmap(void)
314 #endif /* !__mips_n64 */
317 pmap_pte_cache_bits(vm_paddr_t pa, vm_page_t m)
321 ma = pmap_page_get_memattr(m);
322 if (ma == VM_MEMATTR_WRITE_BACK && !is_cacheable_mem(pa))
323 ma = VM_MEMATTR_UNCACHEABLE;
326 #define PMAP_PTE_SET_CACHE_BITS(pte, ps, m) { \
327 pte &= ~PTE_C_MASK; \
328 pte |= pmap_pte_cache_bits(pa, m); \
332 * Page table entry lookup routines.
334 static __inline pd_entry_t *
335 pmap_segmap(pmap_t pmap, vm_offset_t va)
338 return (&pmap->pm_segtab[pmap_seg_index(va)]);
342 static __inline pd_entry_t *
343 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
347 pde = (pd_entry_t *)*pdpe;
348 return (&pde[pmap_pde_index(va)]);
351 static __inline pd_entry_t *
352 pmap_pde(pmap_t pmap, vm_offset_t va)
356 pdpe = pmap_segmap(pmap, va);
360 return (pmap_pdpe_to_pde(pdpe, va));
363 static __inline pd_entry_t *
364 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
371 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va)
374 return (pmap_segmap(pmap, va));
378 static __inline pt_entry_t *
379 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
383 pte = (pt_entry_t *)*pde;
384 return (&pte[pmap_pte_index(va)]);
388 pmap_pte(pmap_t pmap, vm_offset_t va)
392 pde = pmap_pde(pmap, va);
393 if (pde == NULL || *pde == NULL)
396 return (pmap_pde_to_pte(pde, va));
400 pmap_steal_memory(vm_size_t size)
402 vm_paddr_t bank_size, pa;
405 size = round_page(size);
406 bank_size = phys_avail[1] - phys_avail[0];
407 while (size > bank_size) {
410 for (i = 0; phys_avail[i + 2]; i += 2) {
411 phys_avail[i] = phys_avail[i + 2];
412 phys_avail[i + 1] = phys_avail[i + 3];
415 phys_avail[i + 1] = 0;
417 panic("pmap_steal_memory: out of memory");
418 bank_size = phys_avail[1] - phys_avail[0];
422 phys_avail[0] += size;
423 if (MIPS_DIRECT_MAPPABLE(pa) == 0)
424 panic("Out of memory below 512Meg?");
425 va = MIPS_PHYS_TO_DIRECT(pa);
426 bzero((caddr_t)va, size);
431 * Bootstrap the system enough to run with virtual memory. This
432 * assumes that the phys_avail array has been initialized.
435 pmap_create_kernel_pagetable(void)
447 * Allocate segment table for the kernel
449 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE);
452 * Allocate second level page tables for the kernel
455 npde = howmany(NKPT, NPDEPG);
456 pdaddr = pmap_steal_memory(PAGE_SIZE * npde);
459 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt);
462 * The R[4-7]?00 stores only one copy of the Global bit in the
463 * translation lookaside buffer for each 2 page entry. Thus invalid
464 * entrys must have the Global bit set so when Entry LO and Entry HI
465 * G bits are anded together they will produce a global bit to store
468 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++)
472 for (i = 0, npt = nkpt; npt > 0; i++) {
473 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE);
474 pde = (pd_entry_t *)kernel_segmap[i];
476 for (j = 0; j < NPDEPG && npt > 0; j++, npt--)
477 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE);
480 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++)
481 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE));
484 PMAP_LOCK_INIT(kernel_pmap);
485 kernel_pmap->pm_segtab = kernel_segmap;
486 CPU_FILL(&kernel_pmap->pm_active);
487 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
488 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
489 kernel_pmap->pm_asid[0].gen = 0;
490 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE;
497 int need_local_mappings = 0;
501 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
503 * Keep the memory aligned on page boundary.
505 phys_avail[i] = round_page(phys_avail[i]);
506 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
510 if (phys_avail[i - 2] > phys_avail[i]) {
513 ptemp[0] = phys_avail[i + 0];
514 ptemp[1] = phys_avail[i + 1];
516 phys_avail[i + 0] = phys_avail[i - 2];
517 phys_avail[i + 1] = phys_avail[i - 1];
519 phys_avail[i - 2] = ptemp[0];
520 phys_avail[i - 1] = ptemp[1];
526 * In 32 bit, we may have memory which cannot be mapped directly.
527 * This memory will need temporary mapping before it can be
530 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1))
531 need_local_mappings = 1;
534 * Copy the phys_avail[] array before we start stealing memory from it.
536 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
537 physmem_desc[i] = phys_avail[i];
538 physmem_desc[i + 1] = phys_avail[i + 1];
541 Maxmem = atop(phys_avail[i - 1]);
544 printf("Physical memory chunk(s):\n");
545 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
548 size = phys_avail[i + 1] - phys_avail[i];
549 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n",
550 (uintmax_t) phys_avail[i],
551 (uintmax_t) phys_avail[i + 1] - 1,
552 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE);
554 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem));
557 * Steal the message buffer from the beginning of memory.
559 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize);
560 msgbufinit(msgbufp, msgbufsize);
563 * Steal thread0 kstack.
565 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
567 virtual_avail = VM_MIN_KERNEL_ADDRESS;
568 virtual_end = VM_MAX_KERNEL_ADDRESS;
572 * Steal some virtual address space to map the pcpu area.
574 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2);
575 pcpup = (struct pcpu *)virtual_avail;
576 virtual_avail += PAGE_SIZE * 2;
579 * Initialize the wired TLB entry mapping the pcpu region for
580 * the BSP at 'pcpup'. Up until this point we were operating
581 * with the 'pcpup' for the BSP pointing to a virtual address
582 * in KSEG0 so there was no need for a TLB mapping.
584 mips_pcpu_tlb_init(PCPU_ADDR(0));
587 printf("pcpu is available at virtual address %p.\n", pcpup);
590 if (need_local_mappings)
591 pmap_alloc_lmem_map();
592 pmap_create_kernel_pagetable();
593 pmap_max_asid = VMNUM_PIDS;
598 * Initialize the global pv list lock.
600 rw_init(&pvh_global_lock, "pmap pv global");
604 * Initialize a vm_page's machine-dependent fields.
607 pmap_page_init(vm_page_t m)
610 TAILQ_INIT(&m->md.pv_list);
611 m->md.pv_flags = VM_MEMATTR_DEFAULT << PV_MEMATTR_SHIFT;
615 * Initialize the pmap module.
616 * Called by vm_init, to initialize any structures that the pmap
617 * system needs to map virtual memory.
624 /***************************************************
625 * Low level helper routines.....
626 ***************************************************/
630 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
632 int cpuid, cpu, self;
633 cpuset_t active_cpus;
636 if (is_kernel_pmap(pmap)) {
637 smp_rendezvous(NULL, fn, NULL, arg);
640 /* Force ASID update on inactive CPUs */
642 if (!CPU_ISSET(cpu, &pmap->pm_active))
643 pmap->pm_asid[cpu].gen = 0;
645 cpuid = PCPU_GET(cpuid);
647 * XXX: barrier/locking for active?
649 * Take a snapshot of active here, any further changes are ignored.
650 * tlb update/invalidate should be harmless on inactive CPUs
652 active_cpus = pmap->pm_active;
653 self = CPU_ISSET(cpuid, &active_cpus);
654 CPU_CLR(cpuid, &active_cpus);
655 /* Optimize for the case where this cpu is the only active one */
656 if (CPU_EMPTY(&active_cpus)) {
661 CPU_SET(cpuid, &active_cpus);
662 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg);
669 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
673 if (is_kernel_pmap(pmap)) {
677 cpuid = PCPU_GET(cpuid);
678 if (!CPU_ISSET(cpuid, &pmap->pm_active))
679 pmap->pm_asid[cpuid].gen = 0;
686 pmap_invalidate_all(pmap_t pmap)
689 pmap_call_on_active_cpus(pmap,
690 (void (*)(void *))tlb_invalidate_all_user, pmap);
693 struct pmap_invalidate_page_arg {
699 pmap_invalidate_page_action(void *arg)
701 struct pmap_invalidate_page_arg *p = arg;
703 tlb_invalidate_address(p->pmap, p->va);
707 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
709 struct pmap_invalidate_page_arg arg;
713 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg);
716 struct pmap_invalidate_range_arg {
723 pmap_invalidate_range_action(void *arg)
725 struct pmap_invalidate_range_arg *p = arg;
727 tlb_invalidate_range(p->pmap, p->sva, p->eva);
731 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
733 struct pmap_invalidate_range_arg arg;
738 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg);
741 struct pmap_update_page_arg {
748 pmap_update_page_action(void *arg)
750 struct pmap_update_page_arg *p = arg;
752 tlb_update(p->pmap, p->va, p->pte);
756 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte)
758 struct pmap_update_page_arg arg;
763 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg);
767 * Routine: pmap_extract
769 * Extract the physical page address associated
770 * with the given map/virtual_address pair.
773 pmap_extract(pmap_t pmap, vm_offset_t va)
776 vm_offset_t retval = 0;
779 pte = pmap_pte(pmap, va);
781 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK);
788 * Routine: pmap_extract_and_hold
790 * Atomically extract and hold the physical page
791 * with the given pmap and virtual address pair
792 * if that mapping permits the given protection.
795 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
797 pt_entry_t pte, *ptep;
798 vm_paddr_t pa, pte_pa;
805 ptep = pmap_pte(pmap, va);
808 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) ||
809 (prot & VM_PROT_WRITE) == 0)) {
810 pte_pa = TLBLO_PTE_TO_PA(pte);
811 if (vm_page_pa_tryrelock(pmap, pte_pa, &pa))
813 m = PHYS_TO_VM_PAGE(pte_pa);
822 /***************************************************
823 * Low level mapping routines.....
824 ***************************************************/
827 * add a wired page to the kva
830 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
833 pt_entry_t opte, npte;
836 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
839 pte = pmap_pte(kernel_pmap, va);
841 npte = TLBLO_PA_TO_PFN(pa) | PTE_C(ma) | PTE_D | PTE_V | PTE_G;
843 if (pte_test(&opte, PTE_V) && opte != npte)
844 pmap_update_page(kernel_pmap, va, npte);
848 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
851 KASSERT(is_cacheable_mem(pa),
852 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa));
854 pmap_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
858 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
861 KASSERT((size & PAGE_MASK) == 0,
862 ("%s: device mapping not page-sized", __func__));
864 for (; size > 0; size -= PAGE_SIZE) {
866 * XXXCEM: this is somewhat inefficient on SMP systems in that
867 * every single page is individually TLB-invalidated via
868 * rendezvous (pmap_update_page()), instead of invalidating the
869 * entire range via a single rendezvous.
871 pmap_kenter_attr(va, pa, VM_MEMATTR_UNCACHEABLE);
878 pmap_kremove_device(vm_offset_t va, vm_size_t size)
881 KASSERT((size & PAGE_MASK) == 0,
882 ("%s: device mapping not page-sized", __func__));
885 * XXXCEM: Similar to pmap_kenter_device, this is inefficient on SMP,
886 * in that pages are invalidated individually instead of a single range
889 for (; size > 0; size -= PAGE_SIZE) {
896 * remove a page from the kernel pagetables
898 /* PMAP_INLINE */ void
899 pmap_kremove(vm_offset_t va)
904 * Write back all caches from the page being destroyed
906 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
908 pte = pmap_pte(kernel_pmap, va);
910 pmap_invalidate_page(kernel_pmap, va);
914 * Used to map a range of physical addresses into kernel
915 * virtual address space.
917 * The value passed in '*virt' is a suggested virtual address for
918 * the mapping. Architectures which can support a direct-mapped
919 * physical to virtual region can return the appropriate address
920 * within that region, leaving '*virt' unchanged. Other
921 * architectures should map the pages starting at '*virt' and
922 * update '*virt' with the first usable address after the mapped
925 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
928 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
932 if (MIPS_DIRECT_MAPPABLE(end - 1))
933 return (MIPS_PHYS_TO_DIRECT(start));
936 while (start < end) {
937 pmap_kenter(va, start);
946 * Add a list of wired pages to the kva
947 * this routine is only used for temporary
948 * kernel mappings that do not need to have
949 * page modification or references recorded.
950 * Note that old mappings are simply written
951 * over. The page *must* be wired.
954 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
957 vm_offset_t origva = va;
959 for (i = 0; i < count; i++) {
960 pmap_flush_pvcache(m[i]);
961 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i]));
965 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count);
969 * this routine jerks page mappings from the
970 * kernel -- it is meant only for temporary mappings.
973 pmap_qremove(vm_offset_t va, int count)
980 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count);
983 pte = pmap_pte(kernel_pmap, va);
986 } while (--count > 0);
987 pmap_invalidate_range(kernel_pmap, origva, va);
990 /***************************************************
991 * Page table page management routines.....
992 ***************************************************/
995 * Decrements a page table page's wire count, which is used to record the
996 * number of valid page table entries within the page. If the wire count
997 * drops to zero, then the page table page is unmapped. Returns TRUE if the
998 * page table page was unmapped and FALSE otherwise.
1000 static PMAP_INLINE boolean_t
1001 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
1005 if (m->wire_count == 0) {
1006 _pmap_unwire_ptp(pmap, va, m);
1013 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
1017 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1019 * unmap the page table page
1022 if (m->pindex < NUPDE)
1023 pde = pmap_pde(pmap, va);
1025 pde = pmap_segmap(pmap, va);
1027 pde = pmap_pde(pmap, va);
1030 pmap->pm_stats.resident_count--;
1033 if (m->pindex < NUPDE) {
1038 * Recursively decrement next level pagetable refcount
1040 pdp = (pd_entry_t *)*pmap_segmap(pmap, va);
1041 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp));
1042 pmap_unwire_ptp(pmap, va, pdpg);
1047 * If the page is finally unwired, simply free it.
1049 vm_page_free_zero(m);
1054 * After removing a page table entry, this routine is used to
1055 * conditionally free the page, and manage the hold/wire counts.
1058 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1062 if (va >= VM_MAXUSER_ADDRESS)
1064 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0"));
1065 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde));
1066 return (pmap_unwire_ptp(pmap, va, mpte));
1070 pmap_pinit0(pmap_t pmap)
1074 PMAP_LOCK_INIT(pmap);
1075 pmap->pm_segtab = kernel_segmap;
1076 CPU_ZERO(&pmap->pm_active);
1077 for (i = 0; i < MAXCPU; i++) {
1078 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1079 pmap->pm_asid[i].gen = 0;
1081 PCPU_SET(curpmap, pmap);
1082 TAILQ_INIT(&pmap->pm_pvchunk);
1083 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1087 pmap_grow_direct_page(int req)
1093 if (!vm_page_reclaim_contig(req, 1, 0, MIPS_KSEG0_LARGEST_PHYS,
1100 pmap_alloc_direct_page(unsigned int index, int req)
1104 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED |
1109 if ((m->flags & PG_ZERO) == 0)
1117 * Initialize a preallocated and zeroed pmap structure,
1118 * such as one in a vmspace structure.
1121 pmap_pinit(pmap_t pmap)
1128 * allocate the page directory page
1130 req_class = VM_ALLOC_NORMAL;
1131 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, req_class)) ==
1133 pmap_grow_direct_page(req_class);
1135 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg));
1136 pmap->pm_segtab = (pd_entry_t *)ptdva;
1137 CPU_ZERO(&pmap->pm_active);
1138 for (i = 0; i < MAXCPU; i++) {
1139 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1140 pmap->pm_asid[i].gen = 0;
1142 TAILQ_INIT(&pmap->pm_pvchunk);
1143 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1149 * this routine is called if the page table page is not
1153 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags)
1160 * Find or fabricate a new pagetable page
1162 req_class = VM_ALLOC_NORMAL;
1163 if ((m = pmap_alloc_direct_page(ptepindex, req_class)) == NULL) {
1164 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1166 rw_wunlock(&pvh_global_lock);
1167 pmap_grow_direct_page(req_class);
1168 rw_wlock(&pvh_global_lock);
1173 * Indicate the need to retry. While waiting, the page
1174 * table page may have been allocated.
1180 * Map the pagetable page into the process address space, if it
1181 * isn't already there.
1183 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1186 if (ptepindex >= NUPDE) {
1187 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva;
1189 pd_entry_t *pdep, *pde;
1190 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT);
1191 int pdeindex = ptepindex & (NPDEPG - 1);
1194 pdep = &pmap->pm_segtab[segindex];
1195 if (*pdep == NULL) {
1196 /* recurse for allocating page dir */
1197 if (_pmap_allocpte(pmap, NUPDE + segindex,
1199 /* alloc failed, release current */
1200 vm_page_unwire_noq(m);
1201 vm_page_free_zero(m);
1205 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep));
1208 /* Next level entry */
1209 pde = (pd_entry_t *)*pdep;
1210 pde[pdeindex] = (pd_entry_t)pageva;
1213 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva;
1215 pmap->pm_stats.resident_count++;
1220 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1227 * Calculate pagetable page index
1229 ptepindex = pmap_pde_pindex(va);
1232 * Get the page directory entry
1234 pde = pmap_pde(pmap, va);
1237 * If the page table page is mapped, we just increment the hold
1238 * count, and activate it.
1240 if (pde != NULL && *pde != NULL) {
1241 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde));
1245 * Here if the pte page isn't mapped, or if it has been
1248 m = _pmap_allocpte(pmap, ptepindex, flags);
1249 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1256 /***************************************************
1257 * Pmap allocation/deallocation routines.
1258 ***************************************************/
1261 * Release any resources held by the given physical map.
1262 * Called when a pmap initialized by pmap_pinit is being released.
1263 * Should only be called if the map contains no valid mappings.
1266 pmap_release(pmap_t pmap)
1271 KASSERT(pmap->pm_stats.resident_count == 0,
1272 ("pmap_release: pmap resident count %ld != 0",
1273 pmap->pm_stats.resident_count));
1275 ptdva = (vm_offset_t)pmap->pm_segtab;
1276 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva));
1278 vm_page_unwire_noq(ptdpg);
1279 vm_page_free_zero(ptdpg);
1283 * grow the number of kernel page table entries, if needed
1286 pmap_growkernel(vm_offset_t addr)
1289 pd_entry_t *pde, *pdpe;
1293 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1294 req_class = VM_ALLOC_INTERRUPT;
1295 addr = roundup2(addr, NBSEG);
1296 if (addr - 1 >= vm_map_max(kernel_map))
1297 addr = vm_map_max(kernel_map);
1298 while (kernel_vm_end < addr) {
1299 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end);
1302 /* new intermediate page table entry */
1303 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1305 panic("pmap_growkernel: no memory to grow kernel");
1306 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1307 continue; /* try again */
1310 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
1312 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1313 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1314 kernel_vm_end = vm_map_max(kernel_map);
1321 * This index is bogus, but out of the way
1323 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1325 if (nkpg == NULL && vm_page_reclaim_contig(req_class, 1,
1326 0, MIPS_KSEG0_LARGEST_PHYS, PAGE_SIZE, 0))
1327 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1330 panic("pmap_growkernel: no memory to grow kernel");
1332 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1335 * The R[4-7]?00 stores only one copy of the Global bit in
1336 * the translation lookaside buffer for each 2 page entry.
1337 * Thus invalid entrys must have the Global bit set so when
1338 * Entry LO and Entry HI G bits are anded together they will
1339 * produce a global bit to store in the tlb.
1341 pte = (pt_entry_t *)*pde;
1342 for (i = 0; i < NPTEPG; i++)
1345 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1346 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1347 kernel_vm_end = vm_map_max(kernel_map);
1353 /***************************************************
1354 * page management routines.
1355 ***************************************************/
1357 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1359 CTASSERT(_NPCM == 3);
1360 CTASSERT(_NPCPV == 168);
1362 CTASSERT(_NPCM == 11);
1363 CTASSERT(_NPCPV == 336);
1366 static __inline struct pv_chunk *
1367 pv_to_chunk(pv_entry_t pv)
1370 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1373 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1376 #define PC_FREE0_1 0xfffffffffffffffful
1377 #define PC_FREE2 0x000000fffffffffful
1379 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
1380 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
1383 static const u_long pc_freemask[_NPCM] = {
1385 PC_FREE0_1, PC_FREE0_1, PC_FREE2
1387 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1388 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1389 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1390 PC_FREE0_9, PC_FREE10
1394 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1396 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1397 "Current number of pv entries");
1400 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1402 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1403 "Current number of pv entry chunks");
1404 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1405 "Current number of pv entry chunks allocated");
1406 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1407 "Current number of pv entry chunks frees");
1408 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1409 "Number of times tried to get a chunk page but failed.");
1411 static long pv_entry_frees, pv_entry_allocs;
1412 static int pv_entry_spare;
1414 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1415 "Current number of pv entry frees");
1416 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1417 "Current number of pv entry allocs");
1418 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1419 "Current number of spare pv entries");
1423 * We are in a serious low memory condition. Resort to
1424 * drastic measures to free some pages so we can allocate
1425 * another pv entry chunk.
1428 pmap_pv_reclaim(pmap_t locked_pmap)
1431 struct pv_chunk *pc;
1434 pt_entry_t *pte, oldpte;
1439 int bit, field, freed, idx;
1441 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1444 TAILQ_INIT(&newtail);
1445 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) {
1446 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1447 if (pmap != pc->pc_pmap) {
1449 pmap_invalidate_all(pmap);
1450 if (pmap != locked_pmap)
1454 /* Avoid deadlock and lock recursion. */
1455 if (pmap > locked_pmap)
1457 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
1459 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1465 * Destroy every non-wired, 4 KB page mapping in the chunk.
1468 for (field = 0; field < _NPCM; field++) {
1469 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1470 inuse != 0; inuse &= ~(1UL << bit)) {
1471 bit = ffsl(inuse) - 1;
1472 idx = field * sizeof(inuse) * NBBY + bit;
1473 pv = &pc->pc_pventry[idx];
1475 pde = pmap_pde(pmap, va);
1476 KASSERT(pde != NULL && *pde != 0,
1477 ("pmap_pv_reclaim: pde"));
1478 pte = pmap_pde_to_pte(pde, va);
1480 if (pte_test(&oldpte, PTE_W))
1482 if (is_kernel_pmap(pmap))
1486 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte));
1487 if (pte_test(&oldpte, PTE_D))
1489 if (m->md.pv_flags & PV_TABLE_REF)
1490 vm_page_aflag_set(m, PGA_REFERENCED);
1491 m->md.pv_flags &= ~PV_TABLE_REF;
1492 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1493 if (TAILQ_EMPTY(&m->md.pv_list))
1494 vm_page_aflag_clear(m, PGA_WRITEABLE);
1495 pc->pc_map[field] |= 1UL << bit;
1496 pmap_unuse_pt(pmap, va, *pde);
1501 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1504 /* Every freed mapping is for a 4 KB page. */
1505 pmap->pm_stats.resident_count -= freed;
1506 PV_STAT(pv_entry_frees += freed);
1507 PV_STAT(pv_entry_spare += freed);
1508 pv_entry_count -= freed;
1509 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1510 for (field = 0; field < _NPCM; field++)
1511 if (pc->pc_map[field] != pc_freemask[field]) {
1512 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1514 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1517 * One freed pv entry in locked_pmap is
1520 if (pmap == locked_pmap)
1524 if (field == _NPCM) {
1525 PV_STAT(pv_entry_spare -= _NPCPV);
1526 PV_STAT(pc_chunk_count--);
1527 PV_STAT(pc_chunk_frees++);
1528 /* Entire chunk is free; return it. */
1529 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(
1531 dump_drop_page(m_pc->phys_addr);
1536 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
1538 pmap_invalidate_all(pmap);
1539 if (pmap != locked_pmap)
1546 * free the pv_entry back to the free list
1549 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1551 struct pv_chunk *pc;
1552 int bit, field, idx;
1554 rw_assert(&pvh_global_lock, RA_WLOCKED);
1555 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1556 PV_STAT(pv_entry_frees++);
1557 PV_STAT(pv_entry_spare++);
1559 pc = pv_to_chunk(pv);
1560 idx = pv - &pc->pc_pventry[0];
1561 field = idx / (sizeof(u_long) * NBBY);
1562 bit = idx % (sizeof(u_long) * NBBY);
1563 pc->pc_map[field] |= 1ul << bit;
1564 for (idx = 0; idx < _NPCM; idx++)
1565 if (pc->pc_map[idx] != pc_freemask[idx]) {
1567 * 98% of the time, pc is already at the head of the
1568 * list. If it isn't already, move it to the head.
1570 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
1572 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1573 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1578 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1583 free_pv_chunk(struct pv_chunk *pc)
1587 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1588 PV_STAT(pv_entry_spare -= _NPCPV);
1589 PV_STAT(pc_chunk_count--);
1590 PV_STAT(pc_chunk_frees++);
1591 /* entire chunk is free, return it */
1592 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc));
1593 dump_drop_page(m->phys_addr);
1594 vm_page_unwire(m, PQ_NONE);
1599 * get a new pv_entry, allocating a block from the system
1603 get_pv_entry(pmap_t pmap, boolean_t try)
1605 struct pv_chunk *pc;
1608 int bit, field, idx;
1610 rw_assert(&pvh_global_lock, RA_WLOCKED);
1611 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1612 PV_STAT(pv_entry_allocs++);
1615 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1617 for (field = 0; field < _NPCM; field++) {
1618 if (pc->pc_map[field]) {
1619 bit = ffsl(pc->pc_map[field]) - 1;
1623 if (field < _NPCM) {
1624 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
1625 pv = &pc->pc_pventry[idx];
1626 pc->pc_map[field] &= ~(1ul << bit);
1627 /* If this was the last item, move it to tail */
1628 for (field = 0; field < _NPCM; field++)
1629 if (pc->pc_map[field] != 0) {
1630 PV_STAT(pv_entry_spare--);
1631 return (pv); /* not full, return */
1633 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1634 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
1635 PV_STAT(pv_entry_spare--);
1639 /* No free items, allocate another chunk */
1640 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL |
1645 PV_STAT(pc_chunk_tryfail++);
1648 m = pmap_pv_reclaim(pmap);
1652 PV_STAT(pc_chunk_count++);
1653 PV_STAT(pc_chunk_allocs++);
1654 dump_add_page(m->phys_addr);
1655 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1657 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
1658 for (field = 1; field < _NPCM; field++)
1659 pc->pc_map[field] = pc_freemask[field];
1660 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1661 pv = &pc->pc_pventry[0];
1662 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1663 PV_STAT(pv_entry_spare += _NPCPV - 1);
1668 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1672 rw_assert(&pvh_global_lock, RA_WLOCKED);
1673 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
1674 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1675 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
1683 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1687 pv = pmap_pvh_remove(pvh, pmap, va);
1688 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx",
1689 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)),
1691 free_pv_entry(pmap, pv);
1695 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
1698 rw_assert(&pvh_global_lock, RA_WLOCKED);
1699 pmap_pvh_free(&m->md, pmap, va);
1700 if (TAILQ_EMPTY(&m->md.pv_list))
1701 vm_page_aflag_clear(m, PGA_WRITEABLE);
1705 * Conditionally create a pv entry.
1708 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va,
1713 rw_assert(&pvh_global_lock, RA_WLOCKED);
1714 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1715 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
1717 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
1724 * pmap_remove_pte: do the things to unmap a page in a process
1727 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
1734 rw_assert(&pvh_global_lock, RA_WLOCKED);
1735 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1738 * Write back all cache lines from the page being unmapped.
1740 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
1743 if (is_kernel_pmap(pmap))
1748 if (pte_test(&oldpte, PTE_W))
1749 pmap->pm_stats.wired_count -= 1;
1751 pmap->pm_stats.resident_count -= 1;
1753 if (pte_test(&oldpte, PTE_MANAGED)) {
1754 pa = TLBLO_PTE_TO_PA(oldpte);
1755 m = PHYS_TO_VM_PAGE(pa);
1756 if (pte_test(&oldpte, PTE_D)) {
1757 KASSERT(!pte_test(&oldpte, PTE_RO),
1758 ("%s: modified page not writable: va: %p, pte: %#jx",
1759 __func__, (void *)va, (uintmax_t)oldpte));
1762 if (m->md.pv_flags & PV_TABLE_REF)
1763 vm_page_aflag_set(m, PGA_REFERENCED);
1764 m->md.pv_flags &= ~PV_TABLE_REF;
1766 pmap_remove_entry(pmap, m, va);
1768 return (pmap_unuse_pt(pmap, va, pde));
1772 * Remove a single page from a process address space
1775 pmap_remove_page(struct pmap *pmap, vm_offset_t va)
1780 rw_assert(&pvh_global_lock, RA_WLOCKED);
1781 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1782 pde = pmap_pde(pmap, va);
1783 if (pde == NULL || *pde == 0)
1785 ptq = pmap_pde_to_pte(pde, va);
1788 * If there is no pte for this address, just skip it!
1790 if (!pte_test(ptq, PTE_V))
1793 (void)pmap_remove_pte(pmap, ptq, va, *pde);
1794 pmap_invalidate_page(pmap, va);
1798 * Remove the given range of addresses from the specified map.
1800 * It is assumed that the start and end are properly
1801 * rounded to the page size.
1804 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1806 pd_entry_t *pde, *pdpe;
1808 vm_offset_t va, va_next;
1811 * Perform an unsynchronized read. This is, however, safe.
1813 if (pmap->pm_stats.resident_count == 0)
1816 rw_wlock(&pvh_global_lock);
1820 * special handling of removing one page. a very common operation
1821 * and easy to short circuit some code.
1823 if ((sva + PAGE_SIZE) == eva) {
1824 pmap_remove_page(pmap, sva);
1827 for (; sva < eva; sva = va_next) {
1828 pdpe = pmap_segmap(pmap, sva);
1831 va_next = (sva + NBSEG) & ~SEGMASK;
1837 va_next = (sva + NBPDR) & ~PDRMASK;
1841 pde = pmap_pdpe_to_pde(pdpe, sva);
1846 * Limit our scan to either the end of the va represented
1847 * by the current page table page, or to the end of the
1848 * range being removed.
1854 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1856 if (!pte_test(pte, PTE_V)) {
1857 if (va != va_next) {
1858 pmap_invalidate_range(pmap, va, sva);
1865 if (pmap_remove_pte(pmap, pte, sva, *pde)) {
1871 pmap_invalidate_range(pmap, va, sva);
1874 rw_wunlock(&pvh_global_lock);
1879 * Routine: pmap_remove_all
1881 * Removes this physical page from
1882 * all physical maps in which it resides.
1883 * Reflects back modify bits to the pager.
1886 * Original versions of this routine were very
1887 * inefficient because they iteratively called
1888 * pmap_remove (slow...)
1892 pmap_remove_all(vm_page_t m)
1897 pt_entry_t *pte, tpte;
1899 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1900 ("pmap_remove_all: page %p is not managed", m));
1901 rw_wlock(&pvh_global_lock);
1903 if (m->md.pv_flags & PV_TABLE_REF)
1904 vm_page_aflag_set(m, PGA_REFERENCED);
1906 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
1911 * If it's last mapping writeback all caches from
1912 * the page being destroyed
1914 if (TAILQ_NEXT(pv, pv_list) == NULL)
1915 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
1917 pmap->pm_stats.resident_count--;
1919 pde = pmap_pde(pmap, pv->pv_va);
1920 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde"));
1921 pte = pmap_pde_to_pte(pde, pv->pv_va);
1924 if (is_kernel_pmap(pmap))
1929 if (pte_test(&tpte, PTE_W))
1930 pmap->pm_stats.wired_count--;
1933 * Update the vm_page_t clean and reference bits.
1935 if (pte_test(&tpte, PTE_D)) {
1936 KASSERT(!pte_test(&tpte, PTE_RO),
1937 ("%s: modified page not writable: va: %p, pte: %#jx",
1938 __func__, (void *)pv->pv_va, (uintmax_t)tpte));
1941 pmap_invalidate_page(pmap, pv->pv_va);
1943 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1944 pmap_unuse_pt(pmap, pv->pv_va, *pde);
1945 free_pv_entry(pmap, pv);
1949 vm_page_aflag_clear(m, PGA_WRITEABLE);
1950 m->md.pv_flags &= ~PV_TABLE_REF;
1951 rw_wunlock(&pvh_global_lock);
1955 * Set the physical protection on the
1956 * specified range of this map as requested.
1959 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1961 pt_entry_t pbits, *pte;
1962 pd_entry_t *pde, *pdpe;
1963 vm_offset_t va, va_next;
1967 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1968 pmap_remove(pmap, sva, eva);
1971 if (prot & VM_PROT_WRITE)
1975 for (; sva < eva; sva = va_next) {
1976 pdpe = pmap_segmap(pmap, sva);
1979 va_next = (sva + NBSEG) & ~SEGMASK;
1985 va_next = (sva + NBPDR) & ~PDRMASK;
1989 pde = pmap_pdpe_to_pde(pdpe, sva);
1994 * Limit our scan to either the end of the va represented
1995 * by the current page table page, or to the end of the
1996 * range being write protected.
2002 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2005 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits,
2007 if (va != va_next) {
2008 pmap_invalidate_range(pmap, va, sva);
2013 pte_set(&pbits, PTE_RO);
2014 if (pte_test(&pbits, PTE_D)) {
2015 pte_clear(&pbits, PTE_D);
2016 if (pte_test(&pbits, PTE_MANAGED)) {
2017 pa = TLBLO_PTE_TO_PA(pbits);
2018 m = PHYS_TO_VM_PAGE(pa);
2025 * Unless PTE_D is set, any TLB entries
2026 * mapping "sva" don't allow write access, so
2027 * they needn't be invalidated.
2029 if (va != va_next) {
2030 pmap_invalidate_range(pmap, va, sva);
2037 pmap_invalidate_range(pmap, va, sva);
2043 * Insert the given physical page (p) at
2044 * the specified virtual address (v) in the
2045 * target physical map with the protection requested.
2047 * If specified, the page will be wired down, meaning
2048 * that the related pte can not be reclaimed.
2050 * NB: This is the only routine which MAY NOT lazy-evaluate
2051 * or lose information. That is, this routine must actually
2052 * insert this page into the given map NOW.
2055 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2056 u_int flags, int8_t psind __unused)
2060 pt_entry_t origpte, newpte;
2065 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2066 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
2067 va >= kmi.clean_eva,
2068 ("pmap_enter: managed mapping within the clean submap"));
2069 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
2070 VM_OBJECT_ASSERT_LOCKED(m->object);
2071 pa = VM_PAGE_TO_PHYS(m);
2072 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot);
2073 if ((flags & PMAP_ENTER_WIRED) != 0)
2075 if (is_kernel_pmap(pmap))
2077 PMAP_PTE_SET_CACHE_BITS(newpte, pa, m);
2078 if ((m->oflags & VPO_UNMANAGED) == 0)
2079 newpte |= PTE_MANAGED;
2083 rw_wlock(&pvh_global_lock);
2087 * In the case that a page table page is not resident, we are
2090 if (va < VM_MAXUSER_ADDRESS) {
2091 mpte = pmap_allocpte(pmap, va, flags);
2093 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
2094 ("pmap_allocpte failed with sleep allowed"));
2095 rw_wunlock(&pvh_global_lock);
2097 return (KERN_RESOURCE_SHORTAGE);
2100 pte = pmap_pte(pmap, va);
2103 * Page Directory table entry not valid, we need a new PT page
2106 panic("pmap_enter: invalid page directory, pdir=%p, va=%p",
2107 (void *)pmap->pm_segtab, (void *)va);
2111 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO | PTE_V),
2112 ("pmap_enter: modified page not writable: va: %p, pte: %#jx",
2113 (void *)va, (uintmax_t)origpte));
2114 opa = TLBLO_PTE_TO_PA(origpte);
2117 * Mapping has not changed, must be protection or wiring change.
2119 if (pte_test(&origpte, PTE_V) && opa == pa) {
2121 * Wiring change, just update stats. We don't worry about
2122 * wiring PT pages as they remain resident as long as there
2123 * are valid mappings in them. Hence, if a user page is
2124 * wired, the PT page will be also.
2126 if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W))
2127 pmap->pm_stats.wired_count++;
2128 else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte,
2130 pmap->pm_stats.wired_count--;
2133 * Remove extra pte reference
2138 if (pte_test(&origpte, PTE_MANAGED)) {
2139 m->md.pv_flags |= PV_TABLE_REF;
2140 if (!pte_test(&newpte, PTE_RO))
2141 vm_page_aflag_set(m, PGA_WRITEABLE);
2149 * Mapping has changed, invalidate old range and fall through to
2150 * handle validating new mapping.
2153 if (is_kernel_pmap(pmap))
2157 if (pte_test(&origpte, PTE_W))
2158 pmap->pm_stats.wired_count--;
2159 if (pte_test(&origpte, PTE_MANAGED)) {
2160 om = PHYS_TO_VM_PAGE(opa);
2161 if (pte_test(&origpte, PTE_D))
2163 if ((om->md.pv_flags & PV_TABLE_REF) != 0) {
2164 om->md.pv_flags &= ~PV_TABLE_REF;
2165 vm_page_aflag_set(om, PGA_REFERENCED);
2167 pv = pmap_pvh_remove(&om->md, pmap, va);
2168 if (!pte_test(&newpte, PTE_MANAGED))
2169 free_pv_entry(pmap, pv);
2170 if ((om->aflags & PGA_WRITEABLE) != 0 &&
2171 TAILQ_EMPTY(&om->md.pv_list))
2172 vm_page_aflag_clear(om, PGA_WRITEABLE);
2174 pmap_invalidate_page(pmap, va);
2178 KASSERT(mpte->wire_count > 0,
2179 ("pmap_enter: missing reference to page table page,"
2180 " va: %p", (void *)va));
2183 pmap->pm_stats.resident_count++;
2186 * Enter on the PV list if part of our managed memory.
2188 if (pte_test(&newpte, PTE_MANAGED)) {
2189 m->md.pv_flags |= PV_TABLE_REF;
2191 pv = get_pv_entry(pmap, FALSE);
2194 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2195 if (!pte_test(&newpte, PTE_RO))
2196 vm_page_aflag_set(m, PGA_WRITEABLE);
2200 * Increment counters
2202 if (pte_test(&newpte, PTE_W))
2203 pmap->pm_stats.wired_count++;
2208 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
2212 * if the mapping or permission bits are different, we need to
2215 if (origpte != newpte) {
2217 if (pte_test(&origpte, PTE_V)) {
2218 KASSERT(opa == pa, ("pmap_enter: invalid update"));
2219 if (pte_test(&origpte, PTE_D)) {
2220 if (pte_test(&origpte, PTE_MANAGED))
2223 pmap_update_page(pmap, va, newpte);
2228 * Sync I & D caches for executable pages. Do this only if the
2229 * target pmap belongs to the current process. Otherwise, an
2230 * unresolvable TLB miss may occur.
2232 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
2233 (prot & VM_PROT_EXECUTE)) {
2234 mips_icache_sync_range(va, PAGE_SIZE);
2235 mips_dcache_wbinv_range(va, PAGE_SIZE);
2237 rw_wunlock(&pvh_global_lock);
2239 return (KERN_SUCCESS);
2243 * this code makes some *MAJOR* assumptions:
2244 * 1. Current pmap & pmap exists.
2247 * 4. No page table pages.
2248 * but is *MUCH* faster than pmap_enter...
2252 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2255 rw_wlock(&pvh_global_lock);
2257 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
2258 rw_wunlock(&pvh_global_lock);
2263 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2264 vm_prot_t prot, vm_page_t mpte)
2266 pt_entry_t *pte, npte;
2269 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2270 (m->oflags & VPO_UNMANAGED) != 0,
2271 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2272 rw_assert(&pvh_global_lock, RA_WLOCKED);
2273 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2276 * In the case that a page table page is not resident, we are
2279 if (va < VM_MAXUSER_ADDRESS) {
2284 * Calculate pagetable page index
2286 ptepindex = pmap_pde_pindex(va);
2287 if (mpte && (mpte->pindex == ptepindex)) {
2291 * Get the page directory entry
2293 pde = pmap_pde(pmap, va);
2296 * If the page table page is mapped, we just
2297 * increment the hold count, and activate it.
2299 if (pde && *pde != 0) {
2300 mpte = PHYS_TO_VM_PAGE(
2301 MIPS_DIRECT_TO_PHYS(*pde));
2304 mpte = _pmap_allocpte(pmap, ptepindex,
2305 PMAP_ENTER_NOSLEEP);
2314 pte = pmap_pte(pmap, va);
2315 if (pte_test(pte, PTE_V)) {
2324 * Enter on the PV list if part of our managed memory.
2326 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2327 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) {
2329 pmap_unwire_ptp(pmap, va, mpte);
2336 * Increment counters
2338 pmap->pm_stats.resident_count++;
2340 pa = VM_PAGE_TO_PHYS(m);
2343 * Now validate mapping with RO protection
2345 npte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V;
2346 if ((m->oflags & VPO_UNMANAGED) == 0)
2347 npte |= PTE_MANAGED;
2349 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2351 if (is_kernel_pmap(pmap))
2352 *pte = npte | PTE_G;
2356 * Sync I & D caches. Do this only if the target pmap
2357 * belongs to the current process. Otherwise, an
2358 * unresolvable TLB miss may occur. */
2359 if (pmap == &curproc->p_vmspace->vm_pmap) {
2361 mips_icache_sync_range(va, PAGE_SIZE);
2362 mips_dcache_wbinv_range(va, PAGE_SIZE);
2369 * Make a temporary mapping for a physical address. This is only intended
2370 * to be used for panic dumps.
2372 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2375 pmap_kenter_temporary(vm_paddr_t pa, int i)
2380 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
2383 if (MIPS_DIRECT_MAPPABLE(pa)) {
2384 va = MIPS_PHYS_TO_DIRECT(pa);
2386 #ifndef __mips_n64 /* XXX : to be converted to new style */
2389 struct local_sysmaps *sysm;
2390 pt_entry_t *pte, npte;
2392 /* If this is used other than for dumps, we may need to leave
2393 * interrupts disasbled on return. If crash dumps don't work when
2394 * we get to this point, we might want to consider this (leaving things
2395 * disabled as a starting point ;-)
2397 intr = intr_disable();
2398 cpu = PCPU_GET(cpuid);
2399 sysm = &sysmap_lmem[cpu];
2400 /* Since this is for the debugger, no locks or any other fun */
2401 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
2403 pte = pmap_pte(kernel_pmap, sysm->base);
2406 pmap_update_page(kernel_pmap, sysm->base, npte);
2411 return ((void *)va);
2415 pmap_kenter_temporary_free(vm_paddr_t pa)
2417 #ifndef __mips_n64 /* XXX : to be converted to new style */
2420 struct local_sysmaps *sysm;
2423 if (MIPS_DIRECT_MAPPABLE(pa)) {
2424 /* nothing to do for this case */
2427 #ifndef __mips_n64 /* XXX : to be converted to new style */
2428 cpu = PCPU_GET(cpuid);
2429 sysm = &sysmap_lmem[cpu];
2433 intr = intr_disable();
2434 pte = pmap_pte(kernel_pmap, sysm->base);
2436 pmap_invalidate_page(kernel_pmap, sysm->base);
2444 * Maps a sequence of resident pages belonging to the same object.
2445 * The sequence begins with the given page m_start. This page is
2446 * mapped at the given virtual address start. Each subsequent page is
2447 * mapped at a virtual address that is offset from start by the same
2448 * amount as the page is offset from m_start within the object. The
2449 * last page in the sequence is the page with the largest offset from
2450 * m_start that can be mapped at a virtual address less than the given
2451 * virtual address end. Not every virtual page between start and end
2452 * is mapped; only those for which a resident page exists with the
2453 * corresponding offset from m_start are mapped.
2456 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2457 vm_page_t m_start, vm_prot_t prot)
2460 vm_pindex_t diff, psize;
2462 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2464 psize = atop(end - start);
2467 rw_wlock(&pvh_global_lock);
2469 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2470 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m,
2472 m = TAILQ_NEXT(m, listq);
2474 rw_wunlock(&pvh_global_lock);
2479 * pmap_object_init_pt preloads the ptes for a given object
2480 * into the specified pmap. This eliminates the blast of soft
2481 * faults on process startup and immediately after an mmap.
2484 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
2485 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2487 VM_OBJECT_ASSERT_WLOCKED(object);
2488 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2489 ("pmap_object_init_pt: non-device object"));
2493 * Clear the wired attribute from the mappings for the specified range of
2494 * addresses in the given pmap. Every valid mapping within that range
2495 * must have the wired attribute set. In contrast, invalid mappings
2496 * cannot have the wired attribute set, so they are ignored.
2498 * The wired attribute of the page table entry is not a hardware feature,
2499 * so there is no need to invalidate any TLB entries.
2502 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2504 pd_entry_t *pde, *pdpe;
2506 vm_offset_t va_next;
2509 for (; sva < eva; sva = va_next) {
2510 pdpe = pmap_segmap(pmap, sva);
2512 if (*pdpe == NULL) {
2513 va_next = (sva + NBSEG) & ~SEGMASK;
2519 va_next = (sva + NBPDR) & ~PDRMASK;
2522 pde = pmap_pdpe_to_pde(pdpe, sva);
2527 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2529 if (!pte_test(pte, PTE_V))
2531 if (!pte_test(pte, PTE_W))
2532 panic("pmap_unwire: pte %#jx is missing PG_W",
2534 pte_clear(pte, PTE_W);
2535 pmap->pm_stats.wired_count--;
2542 * Copy the range specified by src_addr/len
2543 * from the source map to the range dst_addr/len
2544 * in the destination map.
2546 * This routine is only advisory and need not do anything.
2550 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2551 vm_size_t len, vm_offset_t src_addr)
2556 * pmap_zero_page zeros the specified hardware page by mapping
2557 * the page into KVM and using bzero to clear its contents.
2559 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2562 pmap_zero_page(vm_page_t m)
2565 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2567 if (MIPS_DIRECT_MAPPABLE(phys)) {
2568 va = MIPS_PHYS_TO_DIRECT(phys);
2569 bzero((caddr_t)va, PAGE_SIZE);
2570 mips_dcache_wbinv_range(va, PAGE_SIZE);
2572 va = pmap_lmem_map1(phys);
2573 bzero((caddr_t)va, PAGE_SIZE);
2574 mips_dcache_wbinv_range(va, PAGE_SIZE);
2580 * pmap_zero_page_area zeros the specified hardware page by mapping
2581 * the page into KVM and using bzero to clear its contents.
2583 * off and size may not cover an area beyond a single hardware page.
2586 pmap_zero_page_area(vm_page_t m, int off, int size)
2589 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2591 if (MIPS_DIRECT_MAPPABLE(phys)) {
2592 va = MIPS_PHYS_TO_DIRECT(phys);
2593 bzero((char *)(caddr_t)va + off, size);
2594 mips_dcache_wbinv_range(va + off, size);
2596 va = pmap_lmem_map1(phys);
2597 bzero((char *)va + off, size);
2598 mips_dcache_wbinv_range(va + off, size);
2604 * pmap_copy_page copies the specified (machine independent)
2605 * page by mapping the page into virtual memory and using
2606 * bcopy to copy the page, one machine dependent page at a
2609 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2612 pmap_copy_page(vm_page_t src, vm_page_t dst)
2614 vm_offset_t va_src, va_dst;
2615 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src);
2616 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst);
2618 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) {
2619 /* easy case, all can be accessed via KSEG0 */
2621 * Flush all caches for VA that are mapped to this page
2622 * to make sure that data in SDRAM is up to date
2624 pmap_flush_pvcache(src);
2625 mips_dcache_wbinv_range_index(
2626 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE);
2627 va_src = MIPS_PHYS_TO_DIRECT(phys_src);
2628 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst);
2629 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
2630 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2632 va_src = pmap_lmem_map2(phys_src, phys_dst);
2633 va_dst = va_src + PAGE_SIZE;
2634 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE);
2635 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2640 int unmapped_buf_allowed;
2643 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2644 vm_offset_t b_offset, int xfersize)
2648 vm_offset_t a_pg_offset, b_pg_offset;
2649 vm_paddr_t a_phys, b_phys;
2652 while (xfersize > 0) {
2653 a_pg_offset = a_offset & PAGE_MASK;
2654 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2655 a_m = ma[a_offset >> PAGE_SHIFT];
2656 a_phys = VM_PAGE_TO_PHYS(a_m);
2657 b_pg_offset = b_offset & PAGE_MASK;
2658 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2659 b_m = mb[b_offset >> PAGE_SHIFT];
2660 b_phys = VM_PAGE_TO_PHYS(b_m);
2661 if (MIPS_DIRECT_MAPPABLE(a_phys) &&
2662 MIPS_DIRECT_MAPPABLE(b_phys)) {
2663 pmap_flush_pvcache(a_m);
2664 mips_dcache_wbinv_range_index(
2665 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE);
2666 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) +
2668 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) +
2670 bcopy(a_cp, b_cp, cnt);
2671 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2673 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys);
2674 b_cp = (char *)a_cp + PAGE_SIZE;
2675 a_cp += a_pg_offset;
2676 b_cp += b_pg_offset;
2677 bcopy(a_cp, b_cp, cnt);
2678 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2688 pmap_quick_enter_page(vm_page_t m)
2690 #if defined(__mips_n64)
2691 return MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
2694 struct local_sysmaps *sysm;
2695 pt_entry_t *pte, npte;
2697 pa = VM_PAGE_TO_PHYS(m);
2699 if (MIPS_DIRECT_MAPPABLE(pa)) {
2700 if (pmap_page_get_memattr(m) != VM_MEMATTR_WRITE_BACK)
2701 return (MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
2703 return (MIPS_PHYS_TO_DIRECT(pa));
2706 sysm = &sysmap_lmem[PCPU_GET(cpuid)];
2708 KASSERT(sysm->valid1 == 0, ("pmap_quick_enter_page: PTE busy"));
2710 pte = pmap_pte(kernel_pmap, sysm->base);
2711 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G;
2712 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2716 return (sysm->base);
2721 pmap_quick_remove_page(vm_offset_t addr)
2723 mips_dcache_wbinv_range(addr, PAGE_SIZE);
2725 #if !defined(__mips_n64)
2726 struct local_sysmaps *sysm;
2729 if (addr >= MIPS_KSEG0_START && addr < MIPS_KSEG0_END)
2732 sysm = &sysmap_lmem[PCPU_GET(cpuid)];
2734 KASSERT(sysm->valid1 != 0,
2735 ("pmap_quick_remove_page: PTE not in use"));
2736 KASSERT(sysm->base == addr,
2737 ("pmap_quick_remove_page: invalid address"));
2739 pte = pmap_pte(kernel_pmap, addr);
2741 tlb_invalidate_address(kernel_pmap, addr);
2748 * Returns true if the pmap's pv is one of the first
2749 * 16 pvs linked to from this page. This count may
2750 * be changed upwards or downwards in the future; it
2751 * is only necessary that true be returned for a small
2752 * subset of pmaps for proper page aging.
2755 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2761 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2762 ("pmap_page_exists_quick: page %p is not managed", m));
2764 rw_wlock(&pvh_global_lock);
2765 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2766 if (PV_PMAP(pv) == pmap) {
2774 rw_wunlock(&pvh_global_lock);
2779 * Remove all pages from specified address space
2780 * this aids process exit speeds. Also, this code
2781 * is special cased for current process only, but
2782 * can have the more generic (and slightly slower)
2783 * mode enabled. This is much faster than pmap_remove
2784 * in the case of running down an entire address space.
2787 pmap_remove_pages(pmap_t pmap)
2790 pt_entry_t *pte, tpte;
2793 struct pv_chunk *pc, *npc;
2794 u_long inuse, bitmask;
2795 int allfree, bit, field, idx;
2797 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
2798 printf("warning: pmap_remove_pages called with non-current pmap\n");
2801 rw_wlock(&pvh_global_lock);
2803 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2805 for (field = 0; field < _NPCM; field++) {
2806 inuse = ~pc->pc_map[field] & pc_freemask[field];
2807 while (inuse != 0) {
2808 bit = ffsl(inuse) - 1;
2809 bitmask = 1UL << bit;
2810 idx = field * sizeof(inuse) * NBBY + bit;
2811 pv = &pc->pc_pventry[idx];
2814 pde = pmap_pde(pmap, pv->pv_va);
2815 KASSERT(pde != NULL && *pde != 0,
2816 ("pmap_remove_pages: pde"));
2817 pte = pmap_pde_to_pte(pde, pv->pv_va);
2818 if (!pte_test(pte, PTE_V))
2819 panic("pmap_remove_pages: bad pte");
2823 * We cannot remove wired pages from a process' mapping at this time
2825 if (pte_test(&tpte, PTE_W)) {
2829 *pte = is_kernel_pmap(pmap) ? PTE_G : 0;
2831 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte));
2833 ("pmap_remove_pages: bad tpte %#jx",
2837 * Update the vm_page_t clean and reference bits.
2839 if (pte_test(&tpte, PTE_D))
2843 PV_STAT(pv_entry_frees++);
2844 PV_STAT(pv_entry_spare++);
2846 pc->pc_map[field] |= bitmask;
2847 pmap->pm_stats.resident_count--;
2848 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2849 if (TAILQ_EMPTY(&m->md.pv_list))
2850 vm_page_aflag_clear(m, PGA_WRITEABLE);
2851 pmap_unuse_pt(pmap, pv->pv_va, *pde);
2855 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2859 pmap_invalidate_all(pmap);
2861 rw_wunlock(&pvh_global_lock);
2865 * pmap_testbit tests bits in pte's
2868 pmap_testbit(vm_page_t m, int bit)
2873 boolean_t rv = FALSE;
2875 if (m->oflags & VPO_UNMANAGED)
2878 rw_assert(&pvh_global_lock, RA_WLOCKED);
2879 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2882 pte = pmap_pte(pmap, pv->pv_va);
2883 rv = pte_test(pte, bit);
2892 * pmap_page_wired_mappings:
2894 * Return the number of managed mappings to the given physical page
2898 pmap_page_wired_mappings(vm_page_t m)
2906 if ((m->oflags & VPO_UNMANAGED) != 0)
2908 rw_wlock(&pvh_global_lock);
2909 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2912 pte = pmap_pte(pmap, pv->pv_va);
2913 if (pte_test(pte, PTE_W))
2917 rw_wunlock(&pvh_global_lock);
2922 * Clear the write and modified bits in each of the given page's mappings.
2925 pmap_remove_write(vm_page_t m)
2928 pt_entry_t pbits, *pte;
2931 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2932 ("pmap_remove_write: page %p is not managed", m));
2935 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
2936 * set by another thread while the object is locked. Thus,
2937 * if PGA_WRITEABLE is clear, no page table entries need updating.
2939 VM_OBJECT_ASSERT_WLOCKED(m->object);
2940 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
2942 rw_wlock(&pvh_global_lock);
2943 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2946 pte = pmap_pte(pmap, pv->pv_va);
2947 KASSERT(pte != NULL && pte_test(pte, PTE_V),
2948 ("page on pv_list has no pte"));
2950 if (pte_test(&pbits, PTE_D)) {
2951 pte_clear(&pbits, PTE_D);
2954 pte_set(&pbits, PTE_RO);
2955 if (pbits != *pte) {
2957 pmap_update_page(pmap, pv->pv_va, pbits);
2961 vm_page_aflag_clear(m, PGA_WRITEABLE);
2962 rw_wunlock(&pvh_global_lock);
2966 * pmap_ts_referenced:
2968 * Return the count of reference bits for a page, clearing all of them.
2971 pmap_ts_referenced(vm_page_t m)
2974 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2975 ("pmap_ts_referenced: page %p is not managed", m));
2976 if (m->md.pv_flags & PV_TABLE_REF) {
2977 rw_wlock(&pvh_global_lock);
2978 m->md.pv_flags &= ~PV_TABLE_REF;
2979 rw_wunlock(&pvh_global_lock);
2988 * Return whether or not the specified physical page was modified
2989 * in any physical maps.
2992 pmap_is_modified(vm_page_t m)
2996 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2997 ("pmap_is_modified: page %p is not managed", m));
3000 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
3001 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
3002 * is clear, no PTEs can have PTE_D set.
3004 VM_OBJECT_ASSERT_WLOCKED(m->object);
3005 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
3007 rw_wlock(&pvh_global_lock);
3008 rv = pmap_testbit(m, PTE_D);
3009 rw_wunlock(&pvh_global_lock);
3016 * pmap_is_prefaultable:
3018 * Return whether or not the specified virtual address is elgible
3022 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
3030 pde = pmap_pde(pmap, addr);
3031 if (pde != NULL && *pde != 0) {
3032 pte = pmap_pde_to_pte(pde, addr);
3040 * Apply the given advice to the specified range of addresses within the
3041 * given pmap. Depending on the advice, clear the referenced and/or
3042 * modified flags in each mapping and set the mapped page's dirty field.
3045 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3047 pd_entry_t *pde, *pdpe;
3049 vm_offset_t va, va_next;
3053 if (advice != MADV_DONTNEED && advice != MADV_FREE)
3055 rw_wlock(&pvh_global_lock);
3057 for (; sva < eva; sva = va_next) {
3058 pdpe = pmap_segmap(pmap, sva);
3061 va_next = (sva + NBSEG) & ~SEGMASK;
3067 va_next = (sva + NBPDR) & ~PDRMASK;
3071 pde = pmap_pdpe_to_pde(pdpe, sva);
3076 * Limit our scan to either the end of the va represented
3077 * by the current page table page, or to the end of the
3078 * range being write protected.
3084 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3086 if (!pte_test(pte, PTE_MANAGED | PTE_V)) {
3087 if (va != va_next) {
3088 pmap_invalidate_range(pmap, va, sva);
3093 pa = TLBLO_PTE_TO_PA(*pte);
3094 m = PHYS_TO_VM_PAGE(pa);
3095 m->md.pv_flags &= ~PV_TABLE_REF;
3096 if (pte_test(pte, PTE_D)) {
3097 if (advice == MADV_DONTNEED) {
3099 * Future calls to pmap_is_modified()
3100 * can be avoided by making the page
3105 pte_clear(pte, PTE_D);
3111 * Unless PTE_D is set, any TLB entries
3112 * mapping "sva" don't allow write access, so
3113 * they needn't be invalidated.
3115 if (va != va_next) {
3116 pmap_invalidate_range(pmap, va, sva);
3122 pmap_invalidate_range(pmap, va, sva);
3124 rw_wunlock(&pvh_global_lock);
3129 * Clear the modify bits on the specified physical page.
3132 pmap_clear_modify(vm_page_t m)
3138 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3139 ("pmap_clear_modify: page %p is not managed", m));
3140 VM_OBJECT_ASSERT_WLOCKED(m->object);
3141 KASSERT(!vm_page_xbusied(m),
3142 ("pmap_clear_modify: page %p is exclusive busied", m));
3145 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set.
3146 * If the object containing the page is locked and the page is not
3147 * write busied, then PGA_WRITEABLE cannot be concurrently set.
3149 if ((m->aflags & PGA_WRITEABLE) == 0)
3151 rw_wlock(&pvh_global_lock);
3152 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3155 pte = pmap_pte(pmap, pv->pv_va);
3156 if (pte_test(pte, PTE_D)) {
3157 pte_clear(pte, PTE_D);
3158 pmap_update_page(pmap, pv->pv_va, *pte);
3162 rw_wunlock(&pvh_global_lock);
3166 * pmap_is_referenced:
3168 * Return whether or not the specified physical page was referenced
3169 * in any physical maps.
3172 pmap_is_referenced(vm_page_t m)
3175 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3176 ("pmap_is_referenced: page %p is not managed", m));
3177 return ((m->md.pv_flags & PV_TABLE_REF) != 0);
3181 * Miscellaneous support routines follow
3185 * Map a set of physical memory pages into the kernel virtual
3186 * address space. Return a pointer to where it is mapped. This
3187 * routine is intended to be used for mapping device memory,
3190 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit.
3193 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3195 vm_offset_t va, tmpva, offset;
3198 * KSEG1 maps only first 512M of phys address space. For
3199 * pa > 0x20000000 we should make proper mapping * using pmap_kenter.
3201 if (MIPS_DIRECT_MAPPABLE(pa + size - 1) && ma == VM_MEMATTR_UNCACHEABLE)
3202 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
3204 offset = pa & PAGE_MASK;
3205 size = roundup(size + offset, PAGE_SIZE);
3207 va = kva_alloc(size);
3209 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3210 pa = trunc_page(pa);
3211 for (tmpva = va; size > 0;) {
3212 pmap_kenter_attr(tmpva, pa, ma);
3219 return ((void *)(va + offset));
3223 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3225 return pmap_mapdev_attr(pa, size, VM_MEMATTR_UNCACHEABLE);
3229 pmap_unmapdev(vm_offset_t va, vm_size_t size)
3232 vm_offset_t base, offset;
3234 /* If the address is within KSEG1 then there is nothing to do */
3235 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
3238 base = trunc_page(va);
3239 offset = va & PAGE_MASK;
3240 size = roundup(size + offset, PAGE_SIZE);
3241 kva_free(base, size);
3246 * perform the pmap work for mincore
3249 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3251 pt_entry_t *ptep, pte;
3258 ptep = pmap_pte(pmap, addr);
3259 pte = (ptep != NULL) ? *ptep : 0;
3260 if (!pte_test(&pte, PTE_V)) {
3264 val = MINCORE_INCORE;
3265 if (pte_test(&pte, PTE_D))
3266 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3267 pa = TLBLO_PTE_TO_PA(pte);
3268 if (pte_test(&pte, PTE_MANAGED)) {
3270 * This may falsely report the given address as
3271 * MINCORE_REFERENCED. Unfortunately, due to the lack of
3272 * per-PTE reference information, it is impossible to
3273 * determine if the address is MINCORE_REFERENCED.
3275 m = PHYS_TO_VM_PAGE(pa);
3276 if ((m->aflags & PGA_REFERENCED) != 0)
3277 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3279 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3280 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
3281 pte_test(&pte, PTE_MANAGED)) {
3282 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3283 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3287 PA_UNLOCK_COND(*locked_pa);
3293 pmap_activate(struct thread *td)
3295 pmap_t pmap, oldpmap;
3296 struct proc *p = td->td_proc;
3301 pmap = vmspace_pmap(p->p_vmspace);
3302 oldpmap = PCPU_GET(curpmap);
3303 cpuid = PCPU_GET(cpuid);
3306 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
3307 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
3308 pmap_asid_alloc(pmap);
3309 if (td == curthread) {
3310 PCPU_SET(segbase, pmap->pm_segtab);
3311 mips_wr_entryhi(pmap->pm_asid[cpuid].asid);
3314 PCPU_SET(curpmap, pmap);
3319 pmap_sync_icache_one(void *arg __unused)
3322 mips_icache_sync_all();
3323 mips_dcache_wbinv_all();
3327 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3330 smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
3334 * Increase the starting virtual address of the given mapping if a
3335 * different alignment might result in more superpage mappings.
3338 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3339 vm_offset_t *addr, vm_size_t size)
3341 vm_offset_t superpage_offset;
3345 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
3346 offset += ptoa(object->pg_color);
3347 superpage_offset = offset & PDRMASK;
3348 if (size - ((PDRSIZE - superpage_offset) & PDRMASK) < PDRSIZE ||
3349 (*addr & PDRMASK) == superpage_offset)
3351 if ((*addr & PDRMASK) < superpage_offset)
3352 *addr = (*addr & ~PDRMASK) + superpage_offset;
3354 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
3358 DB_SHOW_COMMAND(ptable, ddb_pid_dump)
3361 struct thread *td = NULL;
3368 td = db_lookup_thread(addr, true);
3370 db_printf("Invalid pid or tid");
3374 if (p->p_vmspace == NULL) {
3375 db_printf("No vmspace for process");
3378 pmap = vmspace_pmap(p->p_vmspace);
3382 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n",
3383 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid,
3384 pmap->pm_asid[0].gen);
3385 for (i = 0; i < NPDEPG; i++) {
3390 pdpe = (pd_entry_t *)pmap->pm_segtab[i];
3393 db_printf("[%4d] %p\n", i, pdpe);
3395 for (j = 0; j < NPDEPG; j++) {
3396 pde = (pt_entry_t *)pdpe[j];
3399 db_printf("\t[%4d] %p\n", j, pde);
3403 pde = (pt_entry_t *)pdpe;
3405 for (k = 0; k < NPTEPG; k++) {
3407 if (pte == 0 || !pte_test(&pte, PTE_V))
3409 pa = TLBLO_PTE_TO_PA(pte);
3410 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT);
3411 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n",
3412 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa);
3420 * Allocate TLB address space tag (called ASID or TLBPID) and return it.
3421 * It takes almost as much or more time to search the TLB for a
3422 * specific ASID and flush those entries as it does to flush the entire TLB.
3423 * Therefore, when we allocate a new ASID, we just take the next number. When
3424 * we run out of numbers, we flush the TLB, increment the generation count
3425 * and start over. ASID zero is reserved for kernel use.
3428 pmap_asid_alloc(pmap)
3431 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED &&
3432 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
3434 if (PCPU_GET(next_asid) == pmap_max_asid) {
3435 tlb_invalidate_all_user(NULL);
3436 PCPU_SET(asid_generation,
3437 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
3438 if (PCPU_GET(asid_generation) == 0) {
3439 PCPU_SET(asid_generation, 1);
3441 PCPU_SET(next_asid, 1); /* 0 means invalid */
3443 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid);
3444 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation);
3445 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1);
3450 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot)
3454 if (!(prot & VM_PROT_WRITE))
3455 rw = PTE_V | PTE_RO;
3456 else if ((m->oflags & VPO_UNMANAGED) == 0) {
3457 if ((access & VM_PROT_WRITE) != 0)
3462 /* Needn't emulate a modified bit for unmanaged pages. */
3468 * pmap_emulate_modified : do dirty bit emulation
3470 * On SMP, update just the local TLB, other CPUs will update their
3471 * TLBs from PTE lazily, if they get the exception.
3472 * Returns 0 in case of sucess, 1 if the page is read only and we
3476 pmap_emulate_modified(pmap_t pmap, vm_offset_t va)
3481 pte = pmap_pte(pmap, va);
3483 panic("pmap_emulate_modified: can't find PTE");
3485 /* It is possible that some other CPU changed m-bit */
3486 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) {
3487 tlb_update(pmap, va, *pte);
3492 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D))
3493 panic("pmap_emulate_modified: invalid pte");
3495 if (pte_test(pte, PTE_RO)) {
3499 pte_set(pte, PTE_D);
3500 tlb_update(pmap, va, *pte);
3501 if (!pte_test(pte, PTE_MANAGED))
3502 panic("pmap_emulate_modified: unmanaged page");
3508 * Routine: pmap_kextract
3510 * Extract the physical page address associated
3514 pmap_kextract(vm_offset_t va)
3519 * First, the direct-mapped regions.
3521 #if defined(__mips_n64)
3522 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
3523 return (MIPS_XKPHYS_TO_PHYS(va));
3525 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
3526 return (MIPS_KSEG0_TO_PHYS(va));
3528 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
3529 return (MIPS_KSEG1_TO_PHYS(va));
3532 * User virtual addresses.
3534 if (va < VM_MAXUSER_ADDRESS) {
3537 if (curproc && curproc->p_vmspace) {
3538 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
3540 return (TLBLO_PTE_TO_PA(*ptep) |
3548 * Should be kernel virtual here, otherwise fail
3550 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
3551 #if defined(__mips_n64)
3552 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
3561 /* Is the kernel pmap initialized? */
3562 if (!CPU_EMPTY(&kernel_pmap->pm_active)) {
3563 /* It's inside the virtual address range */
3564 ptep = pmap_pte(kernel_pmap, va);
3566 return (TLBLO_PTE_TO_PA(*ptep) |
3573 panic("%s for unknown address space %p.", __func__, (void *)va);
3578 pmap_flush_pvcache(vm_page_t m)
3583 for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
3584 pv = TAILQ_NEXT(pv, pv_list)) {
3585 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
3591 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3595 * It appears that this function can only be called before any mappings
3596 * for the page are established. If this ever changes, this code will
3597 * need to walk the pv_list and make each of the existing mappings
3598 * uncacheable, being careful to sync caches and PTEs (and maybe
3599 * invalidate TLB?) for any current mapping it modifies.
3601 if (TAILQ_FIRST(&m->md.pv_list) != NULL)
3602 panic("Can't change memattr on page with existing mappings");
3604 /* Clean memattr portion of pv_flags */
3605 m->md.pv_flags &= ~PV_MEMATTR_MASK;
3606 m->md.pv_flags |= (ma << PV_MEMATTR_SHIFT) & PV_MEMATTR_MASK;
3609 static __inline void
3610 pmap_pte_attr(pt_entry_t *pte, vm_memattr_t ma)
3614 npte = *(u_int *)pte;
3615 npte &= ~PTE_C_MASK;
3621 pmap_change_attr(vm_offset_t sva, vm_size_t size, vm_memattr_t ma)
3623 pd_entry_t *pde, *pdpe;
3625 vm_offset_t ova, eva, va, va_next;
3636 for (; sva < eva; sva = va_next) {
3637 pdpe = pmap_segmap(pmap, sva);
3640 va_next = (sva + NBSEG) & ~SEGMASK;
3646 va_next = (sva + NBPDR) & ~PDRMASK;
3650 pde = pmap_pdpe_to_pde(pdpe, sva);
3655 * Limit our scan to either the end of the va represented
3656 * by the current page table page, or to the end of the
3657 * range being removed.
3663 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3665 if (!pte_test(pte, PTE_V) || pte_cache_bits(pte) == ma) {
3666 if (va != va_next) {
3667 pmap_invalidate_range(pmap, va, sva);
3675 pmap_pte_attr(pte, ma);
3678 pmap_invalidate_range(pmap, va, sva);
3682 /* Flush caches to be in the safe side */
3683 mips_dcache_wbinv_range(ova, size);
3688 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
3692 case VM_MEMATTR_UNCACHEABLE:
3693 case VM_MEMATTR_WRITE_BACK:
3695 case VM_MEMATTR_WRITE_COMBINING: