2 * Copyright (c) 1991 Regents of the University of California.
4 * Copyright (c) 1994 John S. Dyson
6 * Copyright (c) 1994 David Greenman
9 * This code is derived from software contributed to Berkeley by
10 * the Systems Programming Group of the University of Utah Computer
11 * Science Department and William Jolitz of UUNET Technologies Inc.
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 * 4. Neither the name of the University nor the names of its contributors
22 * may be used to endorse or promote products derived from this software
23 * without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
26 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
28 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
31 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
32 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
33 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
34 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
37 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
38 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps
39 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish
43 * Manages physical address maps.
45 * Since the information managed by this module is
46 * also stored by the logical address mapping module,
47 * this module may throw away valid virtual-to-physical
48 * mappings at almost any time. However, invalidations
49 * of virtual-to-physical mappings must be done as
52 * In order to cope with hardware architectures which
53 * make virtual-to-physical map invalidates expensive,
54 * this module may delay invalidate or reduced protection
55 * operations until such time as they are actually
56 * necessary. This module is given full information as
57 * to which processors are currently using which maps,
58 * and to when physical maps must be made correct.
61 #include <sys/cdefs.h>
62 __FBSDID("$FreeBSD$");
67 #include <sys/param.h>
68 #include <sys/systm.h>
71 #include <sys/msgbuf.h>
72 #include <sys/mutex.h>
75 #include <sys/rwlock.h>
76 #include <sys/sched.h>
80 #include <sys/cpuset.h>
82 #include <sys/sysctl.h>
83 #include <sys/vmmeter.h>
90 #include <vm/vm_param.h>
91 #include <vm/vm_kern.h>
92 #include <vm/vm_page.h>
93 #include <vm/vm_map.h>
94 #include <vm/vm_object.h>
95 #include <vm/vm_extern.h>
96 #include <vm/vm_pageout.h>
97 #include <vm/vm_pager.h>
100 #include <machine/cache.h>
101 #include <machine/md_var.h>
102 #include <machine/tlb.h>
106 #if !defined(DIAGNOSTIC)
107 #define PMAP_INLINE __inline
113 #define PV_STAT(x) do { x ; } while (0)
115 #define PV_STAT(x) do { } while (0)
119 * Get PDEs and PTEs for user/kernel address space
121 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
122 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1))
123 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1))
124 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT)
127 #define NUPDE (NPDEPG * NPDEPG)
128 #define NUSERPGTBLS (NUPDE + NPDEPG)
130 #define NUPDE (NPDEPG)
131 #define NUSERPGTBLS (NUPDE)
134 #define is_kernel_pmap(x) ((x) == kernel_pmap)
136 struct pmap kernel_pmap_store;
137 pd_entry_t *kernel_segmap;
139 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
140 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
143 unsigned pmap_max_asid; /* max ASID supported by the system */
145 #define PMAP_ASID_RESERVED 0
147 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
149 static void pmap_asid_alloc(pmap_t pmap);
151 static struct rwlock_padalign pvh_global_lock;
154 * Data for the pv entry allocation mechanism
156 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
157 static int pv_entry_count;
159 static void free_pv_chunk(struct pv_chunk *pc);
160 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
161 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
162 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
163 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
164 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
166 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req);
167 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
168 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
169 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
171 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
172 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
173 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
174 vm_offset_t va, vm_page_t m);
175 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
176 static void pmap_invalidate_all(pmap_t pmap);
177 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
178 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m);
180 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags);
181 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags);
182 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t);
183 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot);
185 static void pmap_invalidate_page_action(void *arg);
186 static void pmap_invalidate_range_action(void *arg);
187 static void pmap_update_page_action(void *arg);
191 * This structure is for high memory (memory above 512Meg in 32 bit) support.
192 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to
193 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc.
195 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To
196 * access a highmem physical address on a CPU, we map the physical address to
197 * the reserved virtual address for the CPU in the kernel pagetable. This is
198 * done with interrupts disabled(although a spinlock and sched_pin would be
201 struct local_sysmaps {
204 uint16_t valid1, valid2;
206 static struct local_sysmaps sysmap_lmem[MAXCPU];
209 pmap_alloc_lmem_map(void)
213 for (i = 0; i < MAXCPU; i++) {
214 sysmap_lmem[i].base = virtual_avail;
215 virtual_avail += PAGE_SIZE * 2;
216 sysmap_lmem[i].valid1 = sysmap_lmem[i].valid2 = 0;
220 static __inline vm_offset_t
221 pmap_lmem_map1(vm_paddr_t phys)
223 struct local_sysmaps *sysm;
224 pt_entry_t *pte, npte;
229 intr = intr_disable();
230 cpu = PCPU_GET(cpuid);
231 sysm = &sysmap_lmem[cpu];
232 sysm->saved_intr = intr;
234 npte = TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
235 pte = pmap_pte(kernel_pmap, va);
241 static __inline vm_offset_t
242 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
244 struct local_sysmaps *sysm;
245 pt_entry_t *pte, npte;
246 vm_offset_t va1, va2;
250 intr = intr_disable();
251 cpu = PCPU_GET(cpuid);
252 sysm = &sysmap_lmem[cpu];
253 sysm->saved_intr = intr;
255 va2 = sysm->base + PAGE_SIZE;
256 npte = TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
257 pte = pmap_pte(kernel_pmap, va1);
259 npte = TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
260 pte = pmap_pte(kernel_pmap, va2);
268 pmap_lmem_unmap(void)
270 struct local_sysmaps *sysm;
274 cpu = PCPU_GET(cpuid);
275 sysm = &sysmap_lmem[cpu];
276 pte = pmap_pte(kernel_pmap, sysm->base);
278 tlb_invalidate_address(kernel_pmap, sysm->base);
281 pte = pmap_pte(kernel_pmap, sysm->base + PAGE_SIZE);
283 tlb_invalidate_address(kernel_pmap, sysm->base + PAGE_SIZE);
286 intr_restore(sysm->saved_intr);
288 #else /* __mips_n64 */
291 pmap_alloc_lmem_map(void)
295 static __inline vm_offset_t
296 pmap_lmem_map1(vm_paddr_t phys)
302 static __inline vm_offset_t
303 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
309 static __inline vm_offset_t
310 pmap_lmem_unmap(void)
315 #endif /* !__mips_n64 */
318 * Page table entry lookup routines.
320 static __inline pd_entry_t *
321 pmap_segmap(pmap_t pmap, vm_offset_t va)
324 return (&pmap->pm_segtab[pmap_seg_index(va)]);
328 static __inline pd_entry_t *
329 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
333 pde = (pd_entry_t *)*pdpe;
334 return (&pde[pmap_pde_index(va)]);
337 static __inline pd_entry_t *
338 pmap_pde(pmap_t pmap, vm_offset_t va)
342 pdpe = pmap_segmap(pmap, va);
346 return (pmap_pdpe_to_pde(pdpe, va));
349 static __inline pd_entry_t *
350 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
357 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va)
360 return (pmap_segmap(pmap, va));
364 static __inline pt_entry_t *
365 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
369 pte = (pt_entry_t *)*pde;
370 return (&pte[pmap_pte_index(va)]);
374 pmap_pte(pmap_t pmap, vm_offset_t va)
378 pde = pmap_pde(pmap, va);
379 if (pde == NULL || *pde == NULL)
382 return (pmap_pde_to_pte(pde, va));
386 pmap_steal_memory(vm_size_t size)
388 vm_paddr_t bank_size, pa;
391 size = round_page(size);
392 bank_size = phys_avail[1] - phys_avail[0];
393 while (size > bank_size) {
396 for (i = 0; phys_avail[i + 2]; i += 2) {
397 phys_avail[i] = phys_avail[i + 2];
398 phys_avail[i + 1] = phys_avail[i + 3];
401 phys_avail[i + 1] = 0;
403 panic("pmap_steal_memory: out of memory");
404 bank_size = phys_avail[1] - phys_avail[0];
408 phys_avail[0] += size;
409 if (MIPS_DIRECT_MAPPABLE(pa) == 0)
410 panic("Out of memory below 512Meg?");
411 va = MIPS_PHYS_TO_DIRECT(pa);
412 bzero((caddr_t)va, size);
417 * Bootstrap the system enough to run with virtual memory. This
418 * assumes that the phys_avail array has been initialized.
421 pmap_create_kernel_pagetable(void)
433 * Allocate segment table for the kernel
435 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE);
438 * Allocate second level page tables for the kernel
441 npde = howmany(NKPT, NPDEPG);
442 pdaddr = pmap_steal_memory(PAGE_SIZE * npde);
445 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt);
448 * The R[4-7]?00 stores only one copy of the Global bit in the
449 * translation lookaside buffer for each 2 page entry. Thus invalid
450 * entrys must have the Global bit set so when Entry LO and Entry HI
451 * G bits are anded together they will produce a global bit to store
454 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++)
458 for (i = 0, npt = nkpt; npt > 0; i++) {
459 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE);
460 pde = (pd_entry_t *)kernel_segmap[i];
462 for (j = 0; j < NPDEPG && npt > 0; j++, npt--)
463 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE);
466 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++)
467 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE));
470 PMAP_LOCK_INIT(kernel_pmap);
471 kernel_pmap->pm_segtab = kernel_segmap;
472 CPU_FILL(&kernel_pmap->pm_active);
473 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
474 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
475 kernel_pmap->pm_asid[0].gen = 0;
476 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE;
483 int need_local_mappings = 0;
487 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
489 * Keep the memory aligned on page boundary.
491 phys_avail[i] = round_page(phys_avail[i]);
492 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
496 if (phys_avail[i - 2] > phys_avail[i]) {
499 ptemp[0] = phys_avail[i + 0];
500 ptemp[1] = phys_avail[i + 1];
502 phys_avail[i + 0] = phys_avail[i - 2];
503 phys_avail[i + 1] = phys_avail[i - 1];
505 phys_avail[i - 2] = ptemp[0];
506 phys_avail[i - 1] = ptemp[1];
512 * In 32 bit, we may have memory which cannot be mapped directly.
513 * This memory will need temporary mapping before it can be
516 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1))
517 need_local_mappings = 1;
520 * Copy the phys_avail[] array before we start stealing memory from it.
522 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
523 physmem_desc[i] = phys_avail[i];
524 physmem_desc[i + 1] = phys_avail[i + 1];
527 Maxmem = atop(phys_avail[i - 1]);
530 printf("Physical memory chunk(s):\n");
531 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
534 size = phys_avail[i + 1] - phys_avail[i];
535 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n",
536 (uintmax_t) phys_avail[i],
537 (uintmax_t) phys_avail[i + 1] - 1,
538 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE);
540 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem));
543 * Steal the message buffer from the beginning of memory.
545 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize);
546 msgbufinit(msgbufp, msgbufsize);
549 * Steal thread0 kstack.
551 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
553 virtual_avail = VM_MIN_KERNEL_ADDRESS;
554 virtual_end = VM_MAX_KERNEL_ADDRESS;
558 * Steal some virtual address space to map the pcpu area.
560 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2);
561 pcpup = (struct pcpu *)virtual_avail;
562 virtual_avail += PAGE_SIZE * 2;
565 * Initialize the wired TLB entry mapping the pcpu region for
566 * the BSP at 'pcpup'. Up until this point we were operating
567 * with the 'pcpup' for the BSP pointing to a virtual address
568 * in KSEG0 so there was no need for a TLB mapping.
570 mips_pcpu_tlb_init(PCPU_ADDR(0));
573 printf("pcpu is available at virtual address %p.\n", pcpup);
576 if (need_local_mappings)
577 pmap_alloc_lmem_map();
578 pmap_create_kernel_pagetable();
579 pmap_max_asid = VMNUM_PIDS;
584 * Initialize the global pv list lock.
586 rw_init(&pvh_global_lock, "pmap pv global");
590 * Initialize a vm_page's machine-dependent fields.
593 pmap_page_init(vm_page_t m)
596 TAILQ_INIT(&m->md.pv_list);
601 * Initialize the pmap module.
602 * Called by vm_init, to initialize any structures that the pmap
603 * system needs to map virtual memory.
610 /***************************************************
611 * Low level helper routines.....
612 ***************************************************/
616 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
618 int cpuid, cpu, self;
619 cpuset_t active_cpus;
622 if (is_kernel_pmap(pmap)) {
623 smp_rendezvous(NULL, fn, NULL, arg);
626 /* Force ASID update on inactive CPUs */
628 if (!CPU_ISSET(cpu, &pmap->pm_active))
629 pmap->pm_asid[cpu].gen = 0;
631 cpuid = PCPU_GET(cpuid);
633 * XXX: barrier/locking for active?
635 * Take a snapshot of active here, any further changes are ignored.
636 * tlb update/invalidate should be harmless on inactive CPUs
638 active_cpus = pmap->pm_active;
639 self = CPU_ISSET(cpuid, &active_cpus);
640 CPU_CLR(cpuid, &active_cpus);
641 /* Optimize for the case where this cpu is the only active one */
642 if (CPU_EMPTY(&active_cpus)) {
647 CPU_SET(cpuid, &active_cpus);
648 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg);
655 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
659 if (is_kernel_pmap(pmap)) {
663 cpuid = PCPU_GET(cpuid);
664 if (!CPU_ISSET(cpuid, &pmap->pm_active))
665 pmap->pm_asid[cpuid].gen = 0;
672 pmap_invalidate_all(pmap_t pmap)
675 pmap_call_on_active_cpus(pmap,
676 (void (*)(void *))tlb_invalidate_all_user, pmap);
679 struct pmap_invalidate_page_arg {
685 pmap_invalidate_page_action(void *arg)
687 struct pmap_invalidate_page_arg *p = arg;
689 tlb_invalidate_address(p->pmap, p->va);
693 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
695 struct pmap_invalidate_page_arg arg;
699 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg);
702 struct pmap_invalidate_range_arg {
709 pmap_invalidate_range_action(void *arg)
711 struct pmap_invalidate_range_arg *p = arg;
713 tlb_invalidate_range(p->pmap, p->sva, p->eva);
717 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
719 struct pmap_invalidate_range_arg arg;
724 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg);
727 struct pmap_update_page_arg {
734 pmap_update_page_action(void *arg)
736 struct pmap_update_page_arg *p = arg;
738 tlb_update(p->pmap, p->va, p->pte);
742 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte)
744 struct pmap_update_page_arg arg;
749 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg);
753 * Routine: pmap_extract
755 * Extract the physical page address associated
756 * with the given map/virtual_address pair.
759 pmap_extract(pmap_t pmap, vm_offset_t va)
762 vm_offset_t retval = 0;
765 pte = pmap_pte(pmap, va);
767 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK);
774 * Routine: pmap_extract_and_hold
776 * Atomically extract and hold the physical page
777 * with the given pmap and virtual address pair
778 * if that mapping permits the given protection.
781 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
783 pt_entry_t pte, *ptep;
784 vm_paddr_t pa, pte_pa;
791 ptep = pmap_pte(pmap, va);
794 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) ||
795 (prot & VM_PROT_WRITE) == 0)) {
796 pte_pa = TLBLO_PTE_TO_PA(pte);
797 if (vm_page_pa_tryrelock(pmap, pte_pa, &pa))
799 m = PHYS_TO_VM_PAGE(pte_pa);
808 /***************************************************
809 * Low level mapping routines.....
810 ***************************************************/
813 * add a wired page to the kva
816 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int attr)
819 pt_entry_t opte, npte;
822 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
825 pte = pmap_pte(kernel_pmap, va);
827 npte = TLBLO_PA_TO_PFN(pa) | attr | PTE_D | PTE_V | PTE_G;
829 if (pte_test(&opte, PTE_V) && opte != npte)
830 pmap_update_page(kernel_pmap, va, npte);
834 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
837 KASSERT(is_cacheable_mem(pa),
838 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa));
840 pmap_kenter_attr(va, pa, PTE_C_CACHE);
844 * remove a page from the kernel pagetables
846 /* PMAP_INLINE */ void
847 pmap_kremove(vm_offset_t va)
852 * Write back all caches from the page being destroyed
854 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
856 pte = pmap_pte(kernel_pmap, va);
858 pmap_invalidate_page(kernel_pmap, va);
862 * Used to map a range of physical addresses into kernel
863 * virtual address space.
865 * The value passed in '*virt' is a suggested virtual address for
866 * the mapping. Architectures which can support a direct-mapped
867 * physical to virtual region can return the appropriate address
868 * within that region, leaving '*virt' unchanged. Other
869 * architectures should map the pages starting at '*virt' and
870 * update '*virt' with the first usable address after the mapped
873 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
876 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
880 if (MIPS_DIRECT_MAPPABLE(end - 1))
881 return (MIPS_PHYS_TO_DIRECT(start));
884 while (start < end) {
885 pmap_kenter(va, start);
894 * Add a list of wired pages to the kva
895 * this routine is only used for temporary
896 * kernel mappings that do not need to have
897 * page modification or references recorded.
898 * Note that old mappings are simply written
899 * over. The page *must* be wired.
902 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
905 vm_offset_t origva = va;
907 for (i = 0; i < count; i++) {
908 pmap_flush_pvcache(m[i]);
909 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i]));
913 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count);
917 * this routine jerks page mappings from the
918 * kernel -- it is meant only for temporary mappings.
921 pmap_qremove(vm_offset_t va, int count)
928 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count);
931 pte = pmap_pte(kernel_pmap, va);
934 } while (--count > 0);
935 pmap_invalidate_range(kernel_pmap, origva, va);
938 /***************************************************
939 * Page table page management routines.....
940 ***************************************************/
943 * Decrements a page table page's wire count, which is used to record the
944 * number of valid page table entries within the page. If the wire count
945 * drops to zero, then the page table page is unmapped. Returns TRUE if the
946 * page table page was unmapped and FALSE otherwise.
948 static PMAP_INLINE boolean_t
949 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
953 if (m->wire_count == 0) {
954 _pmap_unwire_ptp(pmap, va, m);
961 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
965 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
967 * unmap the page table page
970 if (m->pindex < NUPDE)
971 pde = pmap_pde(pmap, va);
973 pde = pmap_segmap(pmap, va);
975 pde = pmap_pde(pmap, va);
978 pmap->pm_stats.resident_count--;
981 if (m->pindex < NUPDE) {
986 * Recursively decrement next level pagetable refcount
988 pdp = (pd_entry_t *)*pmap_segmap(pmap, va);
989 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp));
990 pmap_unwire_ptp(pmap, va, pdpg);
995 * If the page is finally unwired, simply free it.
997 vm_page_free_zero(m);
998 atomic_subtract_int(&cnt.v_wire_count, 1);
1002 * After removing a page table entry, this routine is used to
1003 * conditionally free the page, and manage the hold/wire counts.
1006 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1010 if (va >= VM_MAXUSER_ADDRESS)
1012 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0"));
1013 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde));
1014 return (pmap_unwire_ptp(pmap, va, mpte));
1018 pmap_pinit0(pmap_t pmap)
1022 PMAP_LOCK_INIT(pmap);
1023 pmap->pm_segtab = kernel_segmap;
1024 CPU_ZERO(&pmap->pm_active);
1025 for (i = 0; i < MAXCPU; i++) {
1026 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1027 pmap->pm_asid[i].gen = 0;
1029 PCPU_SET(curpmap, pmap);
1030 TAILQ_INIT(&pmap->pm_pvchunk);
1031 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1035 pmap_grow_direct_page_cache()
1039 vm_pageout_grow_cache(3, 0, MIPS_XKPHYS_LARGEST_PHYS);
1041 vm_pageout_grow_cache(3, 0, MIPS_KSEG0_LARGEST_PHYS);
1046 pmap_alloc_direct_page(unsigned int index, int req)
1050 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED |
1055 if ((m->flags & PG_ZERO) == 0)
1063 * Initialize a preallocated and zeroed pmap structure,
1064 * such as one in a vmspace structure.
1067 pmap_pinit(pmap_t pmap)
1073 PMAP_LOCK_INIT(pmap);
1076 * allocate the page directory page
1078 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, VM_ALLOC_NORMAL)) == NULL)
1079 pmap_grow_direct_page_cache();
1081 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg));
1082 pmap->pm_segtab = (pd_entry_t *)ptdva;
1083 CPU_ZERO(&pmap->pm_active);
1084 for (i = 0; i < MAXCPU; i++) {
1085 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1086 pmap->pm_asid[i].gen = 0;
1088 TAILQ_INIT(&pmap->pm_pvchunk);
1089 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1095 * this routine is called if the page table page is not
1099 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, int flags)
1104 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1105 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1106 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1109 * Find or fabricate a new pagetable page
1111 if ((m = pmap_alloc_direct_page(ptepindex, VM_ALLOC_NORMAL)) == NULL) {
1112 if (flags & M_WAITOK) {
1114 rw_wunlock(&pvh_global_lock);
1115 pmap_grow_direct_page_cache();
1116 rw_wlock(&pvh_global_lock);
1121 * Indicate the need to retry. While waiting, the page
1122 * table page may have been allocated.
1128 * Map the pagetable page into the process address space, if it
1129 * isn't already there.
1131 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1134 if (ptepindex >= NUPDE) {
1135 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva;
1137 pd_entry_t *pdep, *pde;
1138 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT);
1139 int pdeindex = ptepindex & (NPDEPG - 1);
1142 pdep = &pmap->pm_segtab[segindex];
1143 if (*pdep == NULL) {
1144 /* recurse for allocating page dir */
1145 if (_pmap_allocpte(pmap, NUPDE + segindex,
1147 /* alloc failed, release current */
1149 atomic_subtract_int(&cnt.v_wire_count, 1);
1150 vm_page_free_zero(m);
1154 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep));
1157 /* Next level entry */
1158 pde = (pd_entry_t *)*pdep;
1159 pde[pdeindex] = (pd_entry_t)pageva;
1162 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva;
1164 pmap->pm_stats.resident_count++;
1169 pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags)
1175 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT ||
1176 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK,
1177 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK"));
1180 * Calculate pagetable page index
1182 ptepindex = pmap_pde_pindex(va);
1185 * Get the page directory entry
1187 pde = pmap_pde(pmap, va);
1190 * If the page table page is mapped, we just increment the hold
1191 * count, and activate it.
1193 if (pde != NULL && *pde != NULL) {
1194 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde));
1198 * Here if the pte page isn't mapped, or if it has been
1201 m = _pmap_allocpte(pmap, ptepindex, flags);
1202 if (m == NULL && (flags & M_WAITOK))
1209 /***************************************************
1210 * Pmap allocation/deallocation routines.
1211 ***************************************************/
1214 * Release any resources held by the given physical map.
1215 * Called when a pmap initialized by pmap_pinit is being released.
1216 * Should only be called if the map contains no valid mappings.
1219 pmap_release(pmap_t pmap)
1224 KASSERT(pmap->pm_stats.resident_count == 0,
1225 ("pmap_release: pmap resident count %ld != 0",
1226 pmap->pm_stats.resident_count));
1228 ptdva = (vm_offset_t)pmap->pm_segtab;
1229 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva));
1231 ptdpg->wire_count--;
1232 atomic_subtract_int(&cnt.v_wire_count, 1);
1233 vm_page_free_zero(ptdpg);
1234 PMAP_LOCK_DESTROY(pmap);
1238 * grow the number of kernel page table entries, if needed
1241 pmap_growkernel(vm_offset_t addr)
1244 pd_entry_t *pde, *pdpe;
1248 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1249 addr = roundup2(addr, NBSEG);
1250 if (addr - 1 >= kernel_map->max_offset)
1251 addr = kernel_map->max_offset;
1252 while (kernel_vm_end < addr) {
1253 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end);
1256 /* new intermediate page table entry */
1257 nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT);
1259 panic("pmap_growkernel: no memory to grow kernel");
1260 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1261 continue; /* try again */
1264 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
1266 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1267 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1268 kernel_vm_end = kernel_map->max_offset;
1275 * This index is bogus, but out of the way
1277 nkpg = pmap_alloc_direct_page(nkpt, VM_ALLOC_INTERRUPT);
1279 panic("pmap_growkernel: no memory to grow kernel");
1281 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1284 * The R[4-7]?00 stores only one copy of the Global bit in
1285 * the translation lookaside buffer for each 2 page entry.
1286 * Thus invalid entrys must have the Global bit set so when
1287 * Entry LO and Entry HI G bits are anded together they will
1288 * produce a global bit to store in the tlb.
1290 pte = (pt_entry_t *)*pde;
1291 for (i = 0; i < NPTEPG; i++)
1294 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1295 if (kernel_vm_end - 1 >= kernel_map->max_offset) {
1296 kernel_vm_end = kernel_map->max_offset;
1302 /***************************************************
1303 * page management routines.
1304 ***************************************************/
1306 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1308 CTASSERT(_NPCM == 3);
1309 CTASSERT(_NPCPV == 168);
1311 CTASSERT(_NPCM == 11);
1312 CTASSERT(_NPCPV == 336);
1315 static __inline struct pv_chunk *
1316 pv_to_chunk(pv_entry_t pv)
1319 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1322 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1325 #define PC_FREE0_1 0xfffffffffffffffful
1326 #define PC_FREE2 0x000000fffffffffful
1328 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
1329 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
1332 static const u_long pc_freemask[_NPCM] = {
1334 PC_FREE0_1, PC_FREE0_1, PC_FREE2
1336 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1337 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1338 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1339 PC_FREE0_9, PC_FREE10
1343 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1345 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1346 "Current number of pv entries");
1349 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1351 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1352 "Current number of pv entry chunks");
1353 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1354 "Current number of pv entry chunks allocated");
1355 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1356 "Current number of pv entry chunks frees");
1357 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1358 "Number of times tried to get a chunk page but failed.");
1360 static long pv_entry_frees, pv_entry_allocs;
1361 static int pv_entry_spare;
1363 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1364 "Current number of pv entry frees");
1365 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1366 "Current number of pv entry allocs");
1367 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1368 "Current number of spare pv entries");
1372 * We are in a serious low memory condition. Resort to
1373 * drastic measures to free some pages so we can allocate
1374 * another pv entry chunk.
1377 pmap_pv_reclaim(pmap_t locked_pmap)
1380 struct pv_chunk *pc;
1383 pt_entry_t *pte, oldpte;
1388 int bit, field, freed, idx;
1390 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1393 TAILQ_INIT(&newtail);
1394 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) {
1395 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1396 if (pmap != pc->pc_pmap) {
1398 pmap_invalidate_all(pmap);
1399 if (pmap != locked_pmap)
1403 /* Avoid deadlock and lock recursion. */
1404 if (pmap > locked_pmap)
1406 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
1408 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1414 * Destroy every non-wired, 4 KB page mapping in the chunk.
1417 for (field = 0; field < _NPCM; field++) {
1418 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1419 inuse != 0; inuse &= ~(1UL << bit)) {
1420 bit = ffsl(inuse) - 1;
1421 idx = field * sizeof(inuse) * NBBY + bit;
1422 pv = &pc->pc_pventry[idx];
1424 pde = pmap_pde(pmap, va);
1425 KASSERT(pde != NULL && *pde != 0,
1426 ("pmap_pv_reclaim: pde"));
1427 pte = pmap_pde_to_pte(pde, va);
1429 if (pte_test(&oldpte, PTE_W))
1431 if (is_kernel_pmap(pmap))
1435 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte));
1436 if (pte_test(&oldpte, PTE_D))
1438 if (m->md.pv_flags & PV_TABLE_REF)
1439 vm_page_aflag_set(m, PGA_REFERENCED);
1440 m->md.pv_flags &= ~PV_TABLE_REF;
1441 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1442 if (TAILQ_EMPTY(&m->md.pv_list))
1443 vm_page_aflag_clear(m, PGA_WRITEABLE);
1444 pc->pc_map[field] |= 1UL << bit;
1445 pmap_unuse_pt(pmap, va, *pde);
1450 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1453 /* Every freed mapping is for a 4 KB page. */
1454 pmap->pm_stats.resident_count -= freed;
1455 PV_STAT(pv_entry_frees += freed);
1456 PV_STAT(pv_entry_spare += freed);
1457 pv_entry_count -= freed;
1458 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1459 for (field = 0; field < _NPCM; field++)
1460 if (pc->pc_map[field] != pc_freemask[field]) {
1461 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1463 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1466 * One freed pv entry in locked_pmap is
1469 if (pmap == locked_pmap)
1473 if (field == _NPCM) {
1474 PV_STAT(pv_entry_spare -= _NPCPV);
1475 PV_STAT(pc_chunk_count--);
1476 PV_STAT(pc_chunk_frees++);
1477 /* Entire chunk is free; return it. */
1478 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(
1484 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
1486 pmap_invalidate_all(pmap);
1487 if (pmap != locked_pmap)
1494 * free the pv_entry back to the free list
1497 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1499 struct pv_chunk *pc;
1500 int bit, field, idx;
1502 rw_assert(&pvh_global_lock, RA_WLOCKED);
1503 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1504 PV_STAT(pv_entry_frees++);
1505 PV_STAT(pv_entry_spare++);
1507 pc = pv_to_chunk(pv);
1508 idx = pv - &pc->pc_pventry[0];
1509 field = idx / (sizeof(u_long) * NBBY);
1510 bit = idx % (sizeof(u_long) * NBBY);
1511 pc->pc_map[field] |= 1ul << bit;
1512 for (idx = 0; idx < _NPCM; idx++)
1513 if (pc->pc_map[idx] != pc_freemask[idx]) {
1515 * 98% of the time, pc is already at the head of the
1516 * list. If it isn't already, move it to the head.
1518 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
1520 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1521 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1526 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1531 free_pv_chunk(struct pv_chunk *pc)
1535 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1536 PV_STAT(pv_entry_spare -= _NPCPV);
1537 PV_STAT(pc_chunk_count--);
1538 PV_STAT(pc_chunk_frees++);
1539 /* entire chunk is free, return it */
1540 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc));
1541 vm_page_unwire(m, 0);
1546 * get a new pv_entry, allocating a block from the system
1550 get_pv_entry(pmap_t pmap, boolean_t try)
1552 struct pv_chunk *pc;
1555 int bit, field, idx;
1557 rw_assert(&pvh_global_lock, RA_WLOCKED);
1558 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1559 PV_STAT(pv_entry_allocs++);
1562 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1564 for (field = 0; field < _NPCM; field++) {
1565 if (pc->pc_map[field]) {
1566 bit = ffsl(pc->pc_map[field]) - 1;
1570 if (field < _NPCM) {
1571 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
1572 pv = &pc->pc_pventry[idx];
1573 pc->pc_map[field] &= ~(1ul << bit);
1574 /* If this was the last item, move it to tail */
1575 for (field = 0; field < _NPCM; field++)
1576 if (pc->pc_map[field] != 0) {
1577 PV_STAT(pv_entry_spare--);
1578 return (pv); /* not full, return */
1580 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1581 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
1582 PV_STAT(pv_entry_spare--);
1586 /* No free items, allocate another chunk */
1587 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL |
1592 PV_STAT(pc_chunk_tryfail++);
1595 m = pmap_pv_reclaim(pmap);
1599 PV_STAT(pc_chunk_count++);
1600 PV_STAT(pc_chunk_allocs++);
1601 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1603 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
1604 for (field = 1; field < _NPCM; field++)
1605 pc->pc_map[field] = pc_freemask[field];
1606 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1607 pv = &pc->pc_pventry[0];
1608 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1609 PV_STAT(pv_entry_spare += _NPCPV - 1);
1614 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1618 rw_assert(&pvh_global_lock, RA_WLOCKED);
1619 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
1620 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1621 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
1629 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1633 pv = pmap_pvh_remove(pvh, pmap, va);
1634 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx",
1635 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)),
1637 free_pv_entry(pmap, pv);
1641 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
1644 rw_assert(&pvh_global_lock, RA_WLOCKED);
1645 pmap_pvh_free(&m->md, pmap, va);
1646 if (TAILQ_EMPTY(&m->md.pv_list))
1647 vm_page_aflag_clear(m, PGA_WRITEABLE);
1651 * Conditionally create a pv entry.
1654 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va,
1659 rw_assert(&pvh_global_lock, RA_WLOCKED);
1660 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1661 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
1663 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
1670 * pmap_remove_pte: do the things to unmap a page in a process
1673 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
1680 rw_assert(&pvh_global_lock, RA_WLOCKED);
1681 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1684 * Write back all cache lines from the page being unmapped.
1686 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
1689 if (is_kernel_pmap(pmap))
1694 if (pte_test(&oldpte, PTE_W))
1695 pmap->pm_stats.wired_count -= 1;
1697 pmap->pm_stats.resident_count -= 1;
1699 if (pte_test(&oldpte, PTE_MANAGED)) {
1700 pa = TLBLO_PTE_TO_PA(oldpte);
1701 m = PHYS_TO_VM_PAGE(pa);
1702 if (pte_test(&oldpte, PTE_D)) {
1703 KASSERT(!pte_test(&oldpte, PTE_RO),
1704 ("%s: modified page not writable: va: %p, pte: %#jx",
1705 __func__, (void *)va, (uintmax_t)oldpte));
1708 if (m->md.pv_flags & PV_TABLE_REF)
1709 vm_page_aflag_set(m, PGA_REFERENCED);
1710 m->md.pv_flags &= ~PV_TABLE_REF;
1712 pmap_remove_entry(pmap, m, va);
1714 return (pmap_unuse_pt(pmap, va, pde));
1718 * Remove a single page from a process address space
1721 pmap_remove_page(struct pmap *pmap, vm_offset_t va)
1726 rw_assert(&pvh_global_lock, RA_WLOCKED);
1727 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1728 pde = pmap_pde(pmap, va);
1729 if (pde == NULL || *pde == 0)
1731 ptq = pmap_pde_to_pte(pde, va);
1734 * If there is no pte for this address, just skip it!
1736 if (!pte_test(ptq, PTE_V))
1739 (void)pmap_remove_pte(pmap, ptq, va, *pde);
1740 pmap_invalidate_page(pmap, va);
1744 * Remove the given range of addresses from the specified map.
1746 * It is assumed that the start and end are properly
1747 * rounded to the page size.
1750 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1752 pd_entry_t *pde, *pdpe;
1754 vm_offset_t va, va_next;
1757 * Perform an unsynchronized read. This is, however, safe.
1759 if (pmap->pm_stats.resident_count == 0)
1762 rw_wlock(&pvh_global_lock);
1766 * special handling of removing one page. a very common operation
1767 * and easy to short circuit some code.
1769 if ((sva + PAGE_SIZE) == eva) {
1770 pmap_remove_page(pmap, sva);
1773 for (; sva < eva; sva = va_next) {
1774 pdpe = pmap_segmap(pmap, sva);
1777 va_next = (sva + NBSEG) & ~SEGMASK;
1783 va_next = (sva + NBPDR) & ~PDRMASK;
1787 pde = pmap_pdpe_to_pde(pdpe, sva);
1792 * Limit our scan to either the end of the va represented
1793 * by the current page table page, or to the end of the
1794 * range being removed.
1800 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1802 if (!pte_test(pte, PTE_V)) {
1803 if (va != va_next) {
1804 pmap_invalidate_range(pmap, va, sva);
1811 if (pmap_remove_pte(pmap, pte, sva, *pde)) {
1817 pmap_invalidate_range(pmap, va, sva);
1820 rw_wunlock(&pvh_global_lock);
1825 * Routine: pmap_remove_all
1827 * Removes this physical page from
1828 * all physical maps in which it resides.
1829 * Reflects back modify bits to the pager.
1832 * Original versions of this routine were very
1833 * inefficient because they iteratively called
1834 * pmap_remove (slow...)
1838 pmap_remove_all(vm_page_t m)
1843 pt_entry_t *pte, tpte;
1845 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1846 ("pmap_remove_all: page %p is not managed", m));
1847 rw_wlock(&pvh_global_lock);
1849 if (m->md.pv_flags & PV_TABLE_REF)
1850 vm_page_aflag_set(m, PGA_REFERENCED);
1852 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
1857 * If it's last mapping writeback all caches from
1858 * the page being destroyed
1860 if (TAILQ_NEXT(pv, pv_list) == NULL)
1861 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
1863 pmap->pm_stats.resident_count--;
1865 pde = pmap_pde(pmap, pv->pv_va);
1866 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde"));
1867 pte = pmap_pde_to_pte(pde, pv->pv_va);
1870 if (is_kernel_pmap(pmap))
1875 if (pte_test(&tpte, PTE_W))
1876 pmap->pm_stats.wired_count--;
1879 * Update the vm_page_t clean and reference bits.
1881 if (pte_test(&tpte, PTE_D)) {
1882 KASSERT(!pte_test(&tpte, PTE_RO),
1883 ("%s: modified page not writable: va: %p, pte: %#jx",
1884 __func__, (void *)pv->pv_va, (uintmax_t)tpte));
1887 pmap_invalidate_page(pmap, pv->pv_va);
1889 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1890 pmap_unuse_pt(pmap, pv->pv_va, *pde);
1891 free_pv_entry(pmap, pv);
1895 vm_page_aflag_clear(m, PGA_WRITEABLE);
1896 m->md.pv_flags &= ~PV_TABLE_REF;
1897 rw_wunlock(&pvh_global_lock);
1901 * Set the physical protection on the
1902 * specified range of this map as requested.
1905 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1907 pt_entry_t pbits, *pte;
1908 pd_entry_t *pde, *pdpe;
1909 vm_offset_t va, va_next;
1913 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1914 pmap_remove(pmap, sva, eva);
1917 if (prot & VM_PROT_WRITE)
1920 rw_wlock(&pvh_global_lock);
1922 for (; sva < eva; sva = va_next) {
1923 pdpe = pmap_segmap(pmap, sva);
1926 va_next = (sva + NBSEG) & ~SEGMASK;
1932 va_next = (sva + NBPDR) & ~PDRMASK;
1936 pde = pmap_pdpe_to_pde(pdpe, sva);
1941 * Limit our scan to either the end of the va represented
1942 * by the current page table page, or to the end of the
1943 * range being write protected.
1949 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1952 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits,
1954 if (va != va_next) {
1955 pmap_invalidate_range(pmap, va, sva);
1960 pte_set(&pbits, PTE_RO);
1961 if (pte_test(&pbits, PTE_D)) {
1962 pte_clear(&pbits, PTE_D);
1963 if (pte_test(&pbits, PTE_MANAGED)) {
1964 pa = TLBLO_PTE_TO_PA(pbits);
1965 m = PHYS_TO_VM_PAGE(pa);
1972 * Unless PTE_D is set, any TLB entries
1973 * mapping "sva" don't allow write access, so
1974 * they needn't be invalidated.
1976 if (va != va_next) {
1977 pmap_invalidate_range(pmap, va, sva);
1984 pmap_invalidate_range(pmap, va, sva);
1986 rw_wunlock(&pvh_global_lock);
1991 * Insert the given physical page (p) at
1992 * the specified virtual address (v) in the
1993 * target physical map with the protection requested.
1995 * If specified, the page will be wired down, meaning
1996 * that the related pte can not be reclaimed.
1998 * NB: This is the only routine which MAY NOT lazy-evaluate
1999 * or lose information. That is, this routine must actually
2000 * insert this page into the given map NOW.
2003 pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m,
2004 vm_prot_t prot, boolean_t wired)
2008 pt_entry_t origpte, newpte;
2013 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2014 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
2015 va >= kmi.clean_eva,
2016 ("pmap_enter: managed mapping within the clean submap"));
2017 KASSERT((m->oflags & (VPO_UNMANAGED | VPO_BUSY)) != 0,
2018 ("pmap_enter: page %p is not busy", m));
2019 pa = VM_PAGE_TO_PHYS(m);
2020 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, access, prot);
2023 if (is_kernel_pmap(pmap))
2025 if (is_cacheable_mem(pa))
2026 newpte |= PTE_C_CACHE;
2028 newpte |= PTE_C_UNCACHED;
2032 rw_wlock(&pvh_global_lock);
2036 * In the case that a page table page is not resident, we are
2039 if (va < VM_MAXUSER_ADDRESS) {
2040 mpte = pmap_allocpte(pmap, va, M_WAITOK);
2042 pte = pmap_pte(pmap, va);
2045 * Page Directory table entry not valid, we need a new PT page
2048 panic("pmap_enter: invalid page directory, pdir=%p, va=%p",
2049 (void *)pmap->pm_segtab, (void *)va);
2053 opa = TLBLO_PTE_TO_PA(origpte);
2056 * Mapping has not changed, must be protection or wiring change.
2058 if (pte_test(&origpte, PTE_V) && opa == pa) {
2060 * Wiring change, just update stats. We don't worry about
2061 * wiring PT pages as they remain resident as long as there
2062 * are valid mappings in them. Hence, if a user page is
2063 * wired, the PT page will be also.
2065 if (wired && !pte_test(&origpte, PTE_W))
2066 pmap->pm_stats.wired_count++;
2067 else if (!wired && pte_test(&origpte, PTE_W))
2068 pmap->pm_stats.wired_count--;
2070 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO),
2071 ("%s: modified page not writable: va: %p, pte: %#jx",
2072 __func__, (void *)va, (uintmax_t)origpte));
2075 * Remove extra pte reference
2080 if (pte_test(&origpte, PTE_MANAGED)) {
2081 m->md.pv_flags |= PV_TABLE_REF;
2083 newpte |= PTE_MANAGED;
2084 if (!pte_test(&newpte, PTE_RO))
2085 vm_page_aflag_set(m, PGA_WRITEABLE);
2093 * Mapping has changed, invalidate old range and fall through to
2094 * handle validating new mapping.
2097 if (pte_test(&origpte, PTE_W))
2098 pmap->pm_stats.wired_count--;
2100 if (pte_test(&origpte, PTE_MANAGED)) {
2101 om = PHYS_TO_VM_PAGE(opa);
2102 pv = pmap_pvh_remove(&om->md, pmap, va);
2106 KASSERT(mpte->wire_count > 0,
2107 ("pmap_enter: missing reference to page table page,"
2108 " va: %p", (void *)va));
2111 pmap->pm_stats.resident_count++;
2114 * Enter on the PV list if part of our managed memory.
2116 if ((m->oflags & VPO_UNMANAGED) == 0) {
2117 m->md.pv_flags |= PV_TABLE_REF;
2119 pv = get_pv_entry(pmap, FALSE);
2121 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2122 newpte |= PTE_MANAGED;
2123 if (!pte_test(&newpte, PTE_RO))
2124 vm_page_aflag_set(m, PGA_WRITEABLE);
2125 } else if (pv != NULL)
2126 free_pv_entry(pmap, pv);
2129 * Increment counters
2132 pmap->pm_stats.wired_count++;
2137 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
2141 * if the mapping or permission bits are different, we need to
2144 if (origpte != newpte) {
2146 if (pte_test(&origpte, PTE_V)) {
2147 if (pte_test(&origpte, PTE_MANAGED) && opa != pa) {
2148 if (om->md.pv_flags & PV_TABLE_REF)
2149 vm_page_aflag_set(om, PGA_REFERENCED);
2150 om->md.pv_flags &= ~PV_TABLE_REF;
2152 if (pte_test(&origpte, PTE_D)) {
2153 KASSERT(!pte_test(&origpte, PTE_RO),
2154 ("pmap_enter: modified page not writable:"
2155 " va: %p, pte: %#jx", (void *)va, (uintmax_t)origpte));
2156 if (pte_test(&origpte, PTE_MANAGED))
2159 if (pte_test(&origpte, PTE_MANAGED) &&
2160 TAILQ_EMPTY(&om->md.pv_list))
2161 vm_page_aflag_clear(om, PGA_WRITEABLE);
2162 pmap_update_page(pmap, va, newpte);
2167 * Sync I & D caches for executable pages. Do this only if the
2168 * target pmap belongs to the current process. Otherwise, an
2169 * unresolvable TLB miss may occur.
2171 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
2172 (prot & VM_PROT_EXECUTE)) {
2173 mips_icache_sync_range(va, PAGE_SIZE);
2174 mips_dcache_wbinv_range(va, PAGE_SIZE);
2176 rw_wunlock(&pvh_global_lock);
2181 * this code makes some *MAJOR* assumptions:
2182 * 1. Current pmap & pmap exists.
2185 * 4. No page table pages.
2186 * but is *MUCH* faster than pmap_enter...
2190 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2193 rw_wlock(&pvh_global_lock);
2195 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
2196 rw_wunlock(&pvh_global_lock);
2201 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2202 vm_prot_t prot, vm_page_t mpte)
2207 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2208 (m->oflags & VPO_UNMANAGED) != 0,
2209 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2210 rw_assert(&pvh_global_lock, RA_WLOCKED);
2211 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2214 * In the case that a page table page is not resident, we are
2217 if (va < VM_MAXUSER_ADDRESS) {
2222 * Calculate pagetable page index
2224 ptepindex = pmap_pde_pindex(va);
2225 if (mpte && (mpte->pindex == ptepindex)) {
2229 * Get the page directory entry
2231 pde = pmap_pde(pmap, va);
2234 * If the page table page is mapped, we just
2235 * increment the hold count, and activate it.
2237 if (pde && *pde != 0) {
2238 mpte = PHYS_TO_VM_PAGE(
2239 MIPS_DIRECT_TO_PHYS(*pde));
2242 mpte = _pmap_allocpte(pmap, ptepindex,
2252 pte = pmap_pte(pmap, va);
2253 if (pte_test(pte, PTE_V)) {
2262 * Enter on the PV list if part of our managed memory.
2264 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2265 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) {
2267 pmap_unwire_ptp(pmap, va, mpte);
2274 * Increment counters
2276 pmap->pm_stats.resident_count++;
2278 pa = VM_PAGE_TO_PHYS(m);
2281 * Now validate mapping with RO protection
2283 *pte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V;
2284 if ((m->oflags & VPO_UNMANAGED) == 0)
2285 *pte |= PTE_MANAGED;
2287 if (is_cacheable_mem(pa))
2288 *pte |= PTE_C_CACHE;
2290 *pte |= PTE_C_UNCACHED;
2292 if (is_kernel_pmap(pmap))
2296 * Sync I & D caches. Do this only if the target pmap
2297 * belongs to the current process. Otherwise, an
2298 * unresolvable TLB miss may occur. */
2299 if (pmap == &curproc->p_vmspace->vm_pmap) {
2301 mips_icache_sync_range(va, PAGE_SIZE);
2302 mips_dcache_wbinv_range(va, PAGE_SIZE);
2309 * Make a temporary mapping for a physical address. This is only intended
2310 * to be used for panic dumps.
2312 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2315 pmap_kenter_temporary(vm_paddr_t pa, int i)
2320 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
2323 if (MIPS_DIRECT_MAPPABLE(pa)) {
2324 va = MIPS_PHYS_TO_DIRECT(pa);
2326 #ifndef __mips_n64 /* XXX : to be converted to new style */
2329 struct local_sysmaps *sysm;
2330 pt_entry_t *pte, npte;
2332 /* If this is used other than for dumps, we may need to leave
2333 * interrupts disasbled on return. If crash dumps don't work when
2334 * we get to this point, we might want to consider this (leaving things
2335 * disabled as a starting point ;-)
2337 intr = intr_disable();
2338 cpu = PCPU_GET(cpuid);
2339 sysm = &sysmap_lmem[cpu];
2340 /* Since this is for the debugger, no locks or any other fun */
2341 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
2343 pte = pmap_pte(kernel_pmap, sysm->base);
2346 pmap_update_page(kernel_pmap, sysm->base, npte);
2351 return ((void *)va);
2355 pmap_kenter_temporary_free(vm_paddr_t pa)
2357 #ifndef __mips_n64 /* XXX : to be converted to new style */
2360 struct local_sysmaps *sysm;
2363 if (MIPS_DIRECT_MAPPABLE(pa)) {
2364 /* nothing to do for this case */
2367 #ifndef __mips_n64 /* XXX : to be converted to new style */
2368 cpu = PCPU_GET(cpuid);
2369 sysm = &sysmap_lmem[cpu];
2373 intr = intr_disable();
2374 pte = pmap_pte(kernel_pmap, sysm->base);
2376 pmap_invalidate_page(kernel_pmap, sysm->base);
2384 * Maps a sequence of resident pages belonging to the same object.
2385 * The sequence begins with the given page m_start. This page is
2386 * mapped at the given virtual address start. Each subsequent page is
2387 * mapped at a virtual address that is offset from start by the same
2388 * amount as the page is offset from m_start within the object. The
2389 * last page in the sequence is the page with the largest offset from
2390 * m_start that can be mapped at a virtual address less than the given
2391 * virtual address end. Not every virtual page between start and end
2392 * is mapped; only those for which a resident page exists with the
2393 * corresponding offset from m_start are mapped.
2396 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2397 vm_page_t m_start, vm_prot_t prot)
2400 vm_pindex_t diff, psize;
2402 VM_OBJECT_ASSERT_WLOCKED(m_start->object);
2403 psize = atop(end - start);
2406 rw_wlock(&pvh_global_lock);
2408 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2409 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m,
2411 m = TAILQ_NEXT(m, listq);
2413 rw_wunlock(&pvh_global_lock);
2418 * pmap_object_init_pt preloads the ptes for a given object
2419 * into the specified pmap. This eliminates the blast of soft
2420 * faults on process startup and immediately after an mmap.
2423 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
2424 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2426 VM_OBJECT_ASSERT_WLOCKED(object);
2427 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2428 ("pmap_object_init_pt: non-device object"));
2432 * Routine: pmap_change_wiring
2433 * Function: Change the wiring attribute for a map/virtual-address
2435 * In/out conditions:
2436 * The mapping must already exist in the pmap.
2439 pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired)
2444 pte = pmap_pte(pmap, va);
2446 if (wired && !pte_test(pte, PTE_W))
2447 pmap->pm_stats.wired_count++;
2448 else if (!wired && pte_test(pte, PTE_W))
2449 pmap->pm_stats.wired_count--;
2452 * Wiring is not a hardware characteristic so there is no need to
2456 pte_set(pte, PTE_W);
2458 pte_clear(pte, PTE_W);
2463 * Copy the range specified by src_addr/len
2464 * from the source map to the range dst_addr/len
2465 * in the destination map.
2467 * This routine is only advisory and need not do anything.
2471 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2472 vm_size_t len, vm_offset_t src_addr)
2477 * pmap_zero_page zeros the specified hardware page by mapping
2478 * the page into KVM and using bzero to clear its contents.
2480 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2483 pmap_zero_page(vm_page_t m)
2486 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2488 if (MIPS_DIRECT_MAPPABLE(phys)) {
2489 va = MIPS_PHYS_TO_DIRECT(phys);
2490 bzero((caddr_t)va, PAGE_SIZE);
2491 mips_dcache_wbinv_range(va, PAGE_SIZE);
2493 va = pmap_lmem_map1(phys);
2494 bzero((caddr_t)va, PAGE_SIZE);
2495 mips_dcache_wbinv_range(va, PAGE_SIZE);
2501 * pmap_zero_page_area zeros the specified hardware page by mapping
2502 * the page into KVM and using bzero to clear its contents.
2504 * off and size may not cover an area beyond a single hardware page.
2507 pmap_zero_page_area(vm_page_t m, int off, int size)
2510 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2512 if (MIPS_DIRECT_MAPPABLE(phys)) {
2513 va = MIPS_PHYS_TO_DIRECT(phys);
2514 bzero((char *)(caddr_t)va + off, size);
2515 mips_dcache_wbinv_range(va + off, size);
2517 va = pmap_lmem_map1(phys);
2518 bzero((char *)va + off, size);
2519 mips_dcache_wbinv_range(va + off, size);
2525 pmap_zero_page_idle(vm_page_t m)
2528 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2530 if (MIPS_DIRECT_MAPPABLE(phys)) {
2531 va = MIPS_PHYS_TO_DIRECT(phys);
2532 bzero((caddr_t)va, PAGE_SIZE);
2533 mips_dcache_wbinv_range(va, PAGE_SIZE);
2535 va = pmap_lmem_map1(phys);
2536 bzero((caddr_t)va, PAGE_SIZE);
2537 mips_dcache_wbinv_range(va, PAGE_SIZE);
2543 * pmap_copy_page copies the specified (machine independent)
2544 * page by mapping the page into virtual memory and using
2545 * bcopy to copy the page, one machine dependent page at a
2548 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2551 pmap_copy_page(vm_page_t src, vm_page_t dst)
2553 vm_offset_t va_src, va_dst;
2554 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src);
2555 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst);
2557 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) {
2558 /* easy case, all can be accessed via KSEG0 */
2560 * Flush all caches for VA that are mapped to this page
2561 * to make sure that data in SDRAM is up to date
2563 pmap_flush_pvcache(src);
2564 mips_dcache_wbinv_range_index(
2565 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE);
2566 va_src = MIPS_PHYS_TO_DIRECT(phys_src);
2567 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst);
2568 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
2569 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2571 va_src = pmap_lmem_map2(phys_src, phys_dst);
2572 va_dst = va_src + PAGE_SIZE;
2573 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE);
2574 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2579 int unmapped_buf_allowed;
2582 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2583 vm_offset_t b_offset, int xfersize)
2587 vm_offset_t a_pg_offset, b_pg_offset;
2588 vm_paddr_t a_phys, b_phys;
2591 while (xfersize > 0) {
2592 a_pg_offset = a_offset & PAGE_MASK;
2593 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2594 a_m = ma[a_offset >> PAGE_SHIFT];
2595 a_phys = VM_PAGE_TO_PHYS(a_m);
2596 b_pg_offset = b_offset & PAGE_MASK;
2597 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2598 b_m = mb[b_offset >> PAGE_SHIFT];
2599 b_phys = VM_PAGE_TO_PHYS(b_m);
2600 if (MIPS_DIRECT_MAPPABLE(a_phys) &&
2601 MIPS_DIRECT_MAPPABLE(b_phys)) {
2602 pmap_flush_pvcache(a_m);
2603 mips_dcache_wbinv_range_index(
2604 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE);
2605 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) +
2607 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) +
2609 bcopy(a_cp, b_cp, cnt);
2610 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2612 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys);
2613 b_cp = (char *)a_cp + PAGE_SIZE;
2614 a_cp += a_pg_offset;
2615 b_cp += b_pg_offset;
2616 bcopy(a_cp, b_cp, cnt);
2617 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2627 * Returns true if the pmap's pv is one of the first
2628 * 16 pvs linked to from this page. This count may
2629 * be changed upwards or downwards in the future; it
2630 * is only necessary that true be returned for a small
2631 * subset of pmaps for proper page aging.
2634 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2640 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2641 ("pmap_page_exists_quick: page %p is not managed", m));
2643 rw_wlock(&pvh_global_lock);
2644 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2645 if (PV_PMAP(pv) == pmap) {
2653 rw_wunlock(&pvh_global_lock);
2658 * Remove all pages from specified address space
2659 * this aids process exit speeds. Also, this code
2660 * is special cased for current process only, but
2661 * can have the more generic (and slightly slower)
2662 * mode enabled. This is much faster than pmap_remove
2663 * in the case of running down an entire address space.
2666 pmap_remove_pages(pmap_t pmap)
2669 pt_entry_t *pte, tpte;
2672 struct pv_chunk *pc, *npc;
2673 u_long inuse, bitmask;
2674 int allfree, bit, field, idx;
2676 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
2677 printf("warning: pmap_remove_pages called with non-current pmap\n");
2680 rw_wlock(&pvh_global_lock);
2682 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2684 for (field = 0; field < _NPCM; field++) {
2685 inuse = ~pc->pc_map[field] & pc_freemask[field];
2686 while (inuse != 0) {
2687 bit = ffsl(inuse) - 1;
2688 bitmask = 1UL << bit;
2689 idx = field * sizeof(inuse) * NBBY + bit;
2690 pv = &pc->pc_pventry[idx];
2693 pde = pmap_pde(pmap, pv->pv_va);
2694 KASSERT(pde != NULL && *pde != 0,
2695 ("pmap_remove_pages: pde"));
2696 pte = pmap_pde_to_pte(pde, pv->pv_va);
2697 if (!pte_test(pte, PTE_V))
2698 panic("pmap_remove_pages: bad pte");
2702 * We cannot remove wired pages from a process' mapping at this time
2704 if (pte_test(&tpte, PTE_W)) {
2708 *pte = is_kernel_pmap(pmap) ? PTE_G : 0;
2710 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte));
2712 ("pmap_remove_pages: bad tpte %#jx",
2716 * Update the vm_page_t clean and reference bits.
2718 if (pte_test(&tpte, PTE_D))
2722 PV_STAT(pv_entry_frees++);
2723 PV_STAT(pv_entry_spare++);
2725 pc->pc_map[field] |= bitmask;
2726 pmap->pm_stats.resident_count--;
2727 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2728 if (TAILQ_EMPTY(&m->md.pv_list))
2729 vm_page_aflag_clear(m, PGA_WRITEABLE);
2730 pmap_unuse_pt(pmap, pv->pv_va, *pde);
2734 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2738 pmap_invalidate_all(pmap);
2740 rw_wunlock(&pvh_global_lock);
2744 * pmap_testbit tests bits in pte's
2747 pmap_testbit(vm_page_t m, int bit)
2752 boolean_t rv = FALSE;
2754 if (m->oflags & VPO_UNMANAGED)
2757 rw_assert(&pvh_global_lock, RA_WLOCKED);
2758 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2761 pte = pmap_pte(pmap, pv->pv_va);
2762 rv = pte_test(pte, bit);
2771 * pmap_page_wired_mappings:
2773 * Return the number of managed mappings to the given physical page
2777 pmap_page_wired_mappings(vm_page_t m)
2785 if ((m->oflags & VPO_UNMANAGED) != 0)
2787 rw_wlock(&pvh_global_lock);
2788 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2791 pte = pmap_pte(pmap, pv->pv_va);
2792 if (pte_test(pte, PTE_W))
2796 rw_wunlock(&pvh_global_lock);
2801 * Clear the write and modified bits in each of the given page's mappings.
2804 pmap_remove_write(vm_page_t m)
2807 pt_entry_t pbits, *pte;
2810 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2811 ("pmap_remove_write: page %p is not managed", m));
2814 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be set by
2815 * another thread while the object is locked. Thus, if PGA_WRITEABLE
2816 * is clear, no page table entries need updating.
2818 VM_OBJECT_ASSERT_WLOCKED(m->object);
2819 if ((m->oflags & VPO_BUSY) == 0 &&
2820 (m->aflags & PGA_WRITEABLE) == 0)
2822 rw_wlock(&pvh_global_lock);
2823 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2826 pte = pmap_pte(pmap, pv->pv_va);
2827 KASSERT(pte != NULL && pte_test(pte, PTE_V),
2828 ("page on pv_list has no pte"));
2830 if (pte_test(&pbits, PTE_D)) {
2831 pte_clear(&pbits, PTE_D);
2834 pte_set(&pbits, PTE_RO);
2835 if (pbits != *pte) {
2837 pmap_update_page(pmap, pv->pv_va, pbits);
2841 vm_page_aflag_clear(m, PGA_WRITEABLE);
2842 rw_wunlock(&pvh_global_lock);
2846 * pmap_ts_referenced:
2848 * Return the count of reference bits for a page, clearing all of them.
2851 pmap_ts_referenced(vm_page_t m)
2854 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2855 ("pmap_ts_referenced: page %p is not managed", m));
2856 if (m->md.pv_flags & PV_TABLE_REF) {
2857 rw_wlock(&pvh_global_lock);
2858 m->md.pv_flags &= ~PV_TABLE_REF;
2859 rw_wunlock(&pvh_global_lock);
2868 * Return whether or not the specified physical page was modified
2869 * in any physical maps.
2872 pmap_is_modified(vm_page_t m)
2876 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2877 ("pmap_is_modified: page %p is not managed", m));
2880 * If the page is not VPO_BUSY, then PGA_WRITEABLE cannot be
2881 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
2882 * is clear, no PTEs can have PTE_D set.
2884 VM_OBJECT_ASSERT_WLOCKED(m->object);
2885 if ((m->oflags & VPO_BUSY) == 0 &&
2886 (m->aflags & PGA_WRITEABLE) == 0)
2888 rw_wlock(&pvh_global_lock);
2889 rv = pmap_testbit(m, PTE_D);
2890 rw_wunlock(&pvh_global_lock);
2897 * pmap_is_prefaultable:
2899 * Return whether or not the specified virtual address is elgible
2903 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2911 pde = pmap_pde(pmap, addr);
2912 if (pde != NULL && *pde != 0) {
2913 pte = pmap_pde_to_pte(pde, addr);
2921 * Clear the modify bits on the specified physical page.
2924 pmap_clear_modify(vm_page_t m)
2930 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2931 ("pmap_clear_modify: page %p is not managed", m));
2932 VM_OBJECT_ASSERT_WLOCKED(m->object);
2933 KASSERT((m->oflags & VPO_BUSY) == 0,
2934 ("pmap_clear_modify: page %p is busy", m));
2937 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_D set.
2938 * If the object containing the page is locked and the page is not
2939 * VPO_BUSY, then PGA_WRITEABLE cannot be concurrently set.
2941 if ((m->aflags & PGA_WRITEABLE) == 0)
2943 rw_wlock(&pvh_global_lock);
2944 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2947 pte = pmap_pte(pmap, pv->pv_va);
2948 if (pte_test(pte, PTE_D)) {
2949 pte_clear(pte, PTE_D);
2950 pmap_update_page(pmap, pv->pv_va, *pte);
2954 rw_wunlock(&pvh_global_lock);
2958 * pmap_is_referenced:
2960 * Return whether or not the specified physical page was referenced
2961 * in any physical maps.
2964 pmap_is_referenced(vm_page_t m)
2967 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2968 ("pmap_is_referenced: page %p is not managed", m));
2969 return ((m->md.pv_flags & PV_TABLE_REF) != 0);
2973 * pmap_clear_reference:
2975 * Clear the reference bit on the specified physical page.
2978 pmap_clear_reference(vm_page_t m)
2981 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2982 ("pmap_clear_reference: page %p is not managed", m));
2983 rw_wlock(&pvh_global_lock);
2984 if (m->md.pv_flags & PV_TABLE_REF) {
2985 m->md.pv_flags &= ~PV_TABLE_REF;
2987 rw_wunlock(&pvh_global_lock);
2991 * Miscellaneous support routines follow
2995 * Map a set of physical memory pages into the kernel virtual
2996 * address space. Return a pointer to where it is mapped. This
2997 * routine is intended to be used for mapping device memory,
3000 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit.
3003 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3005 vm_offset_t va, tmpva, offset;
3008 * KSEG1 maps only first 512M of phys address space. For
3009 * pa > 0x20000000 we should make proper mapping * using pmap_kenter.
3011 if (MIPS_DIRECT_MAPPABLE(pa + size - 1))
3012 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
3014 offset = pa & PAGE_MASK;
3015 size = roundup(size + offset, PAGE_SIZE);
3017 va = kmem_alloc_nofault(kernel_map, size);
3019 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3020 pa = trunc_page(pa);
3021 for (tmpva = va; size > 0;) {
3022 pmap_kenter_attr(tmpva, pa, PTE_C_UNCACHED);
3029 return ((void *)(va + offset));
3033 pmap_unmapdev(vm_offset_t va, vm_size_t size)
3036 vm_offset_t base, offset;
3038 /* If the address is within KSEG1 then there is nothing to do */
3039 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
3042 base = trunc_page(va);
3043 offset = va & PAGE_MASK;
3044 size = roundup(size + offset, PAGE_SIZE);
3045 kmem_free(kernel_map, base, size);
3050 * perform the pmap work for mincore
3053 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa)
3055 pt_entry_t *ptep, pte;
3062 ptep = pmap_pte(pmap, addr);
3063 pte = (ptep != NULL) ? *ptep : 0;
3064 if (!pte_test(&pte, PTE_V)) {
3068 val = MINCORE_INCORE;
3069 if (pte_test(&pte, PTE_D))
3070 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3071 pa = TLBLO_PTE_TO_PA(pte);
3072 if (pte_test(&pte, PTE_MANAGED)) {
3074 * This may falsely report the given address as
3075 * MINCORE_REFERENCED. Unfortunately, due to the lack of
3076 * per-PTE reference information, it is impossible to
3077 * determine if the address is MINCORE_REFERENCED.
3079 m = PHYS_TO_VM_PAGE(pa);
3080 if ((m->aflags & PGA_REFERENCED) != 0)
3081 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3083 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3084 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
3085 pte_test(&pte, PTE_MANAGED)) {
3086 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */
3087 if (vm_page_pa_tryrelock(pmap, pa, locked_pa))
3091 PA_UNLOCK_COND(*locked_pa);
3097 pmap_activate(struct thread *td)
3099 pmap_t pmap, oldpmap;
3100 struct proc *p = td->td_proc;
3105 pmap = vmspace_pmap(p->p_vmspace);
3106 oldpmap = PCPU_GET(curpmap);
3107 cpuid = PCPU_GET(cpuid);
3110 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
3111 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
3112 pmap_asid_alloc(pmap);
3113 if (td == curthread) {
3114 PCPU_SET(segbase, pmap->pm_segtab);
3115 mips_wr_entryhi(pmap->pm_asid[cpuid].asid);
3118 PCPU_SET(curpmap, pmap);
3123 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3128 * Increase the starting virtual address of the given mapping if a
3129 * different alignment might result in more superpage mappings.
3132 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3133 vm_offset_t *addr, vm_size_t size)
3135 vm_offset_t superpage_offset;
3139 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
3140 offset += ptoa(object->pg_color);
3141 superpage_offset = offset & SEGMASK;
3142 if (size - ((NBSEG - superpage_offset) & SEGMASK) < NBSEG ||
3143 (*addr & SEGMASK) == superpage_offset)
3145 if ((*addr & SEGMASK) < superpage_offset)
3146 *addr = (*addr & ~SEGMASK) + superpage_offset;
3148 *addr = ((*addr + SEGMASK) & ~SEGMASK) + superpage_offset;
3152 * Increase the starting virtual address of the given mapping so
3153 * that it is aligned to not be the second page in a TLB entry.
3154 * This routine assumes that the length is appropriately-sized so
3155 * that the allocation does not share a TLB entry at all if required.
3158 pmap_align_tlb(vm_offset_t *addr)
3160 if ((*addr & PAGE_SIZE) == 0)
3167 DB_SHOW_COMMAND(ptable, ddb_pid_dump)
3170 struct thread *td = NULL;
3177 td = db_lookup_thread(addr, TRUE);
3179 db_printf("Invalid pid or tid");
3183 if (p->p_vmspace == NULL) {
3184 db_printf("No vmspace for process");
3187 pmap = vmspace_pmap(p->p_vmspace);
3191 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n",
3192 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid,
3193 pmap->pm_asid[0].gen);
3194 for (i = 0; i < NPDEPG; i++) {
3199 pdpe = (pd_entry_t *)pmap->pm_segtab[i];
3202 db_printf("[%4d] %p\n", i, pdpe);
3204 for (j = 0; j < NPDEPG; j++) {
3205 pde = (pt_entry_t *)pdpe[j];
3208 db_printf("\t[%4d] %p\n", j, pde);
3212 pde = (pt_entry_t *)pdpe;
3214 for (k = 0; k < NPTEPG; k++) {
3216 if (pte == 0 || !pte_test(&pte, PTE_V))
3218 pa = TLBLO_PTE_TO_PA(pte);
3219 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT);
3220 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n",
3221 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa);
3230 static void pads(pmap_t pm);
3231 void pmap_pvdump(vm_offset_t pa);
3233 /* print address space of pmap*/
3240 if (pm == kernel_pmap)
3242 for (i = 0; i < NPTEPG; i++)
3243 if (pm->pm_segtab[i])
3244 for (j = 0; j < NPTEPG; j++) {
3245 va = (i << SEGSHIFT) + (j << PAGE_SHIFT);
3246 if (pm == kernel_pmap && va < KERNBASE)
3248 if (pm != kernel_pmap &&
3249 va >= VM_MAXUSER_ADDRESS)
3251 ptep = pmap_pte(pm, va);
3252 if (pte_test(ptep, PTE_V))
3253 printf("%x:%x ", va, *(int *)ptep);
3259 pmap_pvdump(vm_offset_t pa)
3261 register pv_entry_t pv;
3264 printf("pa %x", pa);
3265 m = PHYS_TO_VM_PAGE(pa);
3266 for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
3267 pv = TAILQ_NEXT(pv, pv_list)) {
3268 printf(" -> pmap %p, va %x", (void *)pv->pv_pmap, pv->pv_va);
3279 * Allocate TLB address space tag (called ASID or TLBPID) and return it.
3280 * It takes almost as much or more time to search the TLB for a
3281 * specific ASID and flush those entries as it does to flush the entire TLB.
3282 * Therefore, when we allocate a new ASID, we just take the next number. When
3283 * we run out of numbers, we flush the TLB, increment the generation count
3284 * and start over. ASID zero is reserved for kernel use.
3287 pmap_asid_alloc(pmap)
3290 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED &&
3291 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
3293 if (PCPU_GET(next_asid) == pmap_max_asid) {
3294 tlb_invalidate_all_user(NULL);
3295 PCPU_SET(asid_generation,
3296 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
3297 if (PCPU_GET(asid_generation) == 0) {
3298 PCPU_SET(asid_generation, 1);
3300 PCPU_SET(next_asid, 1); /* 0 means invalid */
3302 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid);
3303 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation);
3304 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1);
3309 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot)
3313 if (!(prot & VM_PROT_WRITE))
3314 rw = PTE_V | PTE_RO;
3315 else if ((m->oflags & VPO_UNMANAGED) == 0) {
3316 if ((access & VM_PROT_WRITE) != 0)
3321 /* Needn't emulate a modified bit for unmanaged pages. */
3327 * pmap_emulate_modified : do dirty bit emulation
3329 * On SMP, update just the local TLB, other CPUs will update their
3330 * TLBs from PTE lazily, if they get the exception.
3331 * Returns 0 in case of sucess, 1 if the page is read only and we
3335 pmap_emulate_modified(pmap_t pmap, vm_offset_t va)
3340 pte = pmap_pte(pmap, va);
3342 panic("pmap_emulate_modified: can't find PTE");
3344 /* It is possible that some other CPU changed m-bit */
3345 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) {
3346 tlb_update(pmap, va, *pte);
3351 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D))
3352 panic("pmap_emulate_modified: invalid pte");
3354 if (pte_test(pte, PTE_RO)) {
3358 pte_set(pte, PTE_D);
3359 tlb_update(pmap, va, *pte);
3360 if (!pte_test(pte, PTE_MANAGED))
3361 panic("pmap_emulate_modified: unmanaged page");
3367 * Routine: pmap_kextract
3369 * Extract the physical page address associated
3373 pmap_kextract(vm_offset_t va)
3378 * First, the direct-mapped regions.
3380 #if defined(__mips_n64)
3381 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
3382 return (MIPS_XKPHYS_TO_PHYS(va));
3384 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
3385 return (MIPS_KSEG0_TO_PHYS(va));
3387 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
3388 return (MIPS_KSEG1_TO_PHYS(va));
3391 * User virtual addresses.
3393 if (va < VM_MAXUSER_ADDRESS) {
3396 if (curproc && curproc->p_vmspace) {
3397 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
3399 return (TLBLO_PTE_TO_PA(*ptep) |
3407 * Should be kernel virtual here, otherwise fail
3409 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
3410 #if defined(__mips_n64)
3411 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
3420 /* Is the kernel pmap initialized? */
3421 if (!CPU_EMPTY(&kernel_pmap->pm_active)) {
3422 /* It's inside the virtual address range */
3423 ptep = pmap_pte(kernel_pmap, va);
3425 return (TLBLO_PTE_TO_PA(*ptep) |
3432 panic("%s for unknown address space %p.", __func__, (void *)va);
3437 pmap_flush_pvcache(vm_page_t m)
3442 for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
3443 pv = TAILQ_NEXT(pv, pv_list)) {
3444 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);