2 * SPDX-License-Identifier: BSD-3-Clause
4 * Copyright (c) 1991 Regents of the University of California.
6 * Copyright (c) 1994 John S. Dyson
8 * Copyright (c) 1994 David Greenman
11 * This code is derived from software contributed to Berkeley by
12 * the Systems Programming Group of the University of Utah Computer
13 * Science Department and William Jolitz of UUNET Technologies Inc.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. Neither the name of the University nor the names of its contributors
24 * may be used to endorse or promote products derived from this software
25 * without specific prior written permission.
27 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
28 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
30 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
31 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
35 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
36 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91
40 * from: src/sys/i386/i386/pmap.c,v 1.250.2.8 2000/11/21 00:09:14 ps
41 * JNPR: pmap.c,v 1.11.2.1 2007/08/16 11:51:06 girish
45 * Manages physical address maps.
47 * Since the information managed by this module is
48 * also stored by the logical address mapping module,
49 * this module may throw away valid virtual-to-physical
50 * mappings at almost any time. However, invalidations
51 * of virtual-to-physical mappings must be done as
54 * In order to cope with hardware architectures which
55 * make virtual-to-physical map invalidates expensive,
56 * this module may delay invalidate or reduced protection
57 * operations until such time as they are actually
58 * necessary. This module is given full information as
59 * to which processors are currently using which maps,
60 * and to when physical maps must be made correct.
63 #include <sys/cdefs.h>
64 __FBSDID("$FreeBSD$");
69 #include <sys/param.h>
70 #include <sys/systm.h>
71 #include <sys/kernel.h>
74 #include <sys/msgbuf.h>
75 #include <sys/mutex.h>
78 #include <sys/rwlock.h>
79 #include <sys/sched.h>
81 #include <sys/sysctl.h>
82 #include <sys/vmmeter.h>
89 #include <vm/vm_param.h>
90 #include <vm/vm_kern.h>
91 #include <vm/vm_page.h>
92 #include <vm/vm_phys.h>
93 #include <vm/vm_map.h>
94 #include <vm/vm_object.h>
95 #include <vm/vm_extern.h>
96 #include <vm/vm_pageout.h>
97 #include <vm/vm_pager.h>
100 #include <machine/cache.h>
101 #include <machine/md_var.h>
102 #include <machine/tlb.h>
106 #if !defined(DIAGNOSTIC)
107 #define PMAP_INLINE __inline
113 #define PV_STAT(x) do { x ; } while (0)
115 #define PV_STAT(x) do { } while (0)
119 * Get PDEs and PTEs for user/kernel address space
121 #define pmap_seg_index(v) (((v) >> SEGSHIFT) & (NPDEPG - 1))
122 #define pmap_pde_index(v) (((v) >> PDRSHIFT) & (NPDEPG - 1))
123 #define pmap_pte_index(v) (((v) >> PAGE_SHIFT) & (NPTEPG - 1))
124 #define pmap_pde_pindex(v) ((v) >> PDRSHIFT)
127 #define NUPDE (NPDEPG * NPDEPG)
128 #define NUSERPGTBLS (NUPDE + NPDEPG)
130 #define NUPDE (NPDEPG)
131 #define NUSERPGTBLS (NUPDE)
134 #define is_kernel_pmap(x) ((x) == kernel_pmap)
136 struct pmap kernel_pmap_store;
137 pd_entry_t *kernel_segmap;
139 vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */
140 vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */
142 static int need_local_mappings;
145 unsigned pmap_max_asid; /* max ASID supported by the system */
147 #define PMAP_ASID_RESERVED 0
149 vm_offset_t kernel_vm_end = VM_MIN_KERNEL_ADDRESS;
151 static void pmap_asid_alloc(pmap_t pmap);
153 static struct rwlock_padalign pvh_global_lock;
156 * Data for the pv entry allocation mechanism
158 static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks);
159 static int pv_entry_count;
161 static void free_pv_chunk(struct pv_chunk *pc);
162 static void free_pv_entry(pmap_t pmap, pv_entry_t pv);
163 static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try);
164 static vm_page_t pmap_pv_reclaim(pmap_t locked_pmap);
165 static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va);
166 static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap,
168 static vm_page_t pmap_alloc_direct_page(unsigned int index, int req);
169 static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va,
170 vm_page_t m, vm_prot_t prot, vm_page_t mpte);
171 static void pmap_grow_direct_page(int req);
172 static int pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
174 static void pmap_remove_page(struct pmap *pmap, vm_offset_t va);
175 static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, vm_offset_t va);
176 static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte,
177 vm_offset_t va, vm_page_t m);
178 static void pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte);
179 static void pmap_invalidate_all(pmap_t pmap);
180 static void pmap_invalidate_page(pmap_t pmap, vm_offset_t va);
181 static void _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m);
183 static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags);
184 static vm_page_t _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags);
185 static int pmap_unuse_pt(pmap_t, vm_offset_t, pd_entry_t);
186 static pt_entry_t init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot);
188 static void pmap_invalidate_page_action(void *arg);
189 static void pmap_invalidate_range_action(void *arg);
190 static void pmap_update_page_action(void *arg);
194 static vm_offset_t crashdumpva;
197 * These functions are for high memory (memory above 512Meg in 32 bit) support.
198 * The highmem area does not have a KSEG0 mapping, and we need a mechanism to
199 * do temporary per-CPU mappings for pmap_zero_page, pmap_copy_page etc.
201 * At bootup, we reserve 2 virtual pages per CPU for mapping highmem pages. To
202 * access a highmem physical address on a CPU, we map the physical address to
203 * the reserved virtual address for the CPU in the kernel pagetable.
207 pmap_init_reserved_pages(void)
213 if (need_local_mappings == 0)
219 * Skip if the mapping has already been initialized,
220 * i.e. this is the BSP.
222 if (pc->pc_cmap1_addr != 0)
224 pages = kva_alloc(PAGE_SIZE * 3);
226 panic("%s: unable to allocate KVA", __func__);
227 pc->pc_cmap1_ptep = pmap_pte(kernel_pmap, pages);
228 pc->pc_cmap2_ptep = pmap_pte(kernel_pmap, pages + PAGE_SIZE);
230 pmap_pte(kernel_pmap, pages + (PAGE_SIZE * 2));
231 pc->pc_cmap1_addr = pages;
232 pc->pc_cmap2_addr = pages + PAGE_SIZE;
233 pc->pc_qmap_addr = pages + (PAGE_SIZE * 2);
236 SYSINIT(rpages_init, SI_SUB_CPU, SI_ORDER_ANY, pmap_init_reserved_pages, NULL);
239 pmap_alloc_lmem_map(void)
241 PCPU_SET(cmap1_addr, virtual_avail);
242 PCPU_SET(cmap2_addr, virtual_avail + PAGE_SIZE);
243 PCPU_SET(cmap1_ptep, pmap_pte(kernel_pmap, virtual_avail));
244 PCPU_SET(cmap2_ptep, pmap_pte(kernel_pmap, virtual_avail + PAGE_SIZE));
245 PCPU_SET(qmap_addr, virtual_avail + (2 * PAGE_SIZE));
246 PCPU_SET(qmap_ptep, pmap_pte(kernel_pmap, virtual_avail + (2 * PAGE_SIZE)));
247 crashdumpva = virtual_avail + (3 * PAGE_SIZE);
248 virtual_avail += PAGE_SIZE * 4;
251 static __inline vm_offset_t
252 pmap_lmem_map1(vm_paddr_t phys)
255 *PCPU_GET(cmap1_ptep) =
256 TLBLO_PA_TO_PFN(phys) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
257 return (PCPU_GET(cmap1_addr));
260 static __inline vm_offset_t
261 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
264 *PCPU_GET(cmap1_ptep) =
265 TLBLO_PA_TO_PFN(phys1) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
266 *PCPU_GET(cmap2_ptep) =
267 TLBLO_PA_TO_PFN(phys2) | PTE_C_CACHE | PTE_D | PTE_V | PTE_G;
268 return (PCPU_GET(cmap1_addr));
272 pmap_lmem_unmap(void)
274 *PCPU_GET(cmap1_ptep) = PTE_G;
275 tlb_invalidate_address(kernel_pmap, PCPU_GET(cmap1_addr));
276 if (*PCPU_GET(cmap2_ptep) != PTE_G) {
277 *PCPU_GET(cmap2_ptep) = PTE_G;
278 tlb_invalidate_address(kernel_pmap, PCPU_GET(cmap2_addr));
283 #else /* __mips_n64 */
286 pmap_alloc_lmem_map(void)
290 static __inline vm_offset_t
291 pmap_lmem_map1(vm_paddr_t phys)
297 static __inline vm_offset_t
298 pmap_lmem_map2(vm_paddr_t phys1, vm_paddr_t phys2)
304 static __inline vm_offset_t
305 pmap_lmem_unmap(void)
310 #endif /* !__mips_n64 */
313 pmap_pte_cache_bits(vm_paddr_t pa, vm_page_t m)
317 ma = pmap_page_get_memattr(m);
318 if (ma == VM_MEMATTR_WRITE_BACK && !is_cacheable_mem(pa))
319 ma = VM_MEMATTR_UNCACHEABLE;
322 #define PMAP_PTE_SET_CACHE_BITS(pte, ps, m) { \
323 pte &= ~PTE_C_MASK; \
324 pte |= pmap_pte_cache_bits(pa, m); \
328 * Page table entry lookup routines.
330 static __inline pd_entry_t *
331 pmap_segmap(pmap_t pmap, vm_offset_t va)
334 return (&pmap->pm_segtab[pmap_seg_index(va)]);
338 static __inline pd_entry_t *
339 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
343 pde = (pd_entry_t *)*pdpe;
344 return (&pde[pmap_pde_index(va)]);
347 static __inline pd_entry_t *
348 pmap_pde(pmap_t pmap, vm_offset_t va)
352 pdpe = pmap_segmap(pmap, va);
356 return (pmap_pdpe_to_pde(pdpe, va));
359 static __inline pd_entry_t *
360 pmap_pdpe_to_pde(pd_entry_t *pdpe, vm_offset_t va)
367 pd_entry_t *pmap_pde(pmap_t pmap, vm_offset_t va)
370 return (pmap_segmap(pmap, va));
374 static __inline pt_entry_t *
375 pmap_pde_to_pte(pd_entry_t *pde, vm_offset_t va)
379 pte = (pt_entry_t *)*pde;
380 return (&pte[pmap_pte_index(va)]);
384 pmap_pte(pmap_t pmap, vm_offset_t va)
388 pde = pmap_pde(pmap, va);
389 if (pde == NULL || *pde == NULL)
392 return (pmap_pde_to_pte(pde, va));
396 pmap_steal_memory(vm_size_t size)
398 vm_paddr_t bank_size, pa;
401 size = round_page(size);
402 bank_size = phys_avail[1] - phys_avail[0];
403 while (size > bank_size) {
406 for (i = 0; phys_avail[i + 2]; i += 2) {
407 phys_avail[i] = phys_avail[i + 2];
408 phys_avail[i + 1] = phys_avail[i + 3];
411 phys_avail[i + 1] = 0;
413 panic("pmap_steal_memory: out of memory");
414 bank_size = phys_avail[1] - phys_avail[0];
418 phys_avail[0] += size;
419 if (MIPS_DIRECT_MAPPABLE(pa) == 0)
420 panic("Out of memory below 512Meg?");
421 va = MIPS_PHYS_TO_DIRECT(pa);
422 bzero((caddr_t)va, size);
427 * Bootstrap the system enough to run with virtual memory. This
428 * assumes that the phys_avail array has been initialized.
431 pmap_create_kernel_pagetable(void)
443 * Allocate segment table for the kernel
445 kernel_segmap = (pd_entry_t *)pmap_steal_memory(PAGE_SIZE);
448 * Allocate second level page tables for the kernel
451 npde = howmany(NKPT, NPDEPG);
452 pdaddr = pmap_steal_memory(PAGE_SIZE * npde);
455 ptaddr = pmap_steal_memory(PAGE_SIZE * nkpt);
458 * The R[4-7]?00 stores only one copy of the Global bit in the
459 * translation lookaside buffer for each 2 page entry. Thus invalid
460 * entrys must have the Global bit set so when Entry LO and Entry HI
461 * G bits are anded together they will produce a global bit to store
464 for (i = 0, pte = (pt_entry_t *)ptaddr; i < (nkpt * NPTEPG); i++, pte++)
468 for (i = 0, npt = nkpt; npt > 0; i++) {
469 kernel_segmap[i] = (pd_entry_t)(pdaddr + i * PAGE_SIZE);
470 pde = (pd_entry_t *)kernel_segmap[i];
472 for (j = 0; j < NPDEPG && npt > 0; j++, npt--)
473 pde[j] = (pd_entry_t)(ptaddr + (i * NPDEPG + j) * PAGE_SIZE);
476 for (i = 0, j = pmap_seg_index(VM_MIN_KERNEL_ADDRESS); i < nkpt; i++, j++)
477 kernel_segmap[j] = (pd_entry_t)(ptaddr + (i * PAGE_SIZE));
480 PMAP_LOCK_INIT(kernel_pmap);
481 kernel_pmap->pm_segtab = kernel_segmap;
482 CPU_FILL(&kernel_pmap->pm_active);
483 TAILQ_INIT(&kernel_pmap->pm_pvchunk);
484 kernel_pmap->pm_asid[0].asid = PMAP_ASID_RESERVED;
485 kernel_pmap->pm_asid[0].gen = 0;
486 kernel_vm_end += nkpt * NPTEPG * PAGE_SIZE;
496 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
498 * Keep the memory aligned on page boundary.
500 phys_avail[i] = round_page(phys_avail[i]);
501 phys_avail[i + 1] = trunc_page(phys_avail[i + 1]);
505 if (phys_avail[i - 2] > phys_avail[i]) {
508 ptemp[0] = phys_avail[i + 0];
509 ptemp[1] = phys_avail[i + 1];
511 phys_avail[i + 0] = phys_avail[i - 2];
512 phys_avail[i + 1] = phys_avail[i - 1];
514 phys_avail[i - 2] = ptemp[0];
515 phys_avail[i - 1] = ptemp[1];
521 * In 32 bit, we may have memory which cannot be mapped directly.
522 * This memory will need temporary mapping before it can be
525 if (!MIPS_DIRECT_MAPPABLE(phys_avail[i - 1] - 1))
526 need_local_mappings = 1;
529 * Copy the phys_avail[] array before we start stealing memory from it.
531 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
532 physmem_desc[i] = phys_avail[i];
533 physmem_desc[i + 1] = phys_avail[i + 1];
536 Maxmem = atop(phys_avail[i - 1]);
539 printf("Physical memory chunk(s):\n");
540 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
543 size = phys_avail[i + 1] - phys_avail[i];
544 printf("%#08jx - %#08jx, %ju bytes (%ju pages)\n",
545 (uintmax_t) phys_avail[i],
546 (uintmax_t) phys_avail[i + 1] - 1,
547 (uintmax_t) size, (uintmax_t) size / PAGE_SIZE);
549 printf("Maxmem is 0x%0jx\n", ptoa((uintmax_t)Maxmem));
552 * Steal the message buffer from the beginning of memory.
554 msgbufp = (struct msgbuf *)pmap_steal_memory(msgbufsize);
555 msgbufinit(msgbufp, msgbufsize);
558 * Steal thread0 kstack.
560 kstack0 = pmap_steal_memory(KSTACK_PAGES << PAGE_SHIFT);
562 virtual_avail = VM_MIN_KERNEL_ADDRESS;
563 virtual_end = VM_MAX_KERNEL_ADDRESS;
567 * Steal some virtual address space to map the pcpu area.
569 virtual_avail = roundup2(virtual_avail, PAGE_SIZE * 2);
570 pcpup = (struct pcpu *)virtual_avail;
571 virtual_avail += PAGE_SIZE * 2;
574 * Initialize the wired TLB entry mapping the pcpu region for
575 * the BSP at 'pcpup'. Up until this point we were operating
576 * with the 'pcpup' for the BSP pointing to a virtual address
577 * in KSEG0 so there was no need for a TLB mapping.
579 mips_pcpu_tlb_init(PCPU_ADDR(0));
582 printf("pcpu is available at virtual address %p.\n", pcpup);
585 pmap_create_kernel_pagetable();
586 if (need_local_mappings)
587 pmap_alloc_lmem_map();
588 pmap_max_asid = VMNUM_PIDS;
593 * Initialize the global pv list lock.
595 rw_init(&pvh_global_lock, "pmap pv global");
599 * Initialize a vm_page's machine-dependent fields.
602 pmap_page_init(vm_page_t m)
605 TAILQ_INIT(&m->md.pv_list);
606 m->md.pv_flags = VM_MEMATTR_DEFAULT << PV_MEMATTR_SHIFT;
610 * Initialize the pmap module.
611 * Called by vm_init, to initialize any structures that the pmap
612 * system needs to map virtual memory.
619 /***************************************************
620 * Low level helper routines.....
621 ***************************************************/
625 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
627 int cpuid, cpu, self;
628 cpuset_t active_cpus;
631 if (is_kernel_pmap(pmap)) {
632 smp_rendezvous(NULL, fn, NULL, arg);
635 /* Force ASID update on inactive CPUs */
637 if (!CPU_ISSET(cpu, &pmap->pm_active))
638 pmap->pm_asid[cpu].gen = 0;
640 cpuid = PCPU_GET(cpuid);
642 * XXX: barrier/locking for active?
644 * Take a snapshot of active here, any further changes are ignored.
645 * tlb update/invalidate should be harmless on inactive CPUs
647 active_cpus = pmap->pm_active;
648 self = CPU_ISSET(cpuid, &active_cpus);
649 CPU_CLR(cpuid, &active_cpus);
650 /* Optimize for the case where this cpu is the only active one */
651 if (CPU_EMPTY(&active_cpus)) {
656 CPU_SET(cpuid, &active_cpus);
657 smp_rendezvous_cpus(active_cpus, NULL, fn, NULL, arg);
664 pmap_call_on_active_cpus(pmap_t pmap, void (*fn)(void *), void *arg)
668 if (is_kernel_pmap(pmap)) {
672 cpuid = PCPU_GET(cpuid);
673 if (!CPU_ISSET(cpuid, &pmap->pm_active))
674 pmap->pm_asid[cpuid].gen = 0;
681 pmap_invalidate_all(pmap_t pmap)
684 pmap_call_on_active_cpus(pmap,
685 (void (*)(void *))tlb_invalidate_all_user, pmap);
688 struct pmap_invalidate_page_arg {
694 pmap_invalidate_page_action(void *arg)
696 struct pmap_invalidate_page_arg *p = arg;
698 tlb_invalidate_address(p->pmap, p->va);
702 pmap_invalidate_page(pmap_t pmap, vm_offset_t va)
704 struct pmap_invalidate_page_arg arg;
708 pmap_call_on_active_cpus(pmap, pmap_invalidate_page_action, &arg);
711 struct pmap_invalidate_range_arg {
718 pmap_invalidate_range_action(void *arg)
720 struct pmap_invalidate_range_arg *p = arg;
722 tlb_invalidate_range(p->pmap, p->sva, p->eva);
726 pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
728 struct pmap_invalidate_range_arg arg;
733 pmap_call_on_active_cpus(pmap, pmap_invalidate_range_action, &arg);
736 struct pmap_update_page_arg {
743 pmap_update_page_action(void *arg)
745 struct pmap_update_page_arg *p = arg;
747 tlb_update(p->pmap, p->va, p->pte);
751 pmap_update_page(pmap_t pmap, vm_offset_t va, pt_entry_t pte)
753 struct pmap_update_page_arg arg;
758 pmap_call_on_active_cpus(pmap, pmap_update_page_action, &arg);
762 * Routine: pmap_extract
764 * Extract the physical page address associated
765 * with the given map/virtual_address pair.
768 pmap_extract(pmap_t pmap, vm_offset_t va)
771 vm_offset_t retval = 0;
774 pte = pmap_pte(pmap, va);
776 retval = TLBLO_PTE_TO_PA(*pte) | (va & PAGE_MASK);
783 * Routine: pmap_extract_and_hold
785 * Atomically extract and hold the physical page
786 * with the given pmap and virtual address pair
787 * if that mapping permits the given protection.
790 pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot)
792 pt_entry_t pte, *ptep;
798 ptep = pmap_pte(pmap, va);
801 if (pte_test(&pte, PTE_V) && (!pte_test(&pte, PTE_RO) ||
802 (prot & VM_PROT_WRITE) == 0)) {
803 pa = TLBLO_PTE_TO_PA(pte);
804 m = PHYS_TO_VM_PAGE(pa);
805 if (!vm_page_wire_mapped(m))
813 /***************************************************
814 * Low level mapping routines.....
815 ***************************************************/
818 * add a wired page to the kva
821 pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, vm_memattr_t ma)
824 pt_entry_t opte, npte;
827 printf("pmap_kenter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
830 pte = pmap_pte(kernel_pmap, va);
832 npte = TLBLO_PA_TO_PFN(pa) | PTE_C(ma) | PTE_D | PTE_V | PTE_G;
834 if (pte_test(&opte, PTE_V) && opte != npte)
835 pmap_update_page(kernel_pmap, va, npte);
839 pmap_kenter(vm_offset_t va, vm_paddr_t pa)
842 KASSERT(is_cacheable_mem(pa),
843 ("pmap_kenter: memory at 0x%lx is not cacheable", (u_long)pa));
845 pmap_kenter_attr(va, pa, VM_MEMATTR_DEFAULT);
849 pmap_kenter_device(vm_offset_t va, vm_size_t size, vm_paddr_t pa)
852 KASSERT((size & PAGE_MASK) == 0,
853 ("%s: device mapping not page-sized", __func__));
855 for (; size > 0; size -= PAGE_SIZE) {
857 * XXXCEM: this is somewhat inefficient on SMP systems in that
858 * every single page is individually TLB-invalidated via
859 * rendezvous (pmap_update_page()), instead of invalidating the
860 * entire range via a single rendezvous.
862 pmap_kenter_attr(va, pa, VM_MEMATTR_UNCACHEABLE);
869 pmap_kremove_device(vm_offset_t va, vm_size_t size)
872 KASSERT((size & PAGE_MASK) == 0,
873 ("%s: device mapping not page-sized", __func__));
876 * XXXCEM: Similar to pmap_kenter_device, this is inefficient on SMP,
877 * in that pages are invalidated individually instead of a single range
880 for (; size > 0; size -= PAGE_SIZE) {
887 * remove a page from the kernel pagetables
889 /* PMAP_INLINE */ void
890 pmap_kremove(vm_offset_t va)
895 * Write back all caches from the page being destroyed
897 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
899 pte = pmap_pte(kernel_pmap, va);
901 pmap_invalidate_page(kernel_pmap, va);
905 * Used to map a range of physical addresses into kernel
906 * virtual address space.
908 * The value passed in '*virt' is a suggested virtual address for
909 * the mapping. Architectures which can support a direct-mapped
910 * physical to virtual region can return the appropriate address
911 * within that region, leaving '*virt' unchanged. Other
912 * architectures should map the pages starting at '*virt' and
913 * update '*virt' with the first usable address after the mapped
916 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
919 pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot)
923 if (MIPS_DIRECT_MAPPABLE(end - 1))
924 return (MIPS_PHYS_TO_DIRECT(start));
927 while (start < end) {
928 pmap_kenter(va, start);
937 * Add a list of wired pages to the kva
938 * this routine is only used for temporary
939 * kernel mappings that do not need to have
940 * page modification or references recorded.
941 * Note that old mappings are simply written
942 * over. The page *must* be wired.
945 pmap_qenter(vm_offset_t va, vm_page_t *m, int count)
948 vm_offset_t origva = va;
950 for (i = 0; i < count; i++) {
951 pmap_flush_pvcache(m[i]);
952 pmap_kenter(va, VM_PAGE_TO_PHYS(m[i]));
956 mips_dcache_wbinv_range_index(origva, PAGE_SIZE*count);
960 * this routine jerks page mappings from the
961 * kernel -- it is meant only for temporary mappings.
964 pmap_qremove(vm_offset_t va, int count)
971 mips_dcache_wbinv_range_index(va, PAGE_SIZE * count);
974 pte = pmap_pte(kernel_pmap, va);
977 } while (--count > 0);
978 pmap_invalidate_range(kernel_pmap, origva, va);
981 /***************************************************
982 * Page table page management routines.....
983 ***************************************************/
986 * Decrements a page table page's reference count, which is used to record the
987 * number of valid page table entries within the page. If the reference count
988 * drops to zero, then the page table page is unmapped. Returns TRUE if the
989 * page table page was unmapped and FALSE otherwise.
991 static PMAP_INLINE boolean_t
992 pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
996 if (m->ref_count == 0) {
997 _pmap_unwire_ptp(pmap, va, m);
1004 _pmap_unwire_ptp(pmap_t pmap, vm_offset_t va, vm_page_t m)
1008 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1010 * unmap the page table page
1013 if (m->pindex < NUPDE)
1014 pde = pmap_pde(pmap, va);
1016 pde = pmap_segmap(pmap, va);
1018 pde = pmap_pde(pmap, va);
1021 pmap->pm_stats.resident_count--;
1024 if (m->pindex < NUPDE) {
1029 * Recursively decrement next level pagetable refcount
1031 pdp = (pd_entry_t *)*pmap_segmap(pmap, va);
1032 pdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pdp));
1033 pmap_unwire_ptp(pmap, va, pdpg);
1038 * If the page is finally unwired, simply free it.
1040 vm_page_free_zero(m);
1045 * After removing a page table entry, this routine is used to
1046 * conditionally free the page, and manage the reference count.
1049 pmap_unuse_pt(pmap_t pmap, vm_offset_t va, pd_entry_t pde)
1053 if (va >= VM_MAXUSER_ADDRESS)
1055 KASSERT(pde != 0, ("pmap_unuse_pt: pde != 0"));
1056 mpte = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(pde));
1057 return (pmap_unwire_ptp(pmap, va, mpte));
1061 pmap_pinit0(pmap_t pmap)
1065 PMAP_LOCK_INIT(pmap);
1066 pmap->pm_segtab = kernel_segmap;
1067 CPU_ZERO(&pmap->pm_active);
1068 for (i = 0; i < MAXCPU; i++) {
1069 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1070 pmap->pm_asid[i].gen = 0;
1072 PCPU_SET(curpmap, pmap);
1073 TAILQ_INIT(&pmap->pm_pvchunk);
1074 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1078 pmap_grow_direct_page(int req)
1084 if (!vm_page_reclaim_contig(req, 1, 0, MIPS_KSEG0_LARGEST_PHYS,
1091 pmap_alloc_direct_page(unsigned int index, int req)
1095 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, req | VM_ALLOC_WIRED |
1100 if ((m->flags & PG_ZERO) == 0)
1108 * Initialize a preallocated and zeroed pmap structure,
1109 * such as one in a vmspace structure.
1112 pmap_pinit(pmap_t pmap)
1119 * allocate the page directory page
1121 req_class = VM_ALLOC_NORMAL;
1122 while ((ptdpg = pmap_alloc_direct_page(NUSERPGTBLS, req_class)) ==
1124 pmap_grow_direct_page(req_class);
1126 ptdva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(ptdpg));
1127 pmap->pm_segtab = (pd_entry_t *)ptdva;
1128 CPU_ZERO(&pmap->pm_active);
1129 for (i = 0; i < MAXCPU; i++) {
1130 pmap->pm_asid[i].asid = PMAP_ASID_RESERVED;
1131 pmap->pm_asid[i].gen = 0;
1133 TAILQ_INIT(&pmap->pm_pvchunk);
1134 bzero(&pmap->pm_stats, sizeof pmap->pm_stats);
1140 * this routine is called if the page table page is not
1144 _pmap_allocpte(pmap_t pmap, unsigned ptepindex, u_int flags)
1151 * Find or fabricate a new pagetable page
1153 req_class = VM_ALLOC_NORMAL;
1154 if ((m = pmap_alloc_direct_page(ptepindex, req_class)) == NULL) {
1155 if ((flags & PMAP_ENTER_NOSLEEP) == 0) {
1157 rw_wunlock(&pvh_global_lock);
1158 pmap_grow_direct_page(req_class);
1159 rw_wlock(&pvh_global_lock);
1164 * Indicate the need to retry. While waiting, the page
1165 * table page may have been allocated.
1171 * Map the pagetable page into the process address space, if it
1172 * isn't already there.
1174 pageva = MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1177 if (ptepindex >= NUPDE) {
1178 pmap->pm_segtab[ptepindex - NUPDE] = (pd_entry_t)pageva;
1180 pd_entry_t *pdep, *pde;
1181 int segindex = ptepindex >> (SEGSHIFT - PDRSHIFT);
1182 int pdeindex = ptepindex & (NPDEPG - 1);
1185 pdep = &pmap->pm_segtab[segindex];
1186 if (*pdep == NULL) {
1187 /* recurse for allocating page dir */
1188 if (_pmap_allocpte(pmap, NUPDE + segindex,
1190 /* alloc failed, release current */
1191 vm_page_unwire_noq(m);
1192 vm_page_free_zero(m);
1196 pg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pdep));
1199 /* Next level entry */
1200 pde = (pd_entry_t *)*pdep;
1201 pde[pdeindex] = (pd_entry_t)pageva;
1204 pmap->pm_segtab[ptepindex] = (pd_entry_t)pageva;
1206 pmap->pm_stats.resident_count++;
1211 pmap_allocpte(pmap_t pmap, vm_offset_t va, u_int flags)
1218 * Calculate pagetable page index
1220 ptepindex = pmap_pde_pindex(va);
1223 * Get the page directory entry
1225 pde = pmap_pde(pmap, va);
1228 * If the page table page is mapped, we just increment the hold
1229 * count, and activate it.
1231 if (pde != NULL && *pde != NULL) {
1232 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(*pde));
1236 * Here if the pte page isn't mapped, or if it has been
1239 m = _pmap_allocpte(pmap, ptepindex, flags);
1240 if (m == NULL && (flags & PMAP_ENTER_NOSLEEP) == 0)
1247 /***************************************************
1248 * Pmap allocation/deallocation routines.
1249 ***************************************************/
1252 * Release any resources held by the given physical map.
1253 * Called when a pmap initialized by pmap_pinit is being released.
1254 * Should only be called if the map contains no valid mappings.
1257 pmap_release(pmap_t pmap)
1262 KASSERT(pmap->pm_stats.resident_count == 0,
1263 ("pmap_release: pmap resident count %ld != 0",
1264 pmap->pm_stats.resident_count));
1266 ptdva = (vm_offset_t)pmap->pm_segtab;
1267 ptdpg = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(ptdva));
1269 vm_page_unwire_noq(ptdpg);
1270 vm_page_free_zero(ptdpg);
1274 * grow the number of kernel page table entries, if needed
1277 pmap_growkernel(vm_offset_t addr)
1280 pd_entry_t *pde, *pdpe;
1284 mtx_assert(&kernel_map->system_mtx, MA_OWNED);
1285 req_class = VM_ALLOC_INTERRUPT;
1286 addr = roundup2(addr, NBSEG);
1287 if (addr - 1 >= vm_map_max(kernel_map))
1288 addr = vm_map_max(kernel_map);
1289 while (kernel_vm_end < addr) {
1290 pdpe = pmap_segmap(kernel_pmap, kernel_vm_end);
1293 /* new intermediate page table entry */
1294 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1296 panic("pmap_growkernel: no memory to grow kernel");
1297 *pdpe = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1298 continue; /* try again */
1301 pde = pmap_pdpe_to_pde(pdpe, kernel_vm_end);
1303 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1304 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1305 kernel_vm_end = vm_map_max(kernel_map);
1312 * This index is bogus, but out of the way
1314 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1316 if (nkpg == NULL && vm_page_reclaim_contig(req_class, 1,
1317 0, MIPS_KSEG0_LARGEST_PHYS, PAGE_SIZE, 0))
1318 nkpg = pmap_alloc_direct_page(nkpt, req_class);
1321 panic("pmap_growkernel: no memory to grow kernel");
1323 *pde = (pd_entry_t)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(nkpg));
1326 * The R[4-7]?00 stores only one copy of the Global bit in
1327 * the translation lookaside buffer for each 2 page entry.
1328 * Thus invalid entrys must have the Global bit set so when
1329 * Entry LO and Entry HI G bits are anded together they will
1330 * produce a global bit to store in the tlb.
1332 pte = (pt_entry_t *)*pde;
1333 for (i = 0; i < NPTEPG; i++)
1336 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK;
1337 if (kernel_vm_end - 1 >= vm_map_max(kernel_map)) {
1338 kernel_vm_end = vm_map_max(kernel_map);
1344 /***************************************************
1345 * page management routines.
1346 ***************************************************/
1348 CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE);
1350 CTASSERT(_NPCM == 3);
1351 CTASSERT(_NPCPV == 168);
1353 CTASSERT(_NPCM == 11);
1354 CTASSERT(_NPCPV == 336);
1357 static __inline struct pv_chunk *
1358 pv_to_chunk(pv_entry_t pv)
1361 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK));
1364 #define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap)
1367 #define PC_FREE0_1 0xfffffffffffffffful
1368 #define PC_FREE2 0x000000fffffffffful
1370 #define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */
1371 #define PC_FREE10 0x0000fffful /* Free values for index 10 */
1374 static const u_long pc_freemask[_NPCM] = {
1376 PC_FREE0_1, PC_FREE0_1, PC_FREE2
1378 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1379 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1380 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9,
1381 PC_FREE0_9, PC_FREE10
1385 static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters");
1387 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0,
1388 "Current number of pv entries");
1391 static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail;
1393 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0,
1394 "Current number of pv entry chunks");
1395 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0,
1396 "Current number of pv entry chunks allocated");
1397 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0,
1398 "Current number of pv entry chunks frees");
1399 SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0,
1400 "Number of times tried to get a chunk page but failed.");
1402 static long pv_entry_frees, pv_entry_allocs;
1403 static int pv_entry_spare;
1405 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0,
1406 "Current number of pv entry frees");
1407 SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0,
1408 "Current number of pv entry allocs");
1409 SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0,
1410 "Current number of spare pv entries");
1414 * We are in a serious low memory condition. Resort to
1415 * drastic measures to free some pages so we can allocate
1416 * another pv entry chunk.
1419 pmap_pv_reclaim(pmap_t locked_pmap)
1422 struct pv_chunk *pc;
1425 pt_entry_t *pte, oldpte;
1430 int bit, field, freed, idx;
1432 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED);
1435 TAILQ_INIT(&newtail);
1436 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL) {
1437 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1438 if (pmap != pc->pc_pmap) {
1440 pmap_invalidate_all(pmap);
1441 if (pmap != locked_pmap)
1445 /* Avoid deadlock and lock recursion. */
1446 if (pmap > locked_pmap)
1448 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) {
1450 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1456 * Destroy every non-wired, 4 KB page mapping in the chunk.
1459 for (field = 0; field < _NPCM; field++) {
1460 for (inuse = ~pc->pc_map[field] & pc_freemask[field];
1461 inuse != 0; inuse &= ~(1UL << bit)) {
1462 bit = ffsl(inuse) - 1;
1463 idx = field * sizeof(inuse) * NBBY + bit;
1464 pv = &pc->pc_pventry[idx];
1466 pde = pmap_pde(pmap, va);
1467 KASSERT(pde != NULL && *pde != 0,
1468 ("pmap_pv_reclaim: pde"));
1469 pte = pmap_pde_to_pte(pde, va);
1471 if (pte_test(&oldpte, PTE_W))
1473 if (is_kernel_pmap(pmap))
1477 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(oldpte));
1478 if (pte_test(&oldpte, PTE_D))
1480 if (m->md.pv_flags & PV_TABLE_REF)
1481 vm_page_aflag_set(m, PGA_REFERENCED);
1482 m->md.pv_flags &= ~PV_TABLE_REF;
1483 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1484 if (TAILQ_EMPTY(&m->md.pv_list))
1485 vm_page_aflag_clear(m, PGA_WRITEABLE);
1486 pc->pc_map[field] |= 1UL << bit;
1487 pmap_unuse_pt(pmap, va, *pde);
1492 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1495 /* Every freed mapping is for a 4 KB page. */
1496 pmap->pm_stats.resident_count -= freed;
1497 PV_STAT(pv_entry_frees += freed);
1498 PV_STAT(pv_entry_spare += freed);
1499 pv_entry_count -= freed;
1500 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1501 for (field = 0; field < _NPCM; field++)
1502 if (pc->pc_map[field] != pc_freemask[field]) {
1503 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1505 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru);
1508 * One freed pv entry in locked_pmap is
1511 if (pmap == locked_pmap)
1515 if (field == _NPCM) {
1516 PV_STAT(pv_entry_spare -= _NPCPV);
1517 PV_STAT(pc_chunk_count--);
1518 PV_STAT(pc_chunk_frees++);
1519 /* Entire chunk is free; return it. */
1520 m_pc = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS(
1522 dump_drop_page(m_pc->phys_addr);
1527 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru);
1529 pmap_invalidate_all(pmap);
1530 if (pmap != locked_pmap)
1537 * free the pv_entry back to the free list
1540 free_pv_entry(pmap_t pmap, pv_entry_t pv)
1542 struct pv_chunk *pc;
1543 int bit, field, idx;
1545 rw_assert(&pvh_global_lock, RA_WLOCKED);
1546 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1547 PV_STAT(pv_entry_frees++);
1548 PV_STAT(pv_entry_spare++);
1550 pc = pv_to_chunk(pv);
1551 idx = pv - &pc->pc_pventry[0];
1552 field = idx / (sizeof(u_long) * NBBY);
1553 bit = idx % (sizeof(u_long) * NBBY);
1554 pc->pc_map[field] |= 1ul << bit;
1555 for (idx = 0; idx < _NPCM; idx++)
1556 if (pc->pc_map[idx] != pc_freemask[idx]) {
1558 * 98% of the time, pc is already at the head of the
1559 * list. If it isn't already, move it to the head.
1561 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) !=
1563 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1564 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc,
1569 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1574 free_pv_chunk(struct pv_chunk *pc)
1578 TAILQ_REMOVE(&pv_chunks, pc, pc_lru);
1579 PV_STAT(pv_entry_spare -= _NPCPV);
1580 PV_STAT(pc_chunk_count--);
1581 PV_STAT(pc_chunk_frees++);
1582 /* entire chunk is free, return it */
1583 m = PHYS_TO_VM_PAGE(MIPS_DIRECT_TO_PHYS((vm_offset_t)pc));
1584 dump_drop_page(m->phys_addr);
1585 vm_page_unwire_noq(m);
1590 * get a new pv_entry, allocating a block from the system
1594 get_pv_entry(pmap_t pmap, boolean_t try)
1596 struct pv_chunk *pc;
1599 int bit, field, idx;
1601 rw_assert(&pvh_global_lock, RA_WLOCKED);
1602 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1603 PV_STAT(pv_entry_allocs++);
1606 pc = TAILQ_FIRST(&pmap->pm_pvchunk);
1608 for (field = 0; field < _NPCM; field++) {
1609 if (pc->pc_map[field]) {
1610 bit = ffsl(pc->pc_map[field]) - 1;
1614 if (field < _NPCM) {
1615 idx = field * sizeof(pc->pc_map[field]) * NBBY + bit;
1616 pv = &pc->pc_pventry[idx];
1617 pc->pc_map[field] &= ~(1ul << bit);
1618 /* If this was the last item, move it to tail */
1619 for (field = 0; field < _NPCM; field++)
1620 if (pc->pc_map[field] != 0) {
1621 PV_STAT(pv_entry_spare--);
1622 return (pv); /* not full, return */
1624 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
1625 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list);
1626 PV_STAT(pv_entry_spare--);
1630 /* No free items, allocate another chunk */
1631 m = vm_page_alloc_freelist(VM_FREELIST_DIRECT, VM_ALLOC_NORMAL |
1636 PV_STAT(pc_chunk_tryfail++);
1639 m = pmap_pv_reclaim(pmap);
1643 PV_STAT(pc_chunk_count++);
1644 PV_STAT(pc_chunk_allocs++);
1645 dump_add_page(m->phys_addr);
1646 pc = (struct pv_chunk *)MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
1648 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */
1649 for (field = 1; field < _NPCM; field++)
1650 pc->pc_map[field] = pc_freemask[field];
1651 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru);
1652 pv = &pc->pc_pventry[0];
1653 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list);
1654 PV_STAT(pv_entry_spare += _NPCPV - 1);
1659 pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1663 rw_assert(&pvh_global_lock, RA_WLOCKED);
1664 TAILQ_FOREACH(pv, &pvh->pv_list, pv_list) {
1665 if (pmap == PV_PMAP(pv) && va == pv->pv_va) {
1666 TAILQ_REMOVE(&pvh->pv_list, pv, pv_list);
1674 pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va)
1678 pv = pmap_pvh_remove(pvh, pmap, va);
1679 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found, pa %lx va %lx",
1680 (u_long)VM_PAGE_TO_PHYS(__containerof(pvh, struct vm_page, md)),
1682 free_pv_entry(pmap, pv);
1686 pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va)
1689 rw_assert(&pvh_global_lock, RA_WLOCKED);
1690 pmap_pvh_free(&m->md, pmap, va);
1691 if (TAILQ_EMPTY(&m->md.pv_list))
1692 vm_page_aflag_clear(m, PGA_WRITEABLE);
1696 * Conditionally create a pv entry.
1699 pmap_try_insert_pv_entry(pmap_t pmap, vm_page_t mpte, vm_offset_t va,
1704 rw_assert(&pvh_global_lock, RA_WLOCKED);
1705 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1706 if ((pv = get_pv_entry(pmap, TRUE)) != NULL) {
1708 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
1715 * pmap_remove_pte: do the things to unmap a page in a process
1718 pmap_remove_pte(struct pmap *pmap, pt_entry_t *ptq, vm_offset_t va,
1725 rw_assert(&pvh_global_lock, RA_WLOCKED);
1726 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1729 * Write back all cache lines from the page being unmapped.
1731 mips_dcache_wbinv_range_index(va, PAGE_SIZE);
1734 if (is_kernel_pmap(pmap))
1739 if (pte_test(&oldpte, PTE_W))
1740 pmap->pm_stats.wired_count -= 1;
1742 pmap->pm_stats.resident_count -= 1;
1744 if (pte_test(&oldpte, PTE_MANAGED)) {
1745 pa = TLBLO_PTE_TO_PA(oldpte);
1746 m = PHYS_TO_VM_PAGE(pa);
1747 if (pte_test(&oldpte, PTE_D)) {
1748 KASSERT(!pte_test(&oldpte, PTE_RO),
1749 ("%s: modified page not writable: va: %p, pte: %#jx",
1750 __func__, (void *)va, (uintmax_t)oldpte));
1753 if (m->md.pv_flags & PV_TABLE_REF)
1754 vm_page_aflag_set(m, PGA_REFERENCED);
1755 m->md.pv_flags &= ~PV_TABLE_REF;
1757 pmap_remove_entry(pmap, m, va);
1759 return (pmap_unuse_pt(pmap, va, pde));
1763 * Remove a single page from a process address space
1766 pmap_remove_page(struct pmap *pmap, vm_offset_t va)
1771 rw_assert(&pvh_global_lock, RA_WLOCKED);
1772 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1773 pde = pmap_pde(pmap, va);
1774 if (pde == NULL || *pde == 0)
1776 ptq = pmap_pde_to_pte(pde, va);
1779 * If there is no pte for this address, just skip it!
1781 if (!pte_test(ptq, PTE_V))
1784 (void)pmap_remove_pte(pmap, ptq, va, *pde);
1785 pmap_invalidate_page(pmap, va);
1789 * Remove the given range of addresses from the specified map.
1791 * It is assumed that the start and end are properly
1792 * rounded to the page size.
1795 pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
1797 pd_entry_t *pde, *pdpe;
1799 vm_offset_t va, va_next;
1802 * Perform an unsynchronized read. This is, however, safe.
1804 if (pmap->pm_stats.resident_count == 0)
1807 rw_wlock(&pvh_global_lock);
1811 * special handling of removing one page. a very common operation
1812 * and easy to short circuit some code.
1814 if ((sva + PAGE_SIZE) == eva) {
1815 pmap_remove_page(pmap, sva);
1818 for (; sva < eva; sva = va_next) {
1819 pdpe = pmap_segmap(pmap, sva);
1822 va_next = (sva + NBSEG) & ~SEGMASK;
1828 va_next = (sva + NBPDR) & ~PDRMASK;
1832 pde = pmap_pdpe_to_pde(pdpe, sva);
1837 * Limit our scan to either the end of the va represented
1838 * by the current page table page, or to the end of the
1839 * range being removed.
1845 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1847 if (!pte_test(pte, PTE_V)) {
1848 if (va != va_next) {
1849 pmap_invalidate_range(pmap, va, sva);
1856 if (pmap_remove_pte(pmap, pte, sva, *pde)) {
1862 pmap_invalidate_range(pmap, va, sva);
1865 rw_wunlock(&pvh_global_lock);
1870 * Routine: pmap_remove_all
1872 * Removes this physical page from
1873 * all physical maps in which it resides.
1874 * Reflects back modify bits to the pager.
1877 * Original versions of this routine were very
1878 * inefficient because they iteratively called
1879 * pmap_remove (slow...)
1883 pmap_remove_all(vm_page_t m)
1888 pt_entry_t *pte, tpte;
1890 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1891 ("pmap_remove_all: page %p is not managed", m));
1892 rw_wlock(&pvh_global_lock);
1894 if (m->md.pv_flags & PV_TABLE_REF)
1895 vm_page_aflag_set(m, PGA_REFERENCED);
1897 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) {
1902 * If it's last mapping writeback all caches from
1903 * the page being destroyed
1905 if (TAILQ_NEXT(pv, pv_list) == NULL)
1906 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
1908 pmap->pm_stats.resident_count--;
1910 pde = pmap_pde(pmap, pv->pv_va);
1911 KASSERT(pde != NULL && *pde != 0, ("pmap_remove_all: pde"));
1912 pte = pmap_pde_to_pte(pde, pv->pv_va);
1915 if (is_kernel_pmap(pmap))
1920 if (pte_test(&tpte, PTE_W))
1921 pmap->pm_stats.wired_count--;
1924 * Update the vm_page_t clean and reference bits.
1926 if (pte_test(&tpte, PTE_D)) {
1927 KASSERT(!pte_test(&tpte, PTE_RO),
1928 ("%s: modified page not writable: va: %p, pte: %#jx",
1929 __func__, (void *)pv->pv_va, (uintmax_t)tpte));
1932 pmap_invalidate_page(pmap, pv->pv_va);
1934 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
1935 pmap_unuse_pt(pmap, pv->pv_va, *pde);
1936 free_pv_entry(pmap, pv);
1940 vm_page_aflag_clear(m, PGA_WRITEABLE);
1941 m->md.pv_flags &= ~PV_TABLE_REF;
1942 rw_wunlock(&pvh_global_lock);
1946 * Set the physical protection on the
1947 * specified range of this map as requested.
1950 pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot)
1952 pt_entry_t pbits, *pte;
1953 pd_entry_t *pde, *pdpe;
1954 vm_offset_t va, va_next;
1958 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1959 pmap_remove(pmap, sva, eva);
1962 if (prot & VM_PROT_WRITE)
1966 for (; sva < eva; sva = va_next) {
1967 pdpe = pmap_segmap(pmap, sva);
1970 va_next = (sva + NBSEG) & ~SEGMASK;
1976 va_next = (sva + NBPDR) & ~PDRMASK;
1980 pde = pmap_pdpe_to_pde(pdpe, sva);
1985 * Limit our scan to either the end of the va represented
1986 * by the current page table page, or to the end of the
1987 * range being write protected.
1993 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
1996 if (!pte_test(&pbits, PTE_V) || pte_test(&pbits,
1998 if (va != va_next) {
1999 pmap_invalidate_range(pmap, va, sva);
2004 pte_set(&pbits, PTE_RO);
2005 if (pte_test(&pbits, PTE_D)) {
2006 pte_clear(&pbits, PTE_D);
2007 if (pte_test(&pbits, PTE_MANAGED)) {
2008 pa = TLBLO_PTE_TO_PA(pbits);
2009 m = PHYS_TO_VM_PAGE(pa);
2016 * Unless PTE_D is set, any TLB entries
2017 * mapping "sva" don't allow write access, so
2018 * they needn't be invalidated.
2020 if (va != va_next) {
2021 pmap_invalidate_range(pmap, va, sva);
2028 pmap_invalidate_range(pmap, va, sva);
2034 * Insert the given physical page (p) at
2035 * the specified virtual address (v) in the
2036 * target physical map with the protection requested.
2038 * If specified, the page will be wired down, meaning
2039 * that the related pte can not be reclaimed.
2041 * NB: This is the only routine which MAY NOT lazy-evaluate
2042 * or lose information. That is, this routine must actually
2043 * insert this page into the given map NOW.
2046 pmap_enter(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
2047 u_int flags, int8_t psind __unused)
2051 pt_entry_t origpte, newpte;
2056 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig"));
2057 KASSERT((m->oflags & VPO_UNMANAGED) != 0 || va < kmi.clean_sva ||
2058 va >= kmi.clean_eva,
2059 ("pmap_enter: managed mapping within the clean submap"));
2060 if ((m->oflags & VPO_UNMANAGED) == 0)
2061 VM_PAGE_OBJECT_BUSY_ASSERT(m);
2062 pa = VM_PAGE_TO_PHYS(m);
2063 newpte = TLBLO_PA_TO_PFN(pa) | init_pte_prot(m, flags, prot);
2064 if ((flags & PMAP_ENTER_WIRED) != 0)
2066 if (is_kernel_pmap(pmap))
2068 PMAP_PTE_SET_CACHE_BITS(newpte, pa, m);
2069 if ((m->oflags & VPO_UNMANAGED) == 0)
2070 newpte |= PTE_MANAGED;
2074 rw_wlock(&pvh_global_lock);
2078 * In the case that a page table page is not resident, we are
2081 if (va < VM_MAXUSER_ADDRESS) {
2082 mpte = pmap_allocpte(pmap, va, flags);
2084 KASSERT((flags & PMAP_ENTER_NOSLEEP) != 0,
2085 ("pmap_allocpte failed with sleep allowed"));
2086 rw_wunlock(&pvh_global_lock);
2088 return (KERN_RESOURCE_SHORTAGE);
2091 pte = pmap_pte(pmap, va);
2094 * Page Directory table entry not valid, we need a new PT page
2097 panic("pmap_enter: invalid page directory, pdir=%p, va=%p",
2098 (void *)pmap->pm_segtab, (void *)va);
2102 KASSERT(!pte_test(&origpte, PTE_D | PTE_RO | PTE_V),
2103 ("pmap_enter: modified page not writable: va: %p, pte: %#jx",
2104 (void *)va, (uintmax_t)origpte));
2105 opa = TLBLO_PTE_TO_PA(origpte);
2108 * Mapping has not changed, must be protection or wiring change.
2110 if (pte_test(&origpte, PTE_V) && opa == pa) {
2112 * Wiring change, just update stats. We don't worry about
2113 * wiring PT pages as they remain resident as long as there
2114 * are valid mappings in them. Hence, if a user page is
2115 * wired, the PT page will be also.
2117 if (pte_test(&newpte, PTE_W) && !pte_test(&origpte, PTE_W))
2118 pmap->pm_stats.wired_count++;
2119 else if (!pte_test(&newpte, PTE_W) && pte_test(&origpte,
2121 pmap->pm_stats.wired_count--;
2124 * Remove extra pte reference
2129 if (pte_test(&origpte, PTE_MANAGED)) {
2130 m->md.pv_flags |= PV_TABLE_REF;
2131 if (!pte_test(&newpte, PTE_RO))
2132 vm_page_aflag_set(m, PGA_WRITEABLE);
2140 * Mapping has changed, invalidate old range and fall through to
2141 * handle validating new mapping.
2144 if (is_kernel_pmap(pmap))
2148 if (pte_test(&origpte, PTE_W))
2149 pmap->pm_stats.wired_count--;
2150 if (pte_test(&origpte, PTE_MANAGED)) {
2151 om = PHYS_TO_VM_PAGE(opa);
2152 if (pte_test(&origpte, PTE_D))
2154 if ((om->md.pv_flags & PV_TABLE_REF) != 0) {
2155 om->md.pv_flags &= ~PV_TABLE_REF;
2156 vm_page_aflag_set(om, PGA_REFERENCED);
2158 pv = pmap_pvh_remove(&om->md, pmap, va);
2159 if (!pte_test(&newpte, PTE_MANAGED))
2160 free_pv_entry(pmap, pv);
2161 if ((om->aflags & PGA_WRITEABLE) != 0 &&
2162 TAILQ_EMPTY(&om->md.pv_list))
2163 vm_page_aflag_clear(om, PGA_WRITEABLE);
2165 pmap_invalidate_page(pmap, va);
2169 KASSERT(mpte->ref_count > 0,
2170 ("pmap_enter: missing reference to page table page,"
2171 " va: %p", (void *)va));
2174 pmap->pm_stats.resident_count++;
2177 * Enter on the PV list if part of our managed memory.
2179 if (pte_test(&newpte, PTE_MANAGED)) {
2180 m->md.pv_flags |= PV_TABLE_REF;
2182 pv = get_pv_entry(pmap, FALSE);
2185 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_list);
2186 if (!pte_test(&newpte, PTE_RO))
2187 vm_page_aflag_set(m, PGA_WRITEABLE);
2191 * Increment counters
2193 if (pte_test(&newpte, PTE_W))
2194 pmap->pm_stats.wired_count++;
2199 printf("pmap_enter: va: %p -> pa: %p\n", (void *)va, (void *)pa);
2203 * if the mapping or permission bits are different, we need to
2206 if (origpte != newpte) {
2208 if (pte_test(&origpte, PTE_V)) {
2209 KASSERT(opa == pa, ("pmap_enter: invalid update"));
2210 if (pte_test(&origpte, PTE_D)) {
2211 if (pte_test(&origpte, PTE_MANAGED))
2214 pmap_update_page(pmap, va, newpte);
2219 * Sync I & D caches for executable pages. Do this only if the
2220 * target pmap belongs to the current process. Otherwise, an
2221 * unresolvable TLB miss may occur.
2223 if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) &&
2224 (prot & VM_PROT_EXECUTE)) {
2225 mips_icache_sync_range(va, PAGE_SIZE);
2226 mips_dcache_wbinv_range(va, PAGE_SIZE);
2228 rw_wunlock(&pvh_global_lock);
2230 return (KERN_SUCCESS);
2234 * this code makes some *MAJOR* assumptions:
2235 * 1. Current pmap & pmap exists.
2238 * 4. No page table pages.
2239 * but is *MUCH* faster than pmap_enter...
2243 pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot)
2246 rw_wlock(&pvh_global_lock);
2248 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL);
2249 rw_wunlock(&pvh_global_lock);
2254 pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m,
2255 vm_prot_t prot, vm_page_t mpte)
2257 pt_entry_t *pte, npte;
2260 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva ||
2261 (m->oflags & VPO_UNMANAGED) != 0,
2262 ("pmap_enter_quick_locked: managed mapping within the clean submap"));
2263 rw_assert(&pvh_global_lock, RA_WLOCKED);
2264 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
2267 * In the case that a page table page is not resident, we are
2270 if (va < VM_MAXUSER_ADDRESS) {
2275 * Calculate pagetable page index
2277 ptepindex = pmap_pde_pindex(va);
2278 if (mpte && (mpte->pindex == ptepindex)) {
2282 * Get the page directory entry
2284 pde = pmap_pde(pmap, va);
2287 * If the page table page is mapped, we just
2288 * increment the hold count, and activate it.
2290 if (pde && *pde != 0) {
2291 mpte = PHYS_TO_VM_PAGE(
2292 MIPS_DIRECT_TO_PHYS(*pde));
2295 mpte = _pmap_allocpte(pmap, ptepindex,
2296 PMAP_ENTER_NOSLEEP);
2305 pte = pmap_pte(pmap, va);
2306 if (pte_test(pte, PTE_V)) {
2315 * Enter on the PV list if part of our managed memory.
2317 if ((m->oflags & VPO_UNMANAGED) == 0 &&
2318 !pmap_try_insert_pv_entry(pmap, mpte, va, m)) {
2320 pmap_unwire_ptp(pmap, va, mpte);
2327 * Increment counters
2329 pmap->pm_stats.resident_count++;
2331 pa = VM_PAGE_TO_PHYS(m);
2334 * Now validate mapping with RO protection
2336 npte = PTE_RO | TLBLO_PA_TO_PFN(pa) | PTE_V;
2337 if ((m->oflags & VPO_UNMANAGED) == 0)
2338 npte |= PTE_MANAGED;
2340 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2342 if (is_kernel_pmap(pmap))
2343 *pte = npte | PTE_G;
2347 * Sync I & D caches. Do this only if the target pmap
2348 * belongs to the current process. Otherwise, an
2349 * unresolvable TLB miss may occur. */
2350 if (pmap == &curproc->p_vmspace->vm_pmap) {
2352 mips_icache_sync_range(va, PAGE_SIZE);
2353 mips_dcache_wbinv_range(va, PAGE_SIZE);
2360 * Make a temporary mapping for a physical address. This is only intended
2361 * to be used for panic dumps.
2363 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2366 pmap_kenter_temporary(vm_paddr_t pa, int i)
2371 printf("%s: ERROR!!! More than one page of virtual address mapping not supported\n",
2374 if (MIPS_DIRECT_MAPPABLE(pa)) {
2375 va = MIPS_PHYS_TO_DIRECT(pa);
2377 #ifndef __mips_n64 /* XXX : to be converted to new style */
2378 pt_entry_t *pte, npte;
2380 pte = pmap_pte(kernel_pmap, crashdumpva);
2382 /* Since this is for the debugger, no locks or any other fun */
2383 npte = TLBLO_PA_TO_PFN(pa) | PTE_C_CACHE | PTE_D | PTE_V |
2386 pmap_update_page(kernel_pmap, crashdumpva, npte);
2390 return ((void *)va);
2394 pmap_kenter_temporary_free(vm_paddr_t pa)
2396 #ifndef __mips_n64 /* XXX : to be converted to new style */
2399 if (MIPS_DIRECT_MAPPABLE(pa)) {
2400 /* nothing to do for this case */
2403 #ifndef __mips_n64 /* XXX : to be converted to new style */
2404 pte = pmap_pte(kernel_pmap, crashdumpva);
2406 pmap_invalidate_page(kernel_pmap, crashdumpva);
2411 * Maps a sequence of resident pages belonging to the same object.
2412 * The sequence begins with the given page m_start. This page is
2413 * mapped at the given virtual address start. Each subsequent page is
2414 * mapped at a virtual address that is offset from start by the same
2415 * amount as the page is offset from m_start within the object. The
2416 * last page in the sequence is the page with the largest offset from
2417 * m_start that can be mapped at a virtual address less than the given
2418 * virtual address end. Not every virtual page between start and end
2419 * is mapped; only those for which a resident page exists with the
2420 * corresponding offset from m_start are mapped.
2423 pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end,
2424 vm_page_t m_start, vm_prot_t prot)
2427 vm_pindex_t diff, psize;
2429 VM_OBJECT_ASSERT_LOCKED(m_start->object);
2431 psize = atop(end - start);
2434 rw_wlock(&pvh_global_lock);
2436 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
2437 mpte = pmap_enter_quick_locked(pmap, start + ptoa(diff), m,
2439 m = TAILQ_NEXT(m, listq);
2441 rw_wunlock(&pvh_global_lock);
2446 * pmap_object_init_pt preloads the ptes for a given object
2447 * into the specified pmap. This eliminates the blast of soft
2448 * faults on process startup and immediately after an mmap.
2451 pmap_object_init_pt(pmap_t pmap, vm_offset_t addr,
2452 vm_object_t object, vm_pindex_t pindex, vm_size_t size)
2454 VM_OBJECT_ASSERT_WLOCKED(object);
2455 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG,
2456 ("pmap_object_init_pt: non-device object"));
2460 * Clear the wired attribute from the mappings for the specified range of
2461 * addresses in the given pmap. Every valid mapping within that range
2462 * must have the wired attribute set. In contrast, invalid mappings
2463 * cannot have the wired attribute set, so they are ignored.
2465 * The wired attribute of the page table entry is not a hardware feature,
2466 * so there is no need to invalidate any TLB entries.
2469 pmap_unwire(pmap_t pmap, vm_offset_t sva, vm_offset_t eva)
2471 pd_entry_t *pde, *pdpe;
2473 vm_offset_t va_next;
2476 for (; sva < eva; sva = va_next) {
2477 pdpe = pmap_segmap(pmap, sva);
2479 if (*pdpe == NULL) {
2480 va_next = (sva + NBSEG) & ~SEGMASK;
2486 va_next = (sva + NBPDR) & ~PDRMASK;
2489 pde = pmap_pdpe_to_pde(pdpe, sva);
2494 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
2496 if (!pte_test(pte, PTE_V))
2498 if (!pte_test(pte, PTE_W))
2499 panic("pmap_unwire: pte %#jx is missing PG_W",
2501 pte_clear(pte, PTE_W);
2502 pmap->pm_stats.wired_count--;
2509 * Copy the range specified by src_addr/len
2510 * from the source map to the range dst_addr/len
2511 * in the destination map.
2513 * This routine is only advisory and need not do anything.
2517 pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr,
2518 vm_size_t len, vm_offset_t src_addr)
2523 * pmap_zero_page zeros the specified hardware page by mapping
2524 * the page into KVM and using bzero to clear its contents.
2526 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2529 pmap_zero_page(vm_page_t m)
2532 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2534 if (MIPS_DIRECT_MAPPABLE(phys)) {
2535 va = MIPS_PHYS_TO_DIRECT(phys);
2536 bzero((caddr_t)va, PAGE_SIZE);
2537 mips_dcache_wbinv_range(va, PAGE_SIZE);
2539 va = pmap_lmem_map1(phys);
2540 bzero((caddr_t)va, PAGE_SIZE);
2541 mips_dcache_wbinv_range(va, PAGE_SIZE);
2547 * pmap_zero_page_area zeros the specified hardware page by mapping
2548 * the page into KVM and using bzero to clear its contents.
2550 * off and size may not cover an area beyond a single hardware page.
2553 pmap_zero_page_area(vm_page_t m, int off, int size)
2556 vm_paddr_t phys = VM_PAGE_TO_PHYS(m);
2558 if (MIPS_DIRECT_MAPPABLE(phys)) {
2559 va = MIPS_PHYS_TO_DIRECT(phys);
2560 bzero((char *)(caddr_t)va + off, size);
2561 mips_dcache_wbinv_range(va + off, size);
2563 va = pmap_lmem_map1(phys);
2564 bzero((char *)va + off, size);
2565 mips_dcache_wbinv_range(va + off, size);
2571 * pmap_copy_page copies the specified (machine independent)
2572 * page by mapping the page into virtual memory and using
2573 * bcopy to copy the page, one machine dependent page at a
2576 * Use XKPHYS for 64 bit, and KSEG0 where possible for 32 bit.
2579 pmap_copy_page(vm_page_t src, vm_page_t dst)
2581 vm_offset_t va_src, va_dst;
2582 vm_paddr_t phys_src = VM_PAGE_TO_PHYS(src);
2583 vm_paddr_t phys_dst = VM_PAGE_TO_PHYS(dst);
2585 if (MIPS_DIRECT_MAPPABLE(phys_src) && MIPS_DIRECT_MAPPABLE(phys_dst)) {
2586 /* easy case, all can be accessed via KSEG0 */
2588 * Flush all caches for VA that are mapped to this page
2589 * to make sure that data in SDRAM is up to date
2591 pmap_flush_pvcache(src);
2592 mips_dcache_wbinv_range_index(
2593 MIPS_PHYS_TO_DIRECT(phys_dst), PAGE_SIZE);
2594 va_src = MIPS_PHYS_TO_DIRECT(phys_src);
2595 va_dst = MIPS_PHYS_TO_DIRECT(phys_dst);
2596 bcopy((caddr_t)va_src, (caddr_t)va_dst, PAGE_SIZE);
2597 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2599 va_src = pmap_lmem_map2(phys_src, phys_dst);
2600 va_dst = va_src + PAGE_SIZE;
2601 bcopy((void *)va_src, (void *)va_dst, PAGE_SIZE);
2602 mips_dcache_wbinv_range(va_dst, PAGE_SIZE);
2607 int unmapped_buf_allowed;
2610 pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[],
2611 vm_offset_t b_offset, int xfersize)
2615 vm_offset_t a_pg_offset, b_pg_offset;
2616 vm_paddr_t a_phys, b_phys;
2619 while (xfersize > 0) {
2620 a_pg_offset = a_offset & PAGE_MASK;
2621 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
2622 a_m = ma[a_offset >> PAGE_SHIFT];
2623 a_phys = VM_PAGE_TO_PHYS(a_m);
2624 b_pg_offset = b_offset & PAGE_MASK;
2625 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
2626 b_m = mb[b_offset >> PAGE_SHIFT];
2627 b_phys = VM_PAGE_TO_PHYS(b_m);
2628 if (MIPS_DIRECT_MAPPABLE(a_phys) &&
2629 MIPS_DIRECT_MAPPABLE(b_phys)) {
2630 pmap_flush_pvcache(a_m);
2631 mips_dcache_wbinv_range_index(
2632 MIPS_PHYS_TO_DIRECT(b_phys), PAGE_SIZE);
2633 a_cp = (char *)MIPS_PHYS_TO_DIRECT(a_phys) +
2635 b_cp = (char *)MIPS_PHYS_TO_DIRECT(b_phys) +
2637 bcopy(a_cp, b_cp, cnt);
2638 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2640 a_cp = (char *)pmap_lmem_map2(a_phys, b_phys);
2641 b_cp = (char *)a_cp + PAGE_SIZE;
2642 a_cp += a_pg_offset;
2643 b_cp += b_pg_offset;
2644 bcopy(a_cp, b_cp, cnt);
2645 mips_dcache_wbinv_range((vm_offset_t)b_cp, cnt);
2655 pmap_quick_enter_page(vm_page_t m)
2657 #if defined(__mips_n64)
2658 return MIPS_PHYS_TO_DIRECT(VM_PAGE_TO_PHYS(m));
2662 pt_entry_t *pte, npte;
2664 pa = VM_PAGE_TO_PHYS(m);
2666 if (MIPS_DIRECT_MAPPABLE(pa)) {
2667 if (pmap_page_get_memattr(m) != VM_MEMATTR_WRITE_BACK)
2668 return (MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
2670 return (MIPS_PHYS_TO_DIRECT(pa));
2673 qaddr = PCPU_GET(qmap_addr);
2674 pte = PCPU_GET(qmap_ptep);
2676 KASSERT(*pte == PTE_G, ("pmap_quick_enter_page: PTE busy"));
2678 npte = TLBLO_PA_TO_PFN(pa) | PTE_D | PTE_V | PTE_G;
2679 PMAP_PTE_SET_CACHE_BITS(npte, pa, m);
2687 pmap_quick_remove_page(vm_offset_t addr)
2689 mips_dcache_wbinv_range(addr, PAGE_SIZE);
2691 #if !defined(__mips_n64)
2694 if (addr >= MIPS_KSEG0_START && addr < MIPS_KSEG0_END)
2697 pte = PCPU_GET(qmap_ptep);
2699 KASSERT(*pte != PTE_G,
2700 ("pmap_quick_remove_page: PTE not in use"));
2701 KASSERT(PCPU_GET(qmap_addr) == addr,
2702 ("pmap_quick_remove_page: invalid address"));
2705 tlb_invalidate_address(kernel_pmap, addr);
2711 * Returns true if the pmap's pv is one of the first
2712 * 16 pvs linked to from this page. This count may
2713 * be changed upwards or downwards in the future; it
2714 * is only necessary that true be returned for a small
2715 * subset of pmaps for proper page aging.
2718 pmap_page_exists_quick(pmap_t pmap, vm_page_t m)
2724 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2725 ("pmap_page_exists_quick: page %p is not managed", m));
2727 rw_wlock(&pvh_global_lock);
2728 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2729 if (PV_PMAP(pv) == pmap) {
2737 rw_wunlock(&pvh_global_lock);
2742 * Remove all pages from specified address space
2743 * this aids process exit speeds. Also, this code
2744 * is special cased for current process only, but
2745 * can have the more generic (and slightly slower)
2746 * mode enabled. This is much faster than pmap_remove
2747 * in the case of running down an entire address space.
2750 pmap_remove_pages(pmap_t pmap)
2753 pt_entry_t *pte, tpte;
2756 struct pv_chunk *pc, *npc;
2757 u_long inuse, bitmask;
2758 int allfree, bit, field, idx;
2760 if (pmap != vmspace_pmap(curthread->td_proc->p_vmspace)) {
2761 printf("warning: pmap_remove_pages called with non-current pmap\n");
2764 rw_wlock(&pvh_global_lock);
2766 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) {
2768 for (field = 0; field < _NPCM; field++) {
2769 inuse = ~pc->pc_map[field] & pc_freemask[field];
2770 while (inuse != 0) {
2771 bit = ffsl(inuse) - 1;
2772 bitmask = 1UL << bit;
2773 idx = field * sizeof(inuse) * NBBY + bit;
2774 pv = &pc->pc_pventry[idx];
2777 pde = pmap_pde(pmap, pv->pv_va);
2778 KASSERT(pde != NULL && *pde != 0,
2779 ("pmap_remove_pages: pde"));
2780 pte = pmap_pde_to_pte(pde, pv->pv_va);
2781 if (!pte_test(pte, PTE_V))
2782 panic("pmap_remove_pages: bad pte");
2786 * We cannot remove wired pages from a process' mapping at this time
2788 if (pte_test(&tpte, PTE_W)) {
2792 *pte = is_kernel_pmap(pmap) ? PTE_G : 0;
2794 m = PHYS_TO_VM_PAGE(TLBLO_PTE_TO_PA(tpte));
2796 ("pmap_remove_pages: bad tpte %#jx",
2800 * Update the vm_page_t clean and reference bits.
2802 if (pte_test(&tpte, PTE_D))
2806 PV_STAT(pv_entry_frees++);
2807 PV_STAT(pv_entry_spare++);
2809 pc->pc_map[field] |= bitmask;
2810 pmap->pm_stats.resident_count--;
2811 TAILQ_REMOVE(&m->md.pv_list, pv, pv_list);
2812 if (TAILQ_EMPTY(&m->md.pv_list))
2813 vm_page_aflag_clear(m, PGA_WRITEABLE);
2814 pmap_unuse_pt(pmap, pv->pv_va, *pde);
2818 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list);
2822 pmap_invalidate_all(pmap);
2824 rw_wunlock(&pvh_global_lock);
2828 * pmap_testbit tests bits in pte's
2831 pmap_testbit(vm_page_t m, int bit)
2836 boolean_t rv = FALSE;
2838 if (m->oflags & VPO_UNMANAGED)
2841 rw_assert(&pvh_global_lock, RA_WLOCKED);
2842 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2845 pte = pmap_pte(pmap, pv->pv_va);
2846 rv = pte_test(pte, bit);
2855 * pmap_page_wired_mappings:
2857 * Return the number of managed mappings to the given physical page
2861 pmap_page_wired_mappings(vm_page_t m)
2869 if ((m->oflags & VPO_UNMANAGED) != 0)
2871 rw_wlock(&pvh_global_lock);
2872 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2875 pte = pmap_pte(pmap, pv->pv_va);
2876 if (pte_test(pte, PTE_W))
2880 rw_wunlock(&pvh_global_lock);
2885 * Clear the write and modified bits in each of the given page's mappings.
2888 pmap_remove_write(vm_page_t m)
2891 pt_entry_t pbits, *pte;
2894 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2895 ("pmap_remove_write: page %p is not managed", m));
2896 vm_page_assert_busied(m);
2898 if (!pmap_page_is_write_mapped(m))
2900 rw_wlock(&pvh_global_lock);
2901 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
2904 pte = pmap_pte(pmap, pv->pv_va);
2905 KASSERT(pte != NULL && pte_test(pte, PTE_V),
2906 ("page on pv_list has no pte"));
2908 if (pte_test(&pbits, PTE_D)) {
2909 pte_clear(&pbits, PTE_D);
2912 pte_set(&pbits, PTE_RO);
2913 if (pbits != *pte) {
2915 pmap_update_page(pmap, pv->pv_va, pbits);
2919 vm_page_aflag_clear(m, PGA_WRITEABLE);
2920 rw_wunlock(&pvh_global_lock);
2924 * pmap_ts_referenced:
2926 * Return the count of reference bits for a page, clearing all of them.
2929 pmap_ts_referenced(vm_page_t m)
2932 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2933 ("pmap_ts_referenced: page %p is not managed", m));
2934 if (m->md.pv_flags & PV_TABLE_REF) {
2935 rw_wlock(&pvh_global_lock);
2936 m->md.pv_flags &= ~PV_TABLE_REF;
2937 rw_wunlock(&pvh_global_lock);
2946 * Return whether or not the specified physical page was modified
2947 * in any physical maps.
2950 pmap_is_modified(vm_page_t m)
2954 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
2955 ("pmap_is_modified: page %p is not managed", m));
2958 * If the page is not busied then this check is racy.
2960 if (!pmap_page_is_write_mapped(m))
2963 rw_wlock(&pvh_global_lock);
2964 rv = pmap_testbit(m, PTE_D);
2965 rw_wunlock(&pvh_global_lock);
2972 * pmap_is_prefaultable:
2974 * Return whether or not the specified virtual address is elgible
2978 pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr)
2986 pde = pmap_pde(pmap, addr);
2987 if (pde != NULL && *pde != 0) {
2988 pte = pmap_pde_to_pte(pde, addr);
2996 * Apply the given advice to the specified range of addresses within the
2997 * given pmap. Depending on the advice, clear the referenced and/or
2998 * modified flags in each mapping and set the mapped page's dirty field.
3001 pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice)
3003 pd_entry_t *pde, *pdpe;
3005 vm_offset_t va, va_next;
3009 if (advice != MADV_DONTNEED && advice != MADV_FREE)
3011 rw_wlock(&pvh_global_lock);
3013 for (; sva < eva; sva = va_next) {
3014 pdpe = pmap_segmap(pmap, sva);
3017 va_next = (sva + NBSEG) & ~SEGMASK;
3023 va_next = (sva + NBPDR) & ~PDRMASK;
3027 pde = pmap_pdpe_to_pde(pdpe, sva);
3032 * Limit our scan to either the end of the va represented
3033 * by the current page table page, or to the end of the
3034 * range being write protected.
3040 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3042 if (!pte_test(pte, PTE_MANAGED | PTE_V)) {
3043 if (va != va_next) {
3044 pmap_invalidate_range(pmap, va, sva);
3049 pa = TLBLO_PTE_TO_PA(*pte);
3050 m = PHYS_TO_VM_PAGE(pa);
3051 m->md.pv_flags &= ~PV_TABLE_REF;
3052 if (pte_test(pte, PTE_D)) {
3053 if (advice == MADV_DONTNEED) {
3055 * Future calls to pmap_is_modified()
3056 * can be avoided by making the page
3061 pte_clear(pte, PTE_D);
3067 * Unless PTE_D is set, any TLB entries
3068 * mapping "sva" don't allow write access, so
3069 * they needn't be invalidated.
3071 if (va != va_next) {
3072 pmap_invalidate_range(pmap, va, sva);
3078 pmap_invalidate_range(pmap, va, sva);
3080 rw_wunlock(&pvh_global_lock);
3085 * Clear the modify bits on the specified physical page.
3088 pmap_clear_modify(vm_page_t m)
3094 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3095 ("pmap_clear_modify: page %p is not managed", m));
3096 VM_OBJECT_ASSERT_WLOCKED(m->object);
3097 vm_page_assert_busied(m);
3099 if (!pmap_page_is_write_mapped(m))
3101 rw_wlock(&pvh_global_lock);
3102 TAILQ_FOREACH(pv, &m->md.pv_list, pv_list) {
3105 pte = pmap_pte(pmap, pv->pv_va);
3106 if (pte_test(pte, PTE_D)) {
3107 pte_clear(pte, PTE_D);
3108 pmap_update_page(pmap, pv->pv_va, *pte);
3112 rw_wunlock(&pvh_global_lock);
3116 * pmap_is_referenced:
3118 * Return whether or not the specified physical page was referenced
3119 * in any physical maps.
3122 pmap_is_referenced(vm_page_t m)
3125 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
3126 ("pmap_is_referenced: page %p is not managed", m));
3127 return ((m->md.pv_flags & PV_TABLE_REF) != 0);
3131 * Miscellaneous support routines follow
3135 * Map a set of physical memory pages into the kernel virtual
3136 * address space. Return a pointer to where it is mapped. This
3137 * routine is intended to be used for mapping device memory,
3140 * Use XKPHYS uncached for 64 bit, and KSEG1 where possible for 32 bit.
3143 pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, vm_memattr_t ma)
3145 vm_offset_t va, tmpva, offset;
3148 * KSEG1 maps only first 512M of phys address space. For
3149 * pa > 0x20000000 we should make proper mapping * using pmap_kenter.
3151 if (MIPS_DIRECT_MAPPABLE(pa + size - 1) && ma == VM_MEMATTR_UNCACHEABLE)
3152 return ((void *)MIPS_PHYS_TO_DIRECT_UNCACHED(pa));
3154 offset = pa & PAGE_MASK;
3155 size = roundup(size + offset, PAGE_SIZE);
3157 va = kva_alloc(size);
3159 panic("pmap_mapdev: Couldn't alloc kernel virtual memory");
3160 pa = trunc_page(pa);
3161 for (tmpva = va; size > 0;) {
3162 pmap_kenter_attr(tmpva, pa, ma);
3169 return ((void *)(va + offset));
3173 pmap_mapdev(vm_paddr_t pa, vm_size_t size)
3175 return pmap_mapdev_attr(pa, size, VM_MEMATTR_UNCACHEABLE);
3179 pmap_unmapdev(vm_offset_t va, vm_size_t size)
3182 vm_offset_t base, offset;
3184 /* If the address is within KSEG1 then there is nothing to do */
3185 if (va >= MIPS_KSEG1_START && va <= MIPS_KSEG1_END)
3188 base = trunc_page(va);
3189 offset = va & PAGE_MASK;
3190 size = roundup(size + offset, PAGE_SIZE);
3191 kva_free(base, size);
3196 * Perform the pmap work for mincore(2). If the page is not both referenced and
3197 * modified by this pmap, returns its physical address so that the caller can
3198 * find other mappings.
3201 pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *pap)
3203 pt_entry_t *ptep, pte;
3209 ptep = pmap_pte(pmap, addr);
3210 pte = (ptep != NULL) ? *ptep : 0;
3211 if (!pte_test(&pte, PTE_V)) {
3215 val = MINCORE_INCORE;
3216 if (pte_test(&pte, PTE_D))
3217 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER;
3218 pa = TLBLO_PTE_TO_PA(pte);
3219 if (pte_test(&pte, PTE_MANAGED)) {
3221 * This may falsely report the given address as
3222 * MINCORE_REFERENCED. Unfortunately, due to the lack of
3223 * per-PTE reference information, it is impossible to
3224 * determine if the address is MINCORE_REFERENCED.
3226 m = PHYS_TO_VM_PAGE(pa);
3227 if ((m->aflags & PGA_REFERENCED) != 0)
3228 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER;
3230 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) !=
3231 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) &&
3232 pte_test(&pte, PTE_MANAGED)) {
3240 pmap_activate(struct thread *td)
3242 pmap_t pmap, oldpmap;
3243 struct proc *p = td->td_proc;
3248 pmap = vmspace_pmap(p->p_vmspace);
3249 oldpmap = PCPU_GET(curpmap);
3250 cpuid = PCPU_GET(cpuid);
3253 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active);
3254 CPU_SET_ATOMIC(cpuid, &pmap->pm_active);
3255 pmap_asid_alloc(pmap);
3256 if (td == curthread) {
3257 PCPU_SET(segbase, pmap->pm_segtab);
3258 mips_wr_entryhi(pmap->pm_asid[cpuid].asid);
3261 PCPU_SET(curpmap, pmap);
3266 pmap_sync_icache_one(void *arg __unused)
3269 mips_icache_sync_all();
3270 mips_dcache_wbinv_all();
3274 pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz)
3277 smp_rendezvous(NULL, pmap_sync_icache_one, NULL, NULL);
3281 * Increase the starting virtual address of the given mapping if a
3282 * different alignment might result in more superpage mappings.
3285 pmap_align_superpage(vm_object_t object, vm_ooffset_t offset,
3286 vm_offset_t *addr, vm_size_t size)
3288 vm_offset_t superpage_offset;
3292 if (object != NULL && (object->flags & OBJ_COLORED) != 0)
3293 offset += ptoa(object->pg_color);
3294 superpage_offset = offset & PDRMASK;
3295 if (size - ((PDRSIZE - superpage_offset) & PDRMASK) < PDRSIZE ||
3296 (*addr & PDRMASK) == superpage_offset)
3298 if ((*addr & PDRMASK) < superpage_offset)
3299 *addr = (*addr & ~PDRMASK) + superpage_offset;
3301 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset;
3305 DB_SHOW_COMMAND(ptable, ddb_pid_dump)
3308 struct thread *td = NULL;
3315 td = db_lookup_thread(addr, true);
3317 db_printf("Invalid pid or tid");
3321 if (p->p_vmspace == NULL) {
3322 db_printf("No vmspace for process");
3325 pmap = vmspace_pmap(p->p_vmspace);
3329 db_printf("pmap:%p segtab:%p asid:%x generation:%x\n",
3330 pmap, pmap->pm_segtab, pmap->pm_asid[0].asid,
3331 pmap->pm_asid[0].gen);
3332 for (i = 0; i < NPDEPG; i++) {
3337 pdpe = (pd_entry_t *)pmap->pm_segtab[i];
3340 db_printf("[%4d] %p\n", i, pdpe);
3342 for (j = 0; j < NPDEPG; j++) {
3343 pde = (pt_entry_t *)pdpe[j];
3346 db_printf("\t[%4d] %p\n", j, pde);
3350 pde = (pt_entry_t *)pdpe;
3352 for (k = 0; k < NPTEPG; k++) {
3354 if (pte == 0 || !pte_test(&pte, PTE_V))
3356 pa = TLBLO_PTE_TO_PA(pte);
3357 va = ((u_long)i << SEGSHIFT) | (j << PDRSHIFT) | (k << PAGE_SHIFT);
3358 db_printf("\t\t[%04d] va: %p pte: %8jx pa:%jx\n",
3359 k, (void *)va, (uintmax_t)pte, (uintmax_t)pa);
3367 * Allocate TLB address space tag (called ASID or TLBPID) and return it.
3368 * It takes almost as much or more time to search the TLB for a
3369 * specific ASID and flush those entries as it does to flush the entire TLB.
3370 * Therefore, when we allocate a new ASID, we just take the next number. When
3371 * we run out of numbers, we flush the TLB, increment the generation count
3372 * and start over. ASID zero is reserved for kernel use.
3375 pmap_asid_alloc(pmap)
3378 if (pmap->pm_asid[PCPU_GET(cpuid)].asid != PMAP_ASID_RESERVED &&
3379 pmap->pm_asid[PCPU_GET(cpuid)].gen == PCPU_GET(asid_generation));
3381 if (PCPU_GET(next_asid) == pmap_max_asid) {
3382 tlb_invalidate_all_user(NULL);
3383 PCPU_SET(asid_generation,
3384 (PCPU_GET(asid_generation) + 1) & ASIDGEN_MASK);
3385 if (PCPU_GET(asid_generation) == 0) {
3386 PCPU_SET(asid_generation, 1);
3388 PCPU_SET(next_asid, 1); /* 0 means invalid */
3390 pmap->pm_asid[PCPU_GET(cpuid)].asid = PCPU_GET(next_asid);
3391 pmap->pm_asid[PCPU_GET(cpuid)].gen = PCPU_GET(asid_generation);
3392 PCPU_SET(next_asid, PCPU_GET(next_asid) + 1);
3397 init_pte_prot(vm_page_t m, vm_prot_t access, vm_prot_t prot)
3401 if (!(prot & VM_PROT_WRITE))
3402 rw = PTE_V | PTE_RO;
3403 else if ((m->oflags & VPO_UNMANAGED) == 0) {
3404 if ((access & VM_PROT_WRITE) != 0)
3409 /* Needn't emulate a modified bit for unmanaged pages. */
3415 * pmap_emulate_modified : do dirty bit emulation
3417 * On SMP, update just the local TLB, other CPUs will update their
3418 * TLBs from PTE lazily, if they get the exception.
3419 * Returns 0 in case of sucess, 1 if the page is read only and we
3423 pmap_emulate_modified(pmap_t pmap, vm_offset_t va)
3428 pte = pmap_pte(pmap, va);
3430 panic("pmap_emulate_modified: can't find PTE");
3432 /* It is possible that some other CPU changed m-bit */
3433 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D)) {
3434 tlb_update(pmap, va, *pte);
3439 if (!pte_test(pte, PTE_V) || pte_test(pte, PTE_D))
3440 panic("pmap_emulate_modified: invalid pte");
3442 if (pte_test(pte, PTE_RO)) {
3446 pte_set(pte, PTE_D);
3447 tlb_update(pmap, va, *pte);
3448 if (!pte_test(pte, PTE_MANAGED))
3449 panic("pmap_emulate_modified: unmanaged page");
3455 * Routine: pmap_kextract
3457 * Extract the physical page address associated
3461 pmap_kextract(vm_offset_t va)
3466 * First, the direct-mapped regions.
3468 #if defined(__mips_n64)
3469 if (va >= MIPS_XKPHYS_START && va < MIPS_XKPHYS_END)
3470 return (MIPS_XKPHYS_TO_PHYS(va));
3472 if (va >= MIPS_KSEG0_START && va < MIPS_KSEG0_END)
3473 return (MIPS_KSEG0_TO_PHYS(va));
3475 if (va >= MIPS_KSEG1_START && va < MIPS_KSEG1_END)
3476 return (MIPS_KSEG1_TO_PHYS(va));
3479 * User virtual addresses.
3481 if (va < VM_MAXUSER_ADDRESS) {
3484 if (curproc && curproc->p_vmspace) {
3485 ptep = pmap_pte(&curproc->p_vmspace->vm_pmap, va);
3487 return (TLBLO_PTE_TO_PA(*ptep) |
3495 * Should be kernel virtual here, otherwise fail
3497 mapped = (va >= MIPS_KSEG2_START || va < MIPS_KSEG2_END);
3498 #if defined(__mips_n64)
3499 mapped = mapped || (va >= MIPS_XKSEG_START || va < MIPS_XKSEG_END);
3508 /* Is the kernel pmap initialized? */
3509 if (!CPU_EMPTY(&kernel_pmap->pm_active)) {
3510 /* It's inside the virtual address range */
3511 ptep = pmap_pte(kernel_pmap, va);
3513 return (TLBLO_PTE_TO_PA(*ptep) |
3520 panic("%s for unknown address space %p.", __func__, (void *)va);
3525 pmap_flush_pvcache(vm_page_t m)
3530 for (pv = TAILQ_FIRST(&m->md.pv_list); pv;
3531 pv = TAILQ_NEXT(pv, pv_list)) {
3532 mips_dcache_wbinv_range_index(pv->pv_va, PAGE_SIZE);
3538 pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma)
3542 * It appears that this function can only be called before any mappings
3543 * for the page are established. If this ever changes, this code will
3544 * need to walk the pv_list and make each of the existing mappings
3545 * uncacheable, being careful to sync caches and PTEs (and maybe
3546 * invalidate TLB?) for any current mapping it modifies.
3548 if (TAILQ_FIRST(&m->md.pv_list) != NULL)
3549 panic("Can't change memattr on page with existing mappings");
3551 /* Clean memattr portion of pv_flags */
3552 m->md.pv_flags &= ~PV_MEMATTR_MASK;
3553 m->md.pv_flags |= (ma << PV_MEMATTR_SHIFT) & PV_MEMATTR_MASK;
3556 static __inline void
3557 pmap_pte_attr(pt_entry_t *pte, vm_memattr_t ma)
3561 npte = *(u_int *)pte;
3562 npte &= ~PTE_C_MASK;
3568 pmap_change_attr(vm_offset_t sva, vm_size_t size, vm_memattr_t ma)
3570 pd_entry_t *pde, *pdpe;
3572 vm_offset_t ova, eva, va, va_next;
3583 for (; sva < eva; sva = va_next) {
3584 pdpe = pmap_segmap(pmap, sva);
3587 va_next = (sva + NBSEG) & ~SEGMASK;
3593 va_next = (sva + NBPDR) & ~PDRMASK;
3597 pde = pmap_pdpe_to_pde(pdpe, sva);
3602 * Limit our scan to either the end of the va represented
3603 * by the current page table page, or to the end of the
3604 * range being removed.
3610 for (pte = pmap_pde_to_pte(pde, sva); sva != va_next; pte++,
3612 if (!pte_test(pte, PTE_V) || pte_cache_bits(pte) == ma) {
3613 if (va != va_next) {
3614 pmap_invalidate_range(pmap, va, sva);
3622 pmap_pte_attr(pte, ma);
3625 pmap_invalidate_range(pmap, va, sva);
3629 /* Flush caches to be in the safe side */
3630 mips_dcache_wbinv_range(ova, size);
3635 pmap_is_valid_memattr(pmap_t pmap __unused, vm_memattr_t mode)
3639 case VM_MEMATTR_UNCACHEABLE:
3640 case VM_MEMATTR_WRITE_BACK:
3642 case VM_MEMATTR_WRITE_COMBINING: