2 * Copyright (c) 2013 Ed Schouten <ed@FreeBSD.org>
5 * Copyright (c) 1998 Doug Rabson
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/stdatomic.h>
34 #include <sys/types.h>
36 #if defined(__SYNC_ATOMICS)
41 * It turns out __sync_synchronize() does not emit any code when used
42 * with GCC 4.2. Implement our own version that does work reliably.
44 * Although __sync_lock_test_and_set() should only perform an acquire
45 * barrier, make it do a full barrier like the other functions. This
46 * should make <stdatomic.h>'s atomic_exchange_explicit() work reliably.
54 #if !defined(_KERNEL) || defined(SMP)
66 #else /* _KERNEL && !SMP */
68 #endif /* !KERNEL || SMP */
78 * Given a memory address pointing to an 8-bit or 16-bit integer, return
79 * the address of the 32-bit word containing it.
82 static inline uint32_t *
83 round_to_word(void *ptr)
86 return ((uint32_t *)((intptr_t)ptr & ~3));
90 * Utility functions for loading and storing 8-bit and 16-bit integers
91 * in 32-bit words at an offset corresponding with the location of the
96 put_1(reg_t *r, const uint8_t *offset_ptr, uint8_t val)
100 offset = (intptr_t)offset_ptr & 3;
104 static inline uint8_t
105 get_1(const reg_t *r, const uint8_t *offset_ptr)
109 offset = (intptr_t)offset_ptr & 3;
110 return (r->v8[offset]);
114 put_2(reg_t *r, const uint16_t *offset_ptr, uint16_t val)
122 offset = (intptr_t)offset_ptr & 3;
124 r->v8[offset] = bytes.out[0];
125 r->v8[offset + 1] = bytes.out[1];
128 static inline uint16_t
129 get_2(const reg_t *r, const uint16_t *offset_ptr)
137 offset = (intptr_t)offset_ptr & 3;
138 bytes.in[0] = r->v8[offset];
139 bytes.in[1] = r->v8[offset + 1];
144 * 8-bit and 16-bit routines.
146 * These operations are not natively supported by the CPU, so we use
147 * some shifting and bitmasking on top of the 32-bit instructions.
150 #define EMIT_LOCK_TEST_AND_SET_N(N, uintN_t) \
152 __sync_lock_test_and_set_##N(uintN_t *mem, uintN_t val) \
155 reg_t val32, negmask, old; \
158 mem32 = round_to_word(mem); \
159 val32.v32 = 0x00000000; \
160 put_##N(&val32, mem, val); \
161 negmask.v32 = 0xffffffff; \
162 put_##N(&negmask, mem, 0); \
167 "\tll %0, %5\n" /* Load old value. */ \
168 "\tand %2, %4, %0\n" /* Remove the old value. */ \
169 "\tor %2, %3\n" /* Put in the new value. */ \
170 "\tsc %2, %1\n" /* Attempt to store. */ \
171 "\tbeqz %2, 1b\n" /* Spin if failed. */ \
172 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
173 : "r" (val32.v32), "r" (negmask.v32), "m" (*mem32)); \
174 return (get_##N(&old, mem)); \
177 EMIT_LOCK_TEST_AND_SET_N(1, uint8_t)
178 EMIT_LOCK_TEST_AND_SET_N(2, uint16_t)
180 #define EMIT_VAL_COMPARE_AND_SWAP_N(N, uintN_t) \
182 __sync_val_compare_and_swap_##N(uintN_t *mem, uintN_t expected, \
186 reg_t expected32, desired32, posmask, old; \
187 uint32_t negmask, temp; \
189 mem32 = round_to_word(mem); \
190 expected32.v32 = 0x00000000; \
191 put_##N(&expected32, mem, expected); \
192 desired32.v32 = 0x00000000; \
193 put_##N(&desired32, mem, desired); \
194 posmask.v32 = 0x00000000; \
195 put_##N(&posmask, mem, ~0); \
196 negmask = ~posmask.v32; \
201 "\tll %0, %7\n" /* Load old value. */ \
202 "\tand %2, %5, %0\n" /* Isolate the old value. */ \
203 "\tbne %2, %3, 2f\n" /* Compare to expected value. */\
204 "\tand %2, %6, %0\n" /* Remove the old value. */ \
205 "\tor %2, %4\n" /* Put in the new value. */ \
206 "\tsc %2, %1\n" /* Attempt to store. */ \
207 "\tbeqz %2, 1b\n" /* Spin if failed. */ \
209 : "=&r" (old), "=m" (*mem32), "=&r" (temp) \
210 : "r" (expected32.v32), "r" (desired32.v32), \
211 "r" (posmask.v32), "r" (negmask), "m" (*mem32)); \
212 return (get_##N(&old, mem)); \
215 EMIT_VAL_COMPARE_AND_SWAP_N(1, uint8_t)
216 EMIT_VAL_COMPARE_AND_SWAP_N(2, uint16_t)
218 #define EMIT_ARITHMETIC_FETCH_AND_OP_N(N, uintN_t, name, op) \
220 __sync_##name##_##N(uintN_t *mem, uintN_t val) \
223 reg_t val32, posmask, old; \
224 uint32_t negmask, temp1, temp2; \
226 mem32 = round_to_word(mem); \
227 val32.v32 = 0x00000000; \
228 put_##N(&val32, mem, val); \
229 posmask.v32 = 0x00000000; \
230 put_##N(&posmask, mem, ~0); \
231 negmask = ~posmask.v32; \
236 "\tll %0, %7\n" /* Load old value. */ \
237 "\t"op" %2, %0, %4\n" /* Calculate new value. */ \
238 "\tand %2, %5\n" /* Isolate the new value. */ \
239 "\tand %3, %6, %0\n" /* Remove the old value. */ \
240 "\tor %2, %3\n" /* Put in the new value. */ \
241 "\tsc %2, %1\n" /* Attempt to store. */ \
242 "\tbeqz %2, 1b\n" /* Spin if failed. */ \
243 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp1), \
245 : "r" (val32.v32), "r" (posmask.v32), "r" (negmask), \
247 return (get_##N(&old, mem)); \
250 EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_add, "addu")
251 EMIT_ARITHMETIC_FETCH_AND_OP_N(1, uint8_t, fetch_and_sub, "subu")
252 EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_add, "addu")
253 EMIT_ARITHMETIC_FETCH_AND_OP_N(2, uint16_t, fetch_and_sub, "subu")
255 #define EMIT_BITWISE_FETCH_AND_OP_N(N, uintN_t, name, op, idempotence) \
257 __sync_##name##_##N(uintN_t *mem, uintN_t val) \
263 mem32 = round_to_word(mem); \
264 val32.v32 = idempotence ? 0xffffffff : 0x00000000; \
265 put_##N(&val32, mem, val); \
270 "\tll %0, %4\n" /* Load old value. */ \
271 "\t"op" %2, %3, %0\n" /* Calculate new value. */ \
272 "\tsc %2, %1\n" /* Attempt to store. */ \
273 "\tbeqz %2, 1b\n" /* Spin if failed. */ \
274 : "=&r" (old.v32), "=m" (*mem32), "=&r" (temp) \
275 : "r" (val32.v32), "m" (*mem32)); \
276 return (get_##N(&old, mem)); \
279 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_and, "and", 1)
280 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_or, "or", 0)
281 EMIT_BITWISE_FETCH_AND_OP_N(1, uint8_t, fetch_and_xor, "xor", 0)
282 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_and, "and", 1)
283 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_or, "or", 0)
284 EMIT_BITWISE_FETCH_AND_OP_N(2, uint16_t, fetch_and_xor, "xor", 0)
291 __sync_val_compare_and_swap_4(uint32_t *mem, uint32_t expected,
299 "\tll %0, %5\n" /* Load old value. */
300 "\tbne %0, %3, 2f\n" /* Compare to expected value. */
301 "\tmove %2, %4\n" /* Value to store. */
302 "\tsc %2, %1\n" /* Attempt to store. */
303 "\tbeqz %2, 1b\n" /* Spin if failed. */
305 : "=&r" (old), "=m" (*mem), "=&r" (temp)
306 : "r" (expected), "r" (desired), "m" (*mem));
310 #define EMIT_FETCH_AND_OP_4(name, op) \
312 __sync_##name##_4(uint32_t *mem, uint32_t val) \
314 uint32_t old, temp; \
319 "\tll %0, %4\n" /* Load old value. */ \
320 "\t"op"\n" /* Calculate new value. */ \
321 "\tsc %2, %1\n" /* Attempt to store. */ \
322 "\tbeqz %2, 1b\n" /* Spin if failed. */ \
323 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
324 : "r" (val), "m" (*mem)); \
328 EMIT_FETCH_AND_OP_4(lock_test_and_set, "move %2, %3")
329 EMIT_FETCH_AND_OP_4(fetch_and_add, "addu %2, %0, %3")
330 EMIT_FETCH_AND_OP_4(fetch_and_and, "and %2, %0, %3")
331 EMIT_FETCH_AND_OP_4(fetch_and_or, "or %2, %0, %3")
332 EMIT_FETCH_AND_OP_4(fetch_and_sub, "subu %2, %0, %3")
333 EMIT_FETCH_AND_OP_4(fetch_and_xor, "xor %2, %0, %3")
338 * Note: All the 64-bit atomic operations are only atomic when running
339 * in 64-bit mode. It is assumed that code compiled for n32 and n64 fits
340 * into this definition and no further safeties are needed.
343 #if defined(__mips_n32) || defined(__mips_n64)
346 __sync_val_compare_and_swap_8(uint64_t *mem, uint64_t expected,
354 "\tlld %0, %5\n" /* Load old value. */
355 "\tbne %0, %3, 2f\n" /* Compare to expected value. */
356 "\tmove %2, %4\n" /* Value to store. */
357 "\tscd %2, %1\n" /* Attempt to store. */
358 "\tbeqz %2, 1b\n" /* Spin if failed. */
360 : "=&r" (old), "=m" (*mem), "=&r" (temp)
361 : "r" (expected), "r" (desired), "m" (*mem));
365 #define EMIT_FETCH_AND_OP_8(name, op) \
367 __sync_##name##_8(uint64_t *mem, uint64_t val) \
369 uint64_t old, temp; \
374 "\tlld %0, %4\n" /* Load old value. */ \
375 "\t"op"\n" /* Calculate new value. */ \
376 "\tscd %2, %1\n" /* Attempt to store. */ \
377 "\tbeqz %2, 1b\n" /* Spin if failed. */ \
378 : "=&r" (old), "=m" (*mem), "=&r" (temp) \
379 : "r" (val), "m" (*mem)); \
383 EMIT_FETCH_AND_OP_8(lock_test_and_set, "move %2, %3")
384 EMIT_FETCH_AND_OP_8(fetch_and_add, "daddu %2, %0, %3")
385 EMIT_FETCH_AND_OP_8(fetch_and_and, "and %2, %0, %3")
386 EMIT_FETCH_AND_OP_8(fetch_and_or, "or %2, %0, %3")
387 EMIT_FETCH_AND_OP_8(fetch_and_sub, "dsubu %2, %0, %3")
388 EMIT_FETCH_AND_OP_8(fetch_and_xor, "xor %2, %0, %3")
390 #endif /* __mips_n32 || __mips_n64 */
392 #endif /* __SYNC_ATOMICS */