1 /* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
3 * Copyright (c) 1992, 1993
4 * The Regents of the University of California. All rights reserved.
6 * This code is derived from software contributed to Berkeley by
7 * Digital Equipment Corporation and Ralph Campbell.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Copyright (C) 1989 Digital Equipment Corporation.
34 * Permission to use, copy, modify, and distribute this software and
35 * its documentation for any purpose and without fee is hereby granted,
36 * provided that the above copyright notice appears in all copies.
37 * Digital Equipment Corporation makes no representations about the
38 * suitability of this software for any purpose. It is provided "as is"
39 * without express or implied warranty.
41 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
42 * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
43 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
44 * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
45 * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
46 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
48 * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
49 * JNPR: support.S,v 1.5.2.2 2007/08/29 10:03:49 girish
54 * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
55 * All rights reserved.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
65 * 3. All advertising materials mentioning features or use of this software
66 * must display the following acknowledgement:
67 * This product includes software developed by Jonathan R. Stone for
69 * 4. The name of the author may not be used to endorse or promote products
70 * derived from this software without specific prior written permission.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 * Contains assembly language support routines.
90 #include <sys/errno.h>
91 #include <machine/asm.h>
92 #include <machine/cpu.h>
93 #include <machine/regnum.h>
94 #include <machine/cpuregs.h>
95 #include <machine/pcb.h>
99 .set noreorder # Noreorder is default style!
108 * int copystr(void *kfaddr, void *kdaddr, size_t maxlen, size_t *lencopied)
109 * Copy a NIL-terminated string, at most maxlen characters long. Return the
110 * number of characters copied (including the NIL) in *lencopied. If the
111 * string is too long, return ENAMETOOLONG; else return 0.
120 sb v0, 0(a1) # each byte until NIL
122 bne a2, zero, 1b # less than maxlen
125 li v0, ENAMETOOLONG # run out of space
127 beq a3, zero, 3f # return num. of copied bytes
128 PTR_SUBU a2, t0, a2 # if the 4th arg was non-NULL
131 j ra # v0 is 0 or ENAMETOOLONG
137 * Copy a null terminated string from the user address space into
138 * the kernel address space.
140 * copyinstr(fromaddr, toaddr, maxlength, &lencopied)
146 NESTED(copyinstr, CALLFRAME_SIZ, ra)
147 PTR_SUBU sp, sp, CALLFRAME_SIZ
148 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
150 blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space
151 REG_S ra, CALLFRAME_RA(sp)
153 PTR_L v1, PC_CURPCB(v1)
154 jal _C_LABEL(copystr)
155 PTR_S v0, U_PCB_ONFAULT(v1)
156 REG_L ra, CALLFRAME_RA(sp)
158 PTR_L v1, PC_CURPCB(v1)
159 PTR_S zero, U_PCB_ONFAULT(v1)
161 PTR_ADDU sp, sp, CALLFRAME_SIZ
165 * Copy specified amount of data from user space into the kernel
166 * copyin(from, to, len)
167 * caddr_t *from; (user source address)
168 * caddr_t *to; (kernel destination address)
171 NESTED(copyin, CALLFRAME_SIZ, ra)
172 PTR_SUBU sp, sp, CALLFRAME_SIZ
173 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
175 blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space
176 REG_S ra, CALLFRAME_RA(sp)
178 PTR_L v1, PC_CURPCB(v1)
180 PTR_S v0, U_PCB_ONFAULT(v1)
181 REG_L ra, CALLFRAME_RA(sp)
183 PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload
184 PTR_S zero, U_PCB_ONFAULT(v1)
185 PTR_ADDU sp, sp, CALLFRAME_SIZ
191 * Copy specified amount of data from kernel to the user space
192 * copyout(from, to, len)
193 * caddr_t *from; (kernel source address)
194 * caddr_t *to; (user destination address)
197 NESTED(copyout, CALLFRAME_SIZ, ra)
198 PTR_SUBU sp, sp, CALLFRAME_SIZ
199 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
201 blt a1, zero, _C_LABEL(copyerr) # make sure address is in user space
202 REG_S ra, CALLFRAME_RA(sp)
204 PTR_L v1, PC_CURPCB(v1)
206 PTR_S v0, U_PCB_ONFAULT(v1)
207 REG_L ra, CALLFRAME_RA(sp)
209 PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload
210 PTR_S zero, U_PCB_ONFAULT(v1)
211 PTR_ADDU sp, sp, CALLFRAME_SIZ
217 REG_L ra, CALLFRAME_RA(sp)
218 PTR_ADDU sp, sp, CALLFRAME_SIZ
220 li v0, EFAULT # return error
224 * {fu,su},{byte,sword,word}, fetch or store a byte, short or word to
231 blt a0, zero, fswberr # make sure address is in user space
234 PTR_L v1, PC_CURPCB(v1)
235 PTR_S v0, U_PCB_ONFAULT(v1)
236 ld v0, 0(a0) # fetch word
237 PTR_S zero, U_PCB_ONFAULT(v1)
238 sd v0, 0(a1) # store word
249 blt a0, zero, fswberr # make sure address is in user space
252 PTR_L v1, PC_CURPCB(v1)
253 PTR_S v0, U_PCB_ONFAULT(v1)
254 lw v0, 0(a0) # fetch word
255 PTR_S zero, U_PCB_ONFAULT(v1)
256 sw v0, 0(a1) # store word
263 blt a0, zero, fswberr # make sure address is in user space
266 PTR_L v1, PC_CURPCB(v1)
267 PTR_S v0, U_PCB_ONFAULT(v1)
268 lhu v0, 0(a0) # fetch short
269 PTR_S zero, U_PCB_ONFAULT(v1)
270 sh v0, 0(a1) # store short
277 blt a0, zero, fswberr # make sure address is in user space
280 PTR_L v1, PC_CURPCB(v1)
281 PTR_S v0, U_PCB_ONFAULT(v1)
282 lbu v0, 0(a0) # fetch byte
284 PTR_S zero, U_PCB_ONFAULT(v1)
292 blt a0, zero, fswberr # make sure address is in user space
295 PTR_L v1, PC_CURPCB(v1)
296 PTR_S v0, U_PCB_ONFAULT(v1)
297 sw a1, 0(a0) # store word
298 PTR_S zero, U_PCB_ONFAULT(v1)
307 blt a0, zero, fswberr # make sure address is in user space
310 PTR_L v1, PC_CURPCB(v1)
311 PTR_S v0, U_PCB_ONFAULT(v1)
312 sd a1, 0(a0) # store word
313 PTR_S zero, U_PCB_ONFAULT(v1)
321 * <v0>u_long casueword(<a0>u_long *p, <a1>u_long oldval, <a2>u_long *oldval_p,
326 * <v0>uint32_t casueword(<a0>uint32_t *p, <a1>uint32_t oldval,
327 * <a2>uint32_t newval)
334 blt a0, zero, fswberr # make sure address is in user space
337 PTR_L v1, PC_CURPCB(v1)
338 PTR_S v0, U_PCB_ONFAULT(v1)
345 sc t0, 0(a0) # store word
348 PTR_S zero, U_PCB_ONFAULT(v1)
350 sw t1, 0(a2) # unconditionally store old word
357 blt a0, zero, fswberr # make sure address is in user space
360 PTR_L v1, PC_CURPCB(v1)
361 PTR_S v0, U_PCB_ONFAULT(v1)
368 scd t0, 0(a0) # store double word
371 PTR_S zero, U_PCB_ONFAULT(v1)
373 sd t1, 0(a2) # unconditionally store old word
378 * Will have to flush the instruction cache if byte merging is done in hardware.
382 blt a0, zero, fswberr # make sure address is in user space
385 PTR_L v1, PC_CURPCB(v1)
386 PTR_S v0, U_PCB_ONFAULT(v1)
387 sh a1, 0(a0) # store short
388 PTR_S zero, U_PCB_ONFAULT(v1)
395 blt a0, zero, fswberr # make sure address is in user space
398 PTR_L v1, PC_CURPCB(v1)
399 PTR_S v0, U_PCB_ONFAULT(v1)
400 sb a1, 0(a0) # store byte
401 PTR_S zero, U_PCB_ONFAULT(v1)
412 * memset(void *s1, int c, int len)
413 * NetBSD: memset.S,v 1.3 2001/10/16 15:40:53 uch Exp
417 blt a2, 12, memsetsmallclr # small amount to clear?
418 move v0, a0 # save s1 for result
420 sll t1, a1, 8 # compute c << 8 in t1
421 or t1, t1, a1 # compute c << 8 | c in 11
422 sll t2, t1, 16 # shift that left 16
423 or t1, t2, t1 # or together
425 PTR_SUBU t0, zero, a0 # compute # bytes to word align address
427 beq t0, zero, 1f # skip if word aligned
428 PTR_SUBU a2, a2, t0 # subtract from remaining count
429 SWHI t1, 0(a0) # store 1, 2, or 3 bytes to align
432 and v1, a2, 3 # compute number of whole words left
435 PTR_ADDU t0, t0, a0 # compute ending address
437 PTR_ADDU a0, a0, 4 # clear words
438 bne a0, t0, 2b # unrolling loop does not help
439 sw t1, -4(a0) # since we are limited by memory speed
443 PTR_ADDU t0, a2, a0 # compute ending address
445 PTR_ADDU a0, a0, 1 # clear bytes
460 blt a1, 12, smallclr # small amount to clear?
461 PTR_SUBU a3, zero, a0 # compute # bytes to word align address
463 beq a3, zero, 1f # skip if word aligned
464 PTR_SUBU a1, a1, a3 # subtract from remaining count
465 SWHI zero, 0(a0) # clear 1, 2, or 3 bytes to align
468 and v0, a1, 3 # compute number of words left
471 PTR_ADDU a3, a3, a0 # compute ending address
473 PTR_ADDU a0, a0, 4 # clear words
474 bne a0, a3, 2b # unrolling loop does not help
475 sw zero, -4(a0) # since we are limited by memory speed
478 PTR_ADDU a3, a1, a0 # compute ending address
480 PTR_ADDU a0, a0, 1 # clear bytes
494 blt a2, 16, smallcmp # is it worth any trouble?
495 xor v0, a0, a1 # compare low two bits of addresses
497 PTR_SUBU a3, zero, a1 # compute # bytes to word align address
498 bne v0, zero, unalignedcmp # not possible to align addresses
502 PTR_SUBU a2, a2, a3 # subtract from remaining count
503 move v0, v1 # init v0,v1 so unmodified bytes match
504 LWHI v0, 0(a0) # read 1, 2, or 3 bytes
510 and a3, a2, ~3 # compute number of whole words left
511 PTR_SUBU a2, a2, a3 # which has to be >= (16-3) & ~3
512 PTR_ADDU a3, a3, a0 # compute ending address
514 lw v0, 0(a0) # compare words
521 b smallcmp # finish remainder
525 PTR_SUBU a2, a2, a3 # subtract from remaining count
526 PTR_ADDU a3, a3, a0 # compute ending address
528 lbu v0, 0(a0) # compare bytes until a1 word aligned
536 and a3, a2, ~3 # compute number of whole words left
537 PTR_SUBU a2, a2, a3 # which has to be >= (16-3) & ~3
538 PTR_ADDU a3, a3, a0 # compute ending address
540 LWHI v0, 0(a0) # compare words a0 unaligned, a1 aligned
550 PTR_ADDU a3, a2, a0 # compute ending address
576 and v1, a0, 1 # bit set?
578 beq v1, zero, 1b # no, continue
587 * atomic_set_16(u_int16_t *a, u_int16_t b)
594 srl a0, a0, 2 # round down address to be 32-bit aligned
609 * atomic_clear_16(u_int16_t *a, u_int16_t b)
614 LEAF(atomic_clear_16)
616 srl a0, a0, 2 # round down address to be 32-bit aligned
622 andi t1, t1, 0xffff # t1 has the original lower 16 bits
623 and t1, t1, a1 # t1 has the new lower 16 bits
624 srl t0, t0, 16 # preserve original top 16 bits
637 * atomic_subtract_16(uint16_t *a, uint16_t b)
642 LEAF(atomic_subtract_16)
644 srl a0, a0, 2 # round down address to be 32-bit aligned
649 andi t1, t1, 0xffff # t1 has the original lower 16 bits
651 andi t1, t1, 0xffff # t1 has the new lower 16 bits
652 srl t0, t0, 16 # preserve original top 16 bits
660 END(atomic_subtract_16)
664 * atomic_add_16(uint16_t *a, uint16_t b)
671 srl a0, a0, 2 # round down address to be 32-bit aligned
676 andi t1, t1, 0xffff # t1 has the original lower 16 bits
678 andi t1, t1, 0xffff # t1 has the new lower 16 bits
679 srl t0, t0, 16 # preserve original top 16 bits
691 * atomic_add_8(uint8_t *a, uint8_t b)
698 srl a0, a0, 2 # round down address to be 32-bit aligned
703 andi t1, t1, 0xff # t1 has the original lower 8 bits
705 andi t1, t1, 0xff # t1 has the new lower 8 bits
706 srl t0, t0, 8 # preserve original top 24 bits
719 * atomic_subtract_8(uint8_t *a, uint8_t b)
724 LEAF(atomic_subtract_8)
726 srl a0, a0, 2 # round down address to be 32-bit aligned
731 andi t1, t1, 0xff # t1 has the original lower 8 bits
733 andi t1, t1, 0xff # t1 has the new lower 8 bits
734 srl t0, t0, 8 # preserve original top 24 bits
742 END(atomic_subtract_8)
744 .set noreorder # Noreorder is default style!
746 #if defined(DDB) || defined(DEBUG)
750 and v0, a0, 3 # unaligned ?
752 PTR_L t1, PC_CURPCB(t1)
754 PTR_S v1, U_PCB_ONFAULT(t1)
758 PTR_S zero, U_PCB_ONFAULT(t1)
764 PTR_S zero, U_PCB_ONFAULT(t1)
769 and v0, a0, 3 # unaligned ?
771 PTR_L t1, PC_CURPCB(t1)
773 PTR_S v1, U_PCB_ONFAULT(t1)
777 PTR_S zero, U_PCB_ONFAULT(t1)
783 PTR_S zero, U_PCB_ONFAULT(t1)
793 and v0, a0, 3 # unaligned ?
795 PTR_L t1, PC_CURPCB(t1)
797 PTR_S v1, U_PCB_ONFAULT(t1)
801 PTR_S zero, U_PCB_ONFAULT(t1)
807 PTR_S zero, U_PCB_ONFAULT(t1)
815 #endif /* DDB || DEBUG */
819 break MIPS_BREAK_SOVER_VAL
825 mfc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
826 REG_S s0, (SZREG * PCB_REG_S0)(a0)
827 REG_S s1, (SZREG * PCB_REG_S1)(a0)
828 REG_S s2, (SZREG * PCB_REG_S2)(a0)
829 REG_S s3, (SZREG * PCB_REG_S3)(a0)
830 REG_S s4, (SZREG * PCB_REG_S4)(a0)
831 REG_S s5, (SZREG * PCB_REG_S5)(a0)
832 REG_S s6, (SZREG * PCB_REG_S6)(a0)
833 REG_S s7, (SZREG * PCB_REG_S7)(a0)
834 REG_S s8, (SZREG * PCB_REG_S8)(a0)
835 REG_S sp, (SZREG * PCB_REG_SP)(a0)
836 REG_S ra, (SZREG * PCB_REG_RA)(a0)
837 REG_S v0, (SZREG * PCB_REG_SR)(a0)
839 li v0, 0 # setjmp return
843 REG_L v0, (SZREG * PCB_REG_SR)(a0)
844 REG_L ra, (SZREG * PCB_REG_RA)(a0)
845 REG_L s0, (SZREG * PCB_REG_S0)(a0)
846 REG_L s1, (SZREG * PCB_REG_S1)(a0)
847 REG_L s2, (SZREG * PCB_REG_S2)(a0)
848 REG_L s3, (SZREG * PCB_REG_S3)(a0)
849 REG_L s4, (SZREG * PCB_REG_S4)(a0)
850 REG_L s5, (SZREG * PCB_REG_S5)(a0)
851 REG_L s6, (SZREG * PCB_REG_S6)(a0)
852 REG_L s7, (SZREG * PCB_REG_S7)(a0)
853 REG_L s8, (SZREG * PCB_REG_S8)(a0)
854 REG_L sp, (SZREG * PCB_REG_SP)(a0)
855 mtc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
858 li v0, 1 # longjmp return