1 /* $OpenBSD: locore.S,v 1.18 1998/09/15 10:58:53 pefo Exp $ */
3 * Copyright (c) 1992, 1993
4 * The Regents of the University of California. All rights reserved.
6 * This code is derived from software contributed to Berkeley by
7 * Digital Equipment Corporation and Ralph Campbell.
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * Copyright (C) 1989 Digital Equipment Corporation.
34 * Permission to use, copy, modify, and distribute this software and
35 * its documentation for any purpose and without fee is hereby granted,
36 * provided that the above copyright notice appears in all copies.
37 * Digital Equipment Corporation makes no representations about the
38 * suitability of this software for any purpose. It is provided "as is"
39 * without express or implied warranty.
41 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/loMem.s,
42 * v 1.1 89/07/11 17:55:04 nelson Exp SPRITE (DECWRL)
43 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAsm.s,
44 * v 9.2 90/01/29 18:00:39 shirriff Exp SPRITE (DECWRL)
45 * from: Header: /sprite/src/kernel/vm/ds3100.md/vmPmaxAsm.s,
46 * v 1.1 89/07/10 14:27:41 nelson Exp SPRITE (DECWRL)
48 * from: @(#)locore.s 8.5 (Berkeley) 1/4/94
49 * JNPR: support.S,v 1.5.2.2 2007/08/29 10:03:49 girish
54 * Copyright (c) 1997 Jonathan Stone (hereinafter referred to as the author)
55 * All rights reserved.
57 * Redistribution and use in source and binary forms, with or without
58 * modification, are permitted provided that the following conditions
60 * 1. Redistributions of source code must retain the above copyright
61 * notice, this list of conditions and the following disclaimer.
62 * 2. Redistributions in binary form must reproduce the above copyright
63 * notice, this list of conditions and the following disclaimer in the
64 * documentation and/or other materials provided with the distribution.
65 * 3. All advertising materials mentioning features or use of this software
66 * must display the following acknowledgement:
67 * This product includes software developed by Jonathan R. Stone for
69 * 4. The name of the author may not be used to endorse or promote products
70 * derived from this software without specific prior written permission.
72 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
73 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
74 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
75 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
76 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
77 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
78 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
79 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
80 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
81 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
86 * Contains assembly language support routines.
90 #include <sys/errno.h>
91 #include <machine/asm.h>
92 #include <machine/cpu.h>
93 #include <machine/regnum.h>
94 #include <machine/cpuregs.h>
95 #include <machine/pcb.h>
99 .set noreorder # Noreorder is default style!
108 * Copy a null terminated string from the user address space into
109 * the kernel address space.
111 * copyinstr(fromaddr, toaddr, maxlength, &lencopied)
118 PTR_LA v0, __copyinstr_err
119 blt a0, zero, __copyinstr_err # make sure address is in user space
121 PTR_L v1, PC_CURPCB(v1)
122 PTR_S v0, U_PCB_ONFAULT(v1)
130 sb v0, 0(a1) # each byte until NIL
132 bne a2, zero, 1b # less than maxlen
135 li v0, ENAMETOOLONG # run out of space
137 beq a3, zero, 3f # return num. of copied bytes
138 PTR_SUBU a2, t0, a2 # if the 4th arg was non-NULL
142 PTR_S zero, U_PCB_ONFAULT(v1)
152 * Copy specified amount of data from user space into the kernel
153 * copyin(from, to, len)
154 * caddr_t *from; (user source address)
155 * caddr_t *to; (kernel destination address)
158 NESTED(copyin, CALLFRAME_SIZ, ra)
159 PTR_SUBU sp, sp, CALLFRAME_SIZ
160 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
162 blt a0, zero, _C_LABEL(copyerr) # make sure address is in user space
163 REG_S ra, CALLFRAME_RA(sp)
165 PTR_L v1, PC_CURPCB(v1)
167 PTR_S v0, U_PCB_ONFAULT(v1)
168 REG_L ra, CALLFRAME_RA(sp)
170 PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload
171 PTR_S zero, U_PCB_ONFAULT(v1)
172 PTR_ADDU sp, sp, CALLFRAME_SIZ
178 * Copy specified amount of data from kernel to the user space
179 * copyout(from, to, len)
180 * caddr_t *from; (kernel source address)
181 * caddr_t *to; (user destination address)
184 NESTED(copyout, CALLFRAME_SIZ, ra)
185 PTR_SUBU sp, sp, CALLFRAME_SIZ
186 .mask 0x80000000, (CALLFRAME_RA - CALLFRAME_SIZ)
188 blt a1, zero, _C_LABEL(copyerr) # make sure address is in user space
189 REG_S ra, CALLFRAME_RA(sp)
191 PTR_L v1, PC_CURPCB(v1)
193 PTR_S v0, U_PCB_ONFAULT(v1)
194 REG_L ra, CALLFRAME_RA(sp)
196 PTR_L v1, PC_CURPCB(v1) # bcopy modified v1, so reload
197 PTR_S zero, U_PCB_ONFAULT(v1)
198 PTR_ADDU sp, sp, CALLFRAME_SIZ
204 REG_L ra, CALLFRAME_RA(sp)
205 PTR_ADDU sp, sp, CALLFRAME_SIZ
207 li v0, EFAULT # return error
211 * {fu,su},{byte,sword,word}, fetch or store a byte, short or word to
218 blt a0, zero, fswberr # make sure address is in user space
221 PTR_L v1, PC_CURPCB(v1)
222 PTR_S v0, U_PCB_ONFAULT(v1)
223 ld v0, 0(a0) # fetch word
224 PTR_S zero, U_PCB_ONFAULT(v1)
225 sd v0, 0(a1) # store word
236 blt a0, zero, fswberr # make sure address is in user space
239 PTR_L v1, PC_CURPCB(v1)
240 PTR_S v0, U_PCB_ONFAULT(v1)
241 lw v0, 0(a0) # fetch word
242 PTR_S zero, U_PCB_ONFAULT(v1)
243 sw v0, 0(a1) # store word
250 blt a0, zero, fswberr # make sure address is in user space
253 PTR_L v1, PC_CURPCB(v1)
254 PTR_S v0, U_PCB_ONFAULT(v1)
255 lhu v0, 0(a0) # fetch short
256 PTR_S zero, U_PCB_ONFAULT(v1)
257 sh v0, 0(a1) # store short
264 blt a0, zero, fswberr # make sure address is in user space
267 PTR_L v1, PC_CURPCB(v1)
268 PTR_S v0, U_PCB_ONFAULT(v1)
269 lbu v0, 0(a0) # fetch byte
271 PTR_S zero, U_PCB_ONFAULT(v1)
279 blt a0, zero, fswberr # make sure address is in user space
282 PTR_L v1, PC_CURPCB(v1)
283 PTR_S v0, U_PCB_ONFAULT(v1)
284 sw a1, 0(a0) # store word
285 PTR_S zero, U_PCB_ONFAULT(v1)
294 blt a0, zero, fswberr # make sure address is in user space
297 PTR_L v1, PC_CURPCB(v1)
298 PTR_S v0, U_PCB_ONFAULT(v1)
299 sd a1, 0(a0) # store word
300 PTR_S zero, U_PCB_ONFAULT(v1)
308 * <v0>u_long casueword(<a0>u_long *p, <a1>u_long oldval, <a2>u_long *oldval_p,
313 * <v0>uint32_t casueword(<a0>uint32_t *p, <a1>uint32_t oldval,
314 * <a2>uint32_t newval)
321 blt a0, zero, fswberr # make sure address is in user space
324 PTR_L v1, PC_CURPCB(v1)
325 PTR_S v0, U_PCB_ONFAULT(v1)
332 sc t0, 0(a0) # store word
335 PTR_S zero, U_PCB_ONFAULT(v1)
337 sw t1, 0(a2) # unconditionally store old word
344 blt a0, zero, fswberr # make sure address is in user space
347 PTR_L v1, PC_CURPCB(v1)
348 PTR_S v0, U_PCB_ONFAULT(v1)
355 scd t0, 0(a0) # store double word
358 PTR_S zero, U_PCB_ONFAULT(v1)
360 sd t1, 0(a2) # unconditionally store old word
365 * Will have to flush the instruction cache if byte merging is done in hardware.
369 blt a0, zero, fswberr # make sure address is in user space
372 PTR_L v1, PC_CURPCB(v1)
373 PTR_S v0, U_PCB_ONFAULT(v1)
374 sh a1, 0(a0) # store short
375 PTR_S zero, U_PCB_ONFAULT(v1)
382 blt a0, zero, fswberr # make sure address is in user space
385 PTR_L v1, PC_CURPCB(v1)
386 PTR_S v0, U_PCB_ONFAULT(v1)
387 sb a1, 0(a0) # store byte
388 PTR_S zero, U_PCB_ONFAULT(v1)
399 * memset(void *s1, int c, int len)
400 * NetBSD: memset.S,v 1.3 2001/10/16 15:40:53 uch Exp
404 blt a2, 12, memsetsmallclr # small amount to clear?
405 move v0, a0 # save s1 for result
407 sll t1, a1, 8 # compute c << 8 in t1
408 or t1, t1, a1 # compute c << 8 | c in 11
409 sll t2, t1, 16 # shift that left 16
410 or t1, t2, t1 # or together
412 PTR_SUBU t0, zero, a0 # compute # bytes to word align address
414 beq t0, zero, 1f # skip if word aligned
415 PTR_SUBU a2, a2, t0 # subtract from remaining count
416 SWHI t1, 0(a0) # store 1, 2, or 3 bytes to align
419 and v1, a2, 3 # compute number of whole words left
422 PTR_ADDU t0, t0, a0 # compute ending address
424 PTR_ADDU a0, a0, 4 # clear words
425 bne a0, t0, 2b # unrolling loop does not help
426 sw t1, -4(a0) # since we are limited by memory speed
430 PTR_ADDU t0, a2, a0 # compute ending address
432 PTR_ADDU a0, a0, 1 # clear bytes
447 blt a1, 12, smallclr # small amount to clear?
448 PTR_SUBU a3, zero, a0 # compute # bytes to word align address
450 beq a3, zero, 1f # skip if word aligned
451 PTR_SUBU a1, a1, a3 # subtract from remaining count
452 SWHI zero, 0(a0) # clear 1, 2, or 3 bytes to align
455 and v0, a1, 3 # compute number of words left
458 PTR_ADDU a3, a3, a0 # compute ending address
460 PTR_ADDU a0, a0, 4 # clear words
461 bne a0, a3, 2b # unrolling loop does not help
462 sw zero, -4(a0) # since we are limited by memory speed
465 PTR_ADDU a3, a1, a0 # compute ending address
467 PTR_ADDU a0, a0, 1 # clear bytes
481 blt a2, 16, smallcmp # is it worth any trouble?
482 xor v0, a0, a1 # compare low two bits of addresses
484 PTR_SUBU a3, zero, a1 # compute # bytes to word align address
485 bne v0, zero, unalignedcmp # not possible to align addresses
489 PTR_SUBU a2, a2, a3 # subtract from remaining count
490 move v0, v1 # init v0,v1 so unmodified bytes match
491 LWHI v0, 0(a0) # read 1, 2, or 3 bytes
497 and a3, a2, ~3 # compute number of whole words left
498 PTR_SUBU a2, a2, a3 # which has to be >= (16-3) & ~3
499 PTR_ADDU a3, a3, a0 # compute ending address
501 lw v0, 0(a0) # compare words
508 b smallcmp # finish remainder
512 PTR_SUBU a2, a2, a3 # subtract from remaining count
513 PTR_ADDU a3, a3, a0 # compute ending address
515 lbu v0, 0(a0) # compare bytes until a1 word aligned
523 and a3, a2, ~3 # compute number of whole words left
524 PTR_SUBU a2, a2, a3 # which has to be >= (16-3) & ~3
525 PTR_ADDU a3, a3, a0 # compute ending address
527 LWHI v0, 0(a0) # compare words a0 unaligned, a1 aligned
537 PTR_ADDU a3, a2, a0 # compute ending address
563 and v1, a0, 1 # bit set?
565 beq v1, zero, 1b # no, continue
574 * atomic_set_16(u_int16_t *a, u_int16_t b)
581 srl a0, a0, 2 # round down address to be 32-bit aligned
596 * atomic_clear_16(u_int16_t *a, u_int16_t b)
601 LEAF(atomic_clear_16)
603 srl a0, a0, 2 # round down address to be 32-bit aligned
609 andi t1, t1, 0xffff # t1 has the original lower 16 bits
610 and t1, t1, a1 # t1 has the new lower 16 bits
611 srl t0, t0, 16 # preserve original top 16 bits
624 * atomic_subtract_16(uint16_t *a, uint16_t b)
629 LEAF(atomic_subtract_16)
631 srl a0, a0, 2 # round down address to be 32-bit aligned
636 andi t1, t1, 0xffff # t1 has the original lower 16 bits
638 andi t1, t1, 0xffff # t1 has the new lower 16 bits
639 srl t0, t0, 16 # preserve original top 16 bits
647 END(atomic_subtract_16)
651 * atomic_add_16(uint16_t *a, uint16_t b)
658 srl a0, a0, 2 # round down address to be 32-bit aligned
663 andi t1, t1, 0xffff # t1 has the original lower 16 bits
665 andi t1, t1, 0xffff # t1 has the new lower 16 bits
666 srl t0, t0, 16 # preserve original top 16 bits
678 * atomic_add_8(uint8_t *a, uint8_t b)
685 srl a0, a0, 2 # round down address to be 32-bit aligned
690 andi t1, t1, 0xff # t1 has the original lower 8 bits
692 andi t1, t1, 0xff # t1 has the new lower 8 bits
693 srl t0, t0, 8 # preserve original top 24 bits
706 * atomic_subtract_8(uint8_t *a, uint8_t b)
711 LEAF(atomic_subtract_8)
713 srl a0, a0, 2 # round down address to be 32-bit aligned
718 andi t1, t1, 0xff # t1 has the original lower 8 bits
720 andi t1, t1, 0xff # t1 has the new lower 8 bits
721 srl t0, t0, 8 # preserve original top 24 bits
729 END(atomic_subtract_8)
731 .set noreorder # Noreorder is default style!
733 #if defined(DDB) || defined(DEBUG)
737 and v0, a0, 3 # unaligned ?
739 PTR_L t1, PC_CURPCB(t1)
741 PTR_S v1, U_PCB_ONFAULT(t1)
745 PTR_S zero, U_PCB_ONFAULT(t1)
751 PTR_S zero, U_PCB_ONFAULT(t1)
756 and v0, a0, 3 # unaligned ?
758 PTR_L t1, PC_CURPCB(t1)
760 PTR_S v1, U_PCB_ONFAULT(t1)
764 PTR_S zero, U_PCB_ONFAULT(t1)
770 PTR_S zero, U_PCB_ONFAULT(t1)
780 and v0, a0, 3 # unaligned ?
782 PTR_L t1, PC_CURPCB(t1)
784 PTR_S v1, U_PCB_ONFAULT(t1)
788 PTR_S zero, U_PCB_ONFAULT(t1)
794 PTR_S zero, U_PCB_ONFAULT(t1)
802 #endif /* DDB || DEBUG */
806 break MIPS_BREAK_SOVER_VAL
812 mfc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
813 REG_S s0, (SZREG * PCB_REG_S0)(a0)
814 REG_S s1, (SZREG * PCB_REG_S1)(a0)
815 REG_S s2, (SZREG * PCB_REG_S2)(a0)
816 REG_S s3, (SZREG * PCB_REG_S3)(a0)
817 REG_S s4, (SZREG * PCB_REG_S4)(a0)
818 REG_S s5, (SZREG * PCB_REG_S5)(a0)
819 REG_S s6, (SZREG * PCB_REG_S6)(a0)
820 REG_S s7, (SZREG * PCB_REG_S7)(a0)
821 REG_S s8, (SZREG * PCB_REG_S8)(a0)
822 REG_S sp, (SZREG * PCB_REG_SP)(a0)
823 REG_S ra, (SZREG * PCB_REG_RA)(a0)
824 REG_S v0, (SZREG * PCB_REG_SR)(a0)
826 li v0, 0 # setjmp return
830 REG_L v0, (SZREG * PCB_REG_SR)(a0)
831 REG_L ra, (SZREG * PCB_REG_RA)(a0)
832 REG_L s0, (SZREG * PCB_REG_S0)(a0)
833 REG_L s1, (SZREG * PCB_REG_S1)(a0)
834 REG_L s2, (SZREG * PCB_REG_S2)(a0)
835 REG_L s3, (SZREG * PCB_REG_S3)(a0)
836 REG_L s4, (SZREG * PCB_REG_S4)(a0)
837 REG_L s5, (SZREG * PCB_REG_S5)(a0)
838 REG_L s6, (SZREG * PCB_REG_S6)(a0)
839 REG_L s7, (SZREG * PCB_REG_S7)(a0)
840 REG_L s8, (SZREG * PCB_REG_S8)(a0)
841 REG_L sp, (SZREG * PCB_REG_SP)(a0)
842 mtc0 v0, MIPS_COP_0_STATUS # Later the "real" spl value!
845 li v0, 1 # longjmp return