2 * Copyright (c) 2006-2007 Bruce M. Simpson.
3 * Copyright (c) 2003-2004 Juli Mallett.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 * Simple driver for the 32-bit interval counter built in to all
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include <sys/param.h>
37 #include <sys/systm.h>
38 #include <sys/sysctl.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
43 #include <sys/power.h>
46 #include <sys/timeet.h>
47 #include <sys/timetc.h>
49 #include <machine/hwfunc.h>
50 #include <machine/clock.h>
51 #include <machine/locore.h>
52 #include <machine/md_var.h>
54 uint64_t counter_freq;
56 struct timecounter *platform_timecounter;
58 static DPCPU_DEFINE(uint32_t, cycles_per_tick);
59 static uint32_t cycles_per_usec;
61 static DPCPU_DEFINE(volatile uint32_t, counter_upper);
62 static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
63 static DPCPU_DEFINE(uint32_t, compare_ticks);
64 static DPCPU_DEFINE(uint32_t, lost_ticks);
68 struct resource *intr_res;
70 struct timecounter tc;
73 static struct clock_softc *softc;
78 static int clock_probe(device_t);
79 static void clock_identify(driver_t *, device_t);
80 static int clock_attach(device_t);
81 static unsigned counter_get_timecount(struct timecounter *tc);
84 mips_timer_early_init(uint64_t clock_hz)
86 /* Initialize clock early so that we can use DELAY sooner */
87 counter_freq = clock_hz;
88 cycles_per_usec = (clock_hz / (1000 * 1000));
92 platform_initclocks(void)
95 if (platform_timecounter != NULL)
96 tc_init(platform_timecounter);
104 uint32_t t_lower_last, t_upper;
107 * Disable preemption because we are working with cpu specific data.
112 * Note that even though preemption is disabled, interrupts are
113 * still enabled. In particular there is a race with clock_intr()
114 * reading the values of 'counter_upper' and 'counter_lower_last'.
116 * XXX this depends on clock_intr() being executed periodically
117 * so that 'counter_upper' and 'counter_lower_last' are not stale.
120 t_upper = DPCPU_GET(counter_upper);
121 t_lower_last = DPCPU_GET(counter_lower_last);
122 } while (t_upper != DPCPU_GET(counter_upper));
124 ticktock = mips_rd_count();
128 /* COUNT register wrapped around */
129 if (ticktock < t_lower_last)
132 ret = ((uint64_t)t_upper << 32) | ticktock;
137 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
141 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
142 * function should be called before cninit.
144 counter_freq = platform_counter_freq;
146 * XXX: Some MIPS32 cores update the Count register only every two
148 * We know this because of status registers in CP0, make it automatic.
150 if (double_count != 0)
153 cycles_per_usec = counter_freq / (1 * 1000 * 1000);
154 set_cputicker(tick_ticker, counter_freq, 1);
158 sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
166 error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
167 if (error == 0 && req->newptr != NULL) {
169 softc->et.et_frequency = counter_freq;
170 softc->tc.tc_frequency = counter_freq;
175 SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
176 NULL, 0, sysctl_machdep_counter_freq, "QU",
177 "Timecounter frequency in Hz");
180 counter_get_timecount(struct timecounter *tc)
183 return (mips_rd_count());
187 * Wait for about n microseconds (at least!).
192 uint32_t cur, last, delta, usecs;
195 * This works by polling the timer and counting the number of
196 * microseconds that go by.
198 last = mips_rd_count();
202 cur = mips_rd_count();
204 /* Check to see if the timer has wrapped around. */
206 delta += cur + (0xffffffff - last) + 1;
212 if (delta >= cycles_per_usec) {
213 usecs += delta / cycles_per_usec;
214 delta %= cycles_per_usec;
220 clock_start(struct eventtimer *et,
221 struct bintime *first, struct bintime *period)
223 uint32_t fdiv, div, next;
225 if (period != NULL) {
226 div = (et->et_frequency * (period->frac >> 32)) >> 32;
227 if (period->sec != 0)
228 div += et->et_frequency * period->sec;
232 fdiv = (et->et_frequency * (first->frac >> 32)) >> 32;
234 fdiv += et->et_frequency * first->sec;
237 DPCPU_SET(cycles_per_tick, div);
238 next = mips_rd_count() + fdiv;
239 DPCPU_SET(compare_ticks, next);
240 mips_wr_compare(next);
245 clock_stop(struct eventtimer *et)
248 DPCPU_SET(cycles_per_tick, 0);
249 mips_wr_compare(0xffffffff);
254 * Device section of file below
257 clock_intr(void *arg)
259 struct clock_softc *sc = (struct clock_softc *)arg;
260 uint32_t cycles_per_tick;
261 uint32_t count, compare_last, compare_next, lost_ticks;
263 cycles_per_tick = DPCPU_GET(cycles_per_tick);
265 * Set next clock edge.
267 count = mips_rd_count();
268 compare_last = DPCPU_GET(compare_ticks);
269 if (cycles_per_tick > 0) {
270 compare_next = count + cycles_per_tick;
271 DPCPU_SET(compare_ticks, compare_next);
272 mips_wr_compare(compare_next);
273 } else /* In one-shot mode timer should be stopped after the event. */
274 mips_wr_compare(0xffffffff);
276 /* COUNT register wrapped around */
277 if (count < DPCPU_GET(counter_lower_last)) {
278 DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
280 DPCPU_SET(counter_lower_last, count);
282 if (cycles_per_tick > 0) {
285 * Account for the "lost time" between when the timer interrupt
286 * fired and when 'clock_intr' actually started executing.
288 lost_ticks = DPCPU_GET(lost_ticks);
289 lost_ticks += count - compare_last;
292 * If the COUNT and COMPARE registers are no longer in sync
293 * then make up some reasonable value for the 'lost_ticks'.
295 * This could happen, for e.g., after we resume normal
296 * operations after exiting the debugger.
298 if (lost_ticks > 2 * cycles_per_tick)
299 lost_ticks = cycles_per_tick;
301 while (lost_ticks >= cycles_per_tick) {
302 if (sc->et.et_active)
303 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
304 lost_ticks -= cycles_per_tick;
306 DPCPU_SET(lost_ticks, lost_ticks);
308 if (sc->et.et_active)
309 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
310 return (FILTER_HANDLED);
314 clock_probe(device_t dev)
317 if (device_get_unit(dev) != 0)
318 panic("can't attach more clocks");
320 device_set_desc(dev, "Generic MIPS32 ticker");
325 clock_identify(driver_t * drv, device_t parent)
328 BUS_ADD_CHILD(parent, 0, "clock", 0);
332 clock_attach(device_t dev)
334 struct clock_softc *sc;
337 softc = sc = device_get_softc(dev);
339 sc->intr_res = bus_alloc_resource(dev,
340 SYS_RES_IRQ, &sc->intr_rid, 5, 5, 1, RF_ACTIVE);
341 if (sc->intr_res == NULL) {
342 device_printf(dev, "failed to allocate irq\n");
345 error = bus_setup_intr(dev, sc->intr_res, INTR_TYPE_CLK,
346 clock_intr, NULL, sc, &sc->intr_handler);
348 device_printf(dev, "bus_setup_intr returned %d\n", error);
352 sc->tc.tc_get_timecount = counter_get_timecount;
353 sc->tc.tc_counter_mask = 0xffffffff;
354 sc->tc.tc_frequency = counter_freq;
355 sc->tc.tc_name = "MIPS32";
356 sc->tc.tc_quality = 800;
359 sc->et.et_name = "MIPS32";
360 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
362 sc->et.et_quality = 800;
363 sc->et.et_frequency = counter_freq;
364 sc->et.et_min_period.sec = 0;
365 sc->et.et_min_period.frac = 0x00004000LLU << 32; /* To be safe. */
366 sc->et.et_max_period.sec = 0xfffffffeU / sc->et.et_frequency;
367 sc->et.et_max_period.frac =
368 ((0xfffffffeLLU << 32) / sc->et.et_frequency) << 32;
369 sc->et.et_start = clock_start;
370 sc->et.et_stop = clock_stop;
372 et_register(&sc->et);
376 static device_method_t clock_methods[] = {
377 /* Device interface */
378 DEVMETHOD(device_probe, clock_probe),
379 DEVMETHOD(device_identify, clock_identify),
380 DEVMETHOD(device_attach, clock_attach),
381 DEVMETHOD(device_detach, bus_generic_detach),
382 DEVMETHOD(device_shutdown, bus_generic_shutdown),
387 static driver_t clock_driver = {
390 sizeof(struct clock_softc),
393 static devclass_t clock_devclass;
395 DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);