1 /* $OpenBSD: trap.c,v 1.19 1998/09/30 12:40:41 pefo Exp $ */
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 4. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: Utah Hdr: trap.c 1.32 91/04/06
38 * from: @(#)trap.c 8.5 (Berkeley) 1/11/94
39 * JNPR: trap.c,v 1.13.2.2 2007/08/29 10:03:49 girish
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include "opt_compat.h"
46 #include "opt_global.h"
47 #include "opt_ktrace.h"
48 #include "opt_kdtrace.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/sysent.h>
54 #include <sys/kernel.h>
55 #include <sys/signalvar.h>
56 #include <sys/syscall.h>
59 #include <vm/vm_extern.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_page.h>
62 #include <vm/vm_map.h>
63 #include <vm/vm_param.h>
64 #include <sys/vmmeter.h>
65 #include <sys/ptrace.h>
68 #include <sys/vnode.h>
69 #include <sys/pioctl.h>
70 #include <sys/sysctl.h>
71 #include <sys/syslog.h>
74 #include <sys/ktrace.h>
76 #include <net/netisr.h>
78 #include <machine/trap.h>
79 #include <machine/cpu.h>
80 #include <machine/pte.h>
81 #include <machine/pmap.h>
82 #include <machine/md_var.h>
83 #include <machine/mips_opcode.h>
84 #include <machine/frame.h>
85 #include <machine/regnum.h>
86 #include <machine/tls.h>
89 #include <machine/db_machdep.h>
90 #include <ddb/db_sym.h>
96 #include <sys/dtrace_bsd.h>
101 SYSCTL_INT(_machdep, OID_AUTO, trap_debug, CTLFLAG_RW,
102 &trap_debug, 0, "Debug information on all traps");
105 #define lbu_macro(data, addr) \
106 __asm __volatile ("lbu %0, 0x0(%1)" \
107 : "=r" (data) /* outputs */ \
108 : "r" (addr)); /* inputs */
110 #define lb_macro(data, addr) \
111 __asm __volatile ("lb %0, 0x0(%1)" \
112 : "=r" (data) /* outputs */ \
113 : "r" (addr)); /* inputs */
115 #define lwl_macro(data, addr) \
116 __asm __volatile ("lwl %0, 0x0(%1)" \
117 : "=r" (data) /* outputs */ \
118 : "r" (addr)); /* inputs */
120 #define lwr_macro(data, addr) \
121 __asm __volatile ("lwr %0, 0x0(%1)" \
122 : "=r" (data) /* outputs */ \
123 : "r" (addr)); /* inputs */
125 #define ldl_macro(data, addr) \
126 __asm __volatile ("ldl %0, 0x0(%1)" \
127 : "=r" (data) /* outputs */ \
128 : "r" (addr)); /* inputs */
130 #define ldr_macro(data, addr) \
131 __asm __volatile ("ldr %0, 0x0(%1)" \
132 : "=r" (data) /* outputs */ \
133 : "r" (addr)); /* inputs */
135 #define sb_macro(data, addr) \
136 __asm __volatile ("sb %0, 0x0(%1)" \
138 : "r" (data), "r" (addr)); /* inputs */
140 #define swl_macro(data, addr) \
141 __asm __volatile ("swl %0, 0x0(%1)" \
143 : "r" (data), "r" (addr)); /* inputs */
145 #define swr_macro(data, addr) \
146 __asm __volatile ("swr %0, 0x0(%1)" \
148 : "r" (data), "r" (addr)); /* inputs */
150 #define sdl_macro(data, addr) \
151 __asm __volatile ("sdl %0, 0x0(%1)" \
153 : "r" (data), "r" (addr)); /* inputs */
155 #define sdr_macro(data, addr) \
156 __asm __volatile ("sdr %0, 0x0(%1)" \
158 : "r" (data), "r" (addr)); /* inputs */
160 static void log_illegal_instruction(const char *, struct trapframe *);
161 static void log_bad_page_fault(char *, struct trapframe *, int);
162 static void log_frame_dump(struct trapframe *frame);
163 static void get_mapping_info(vm_offset_t, pd_entry_t **, pt_entry_t **);
166 static void trap_frame_dump(struct trapframe *frame);
169 void (*machExceptionTable[]) (void)= {
171 * The kernel exception handlers.
173 MipsKernIntr, /* external interrupt */
174 MipsKernGenException, /* TLB modification */
175 MipsTLBInvalidException,/* TLB miss (load or instr. fetch) */
176 MipsTLBInvalidException,/* TLB miss (store) */
177 MipsKernGenException, /* address error (load or I-fetch) */
178 MipsKernGenException, /* address error (store) */
179 MipsKernGenException, /* bus error (I-fetch) */
180 MipsKernGenException, /* bus error (load or store) */
181 MipsKernGenException, /* system call */
182 MipsKernGenException, /* breakpoint */
183 MipsKernGenException, /* reserved instruction */
184 MipsKernGenException, /* coprocessor unusable */
185 MipsKernGenException, /* arithmetic overflow */
186 MipsKernGenException, /* trap exception */
187 MipsKernGenException, /* virtual coherence exception inst */
188 MipsKernGenException, /* floating point exception */
189 MipsKernGenException, /* reserved */
190 MipsKernGenException, /* reserved */
191 MipsKernGenException, /* reserved */
192 MipsKernGenException, /* reserved */
193 MipsKernGenException, /* reserved */
194 MipsKernGenException, /* reserved */
195 MipsKernGenException, /* reserved */
196 MipsKernGenException, /* watch exception */
197 MipsKernGenException, /* reserved */
198 MipsKernGenException, /* reserved */
199 MipsKernGenException, /* reserved */
200 MipsKernGenException, /* reserved */
201 MipsKernGenException, /* reserved */
202 MipsKernGenException, /* reserved */
203 MipsKernGenException, /* reserved */
204 MipsKernGenException, /* virtual coherence exception data */
206 * The user exception handlers.
208 MipsUserIntr, /* 0 */
209 MipsUserGenException, /* 1 */
210 MipsTLBInvalidException,/* 2 */
211 MipsTLBInvalidException,/* 3 */
212 MipsUserGenException, /* 4 */
213 MipsUserGenException, /* 5 */
214 MipsUserGenException, /* 6 */
215 MipsUserGenException, /* 7 */
216 MipsUserGenException, /* 8 */
217 MipsUserGenException, /* 9 */
218 MipsUserGenException, /* 10 */
219 MipsUserGenException, /* 11 */
220 MipsUserGenException, /* 12 */
221 MipsUserGenException, /* 13 */
222 MipsUserGenException, /* 14 */
223 MipsUserGenException, /* 15 */
224 MipsUserGenException, /* 16 */
225 MipsUserGenException, /* 17 */
226 MipsUserGenException, /* 18 */
227 MipsUserGenException, /* 19 */
228 MipsUserGenException, /* 20 */
229 MipsUserGenException, /* 21 */
230 MipsUserGenException, /* 22 */
231 MipsUserGenException, /* 23 */
232 MipsUserGenException, /* 24 */
233 MipsUserGenException, /* 25 */
234 MipsUserGenException, /* 26 */
235 MipsUserGenException, /* 27 */
236 MipsUserGenException, /* 28 */
237 MipsUserGenException, /* 29 */
238 MipsUserGenException, /* 20 */
239 MipsUserGenException, /* 31 */
242 char *trap_type[] = {
243 "external interrupt",
245 "TLB miss (load or instr. fetch)",
247 "address error (load or I-fetch)",
248 "address error (store)",
249 "bus error (I-fetch)",
250 "bus error (load or store)",
253 "reserved instruction",
254 "coprocessor unusable",
255 "arithmetic overflow",
257 "virtual coherency instruction",
274 "virtual coherency data",
277 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
278 struct trapdebug trapdebug[TRAPSIZE], *trp = trapdebug;
281 #if defined(DDB) || defined(DEBUG)
282 void stacktrace(struct trapframe *);
283 void logstacktrace(struct trapframe *);
286 #define KERNLAND(x) ((vm_offset_t)(x) >= VM_MIN_KERNEL_ADDRESS && (vm_offset_t)(x) < VM_MAX_KERNEL_ADDRESS)
287 #define DELAYBRANCH(x) ((int)(x) < 0)
290 * MIPS load/store access type
303 char *access_name[] = {
304 "Load Halfword Unsigned",
306 "Load Word Unsigned",
315 #include <machine/octeon_cop2.h>
318 static int allow_unaligned_acc = 1;
320 SYSCTL_INT(_vm, OID_AUTO, allow_unaligned_acc, CTLFLAG_RW,
321 &allow_unaligned_acc, 0, "Allow unaligned accesses");
324 * FP emulation is assumed to work on O32, but the code is outdated and crufty
325 * enough that it's a more sensible default to have it disabled when using
326 * other ABIs. At the very least, it needs a lot of help in using
327 * type-semantic ABI-oblivious macros for everything it does.
329 #if defined(__mips_o32)
330 static int emulate_fp = 1;
332 static int emulate_fp = 0;
334 SYSCTL_INT(_machdep, OID_AUTO, emulate_fp, CTLFLAG_RW,
335 &emulate_fp, 0, "Emulate unimplemented FPU instructions");
337 static int emulate_unaligned_access(struct trapframe *frame, int mode);
339 extern void fswintrberr(void); /* XXX */
342 cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
344 struct trapframe *locr0 = td->td_frame;
345 struct sysentvec *se;
348 bzero(sa->args, sizeof(sa->args));
350 /* compute next PC after syscall instruction */
351 td->td_pcb->pcb_tpc = sa->trapframe->pc; /* Remember if restart */
352 if (DELAYBRANCH(sa->trapframe->cause)) /* Check BD bit */
353 locr0->pc = MipsEmulateBranch(locr0, sa->trapframe->pc, 0, 0);
355 locr0->pc += sizeof(int);
356 sa->code = locr0->v0;
362 * This is an indirect syscall, in which the code is the first argument.
364 #if (!defined(__mips_n32) && !defined(__mips_n64)) || defined(COMPAT_FREEBSD32)
365 if (sa->code == SYS___syscall && SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
367 * Like syscall, but code is a quad, so as to maintain alignment
368 * for the rest of the arguments.
370 if (_QUAD_LOWWORD == 0)
371 sa->code = locr0->a0;
373 sa->code = locr0->a1;
374 sa->args[0] = locr0->a2;
375 sa->args[1] = locr0->a3;
381 * This is either not a quad syscall, or is a quad syscall with a
382 * new ABI in which quads fit in a single register.
384 sa->code = locr0->a0;
385 sa->args[0] = locr0->a1;
386 sa->args[1] = locr0->a2;
387 sa->args[2] = locr0->a3;
389 #if defined(__mips_n32) || defined(__mips_n64)
390 #ifdef COMPAT_FREEBSD32
391 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
394 * Non-o32 ABIs support more arguments in registers.
396 sa->args[3] = locr0->a4;
397 sa->args[4] = locr0->a5;
398 sa->args[5] = locr0->a6;
399 sa->args[6] = locr0->a7;
401 #ifdef COMPAT_FREEBSD32
408 * A direct syscall, arguments are just parameters to the syscall.
410 sa->args[0] = locr0->a0;
411 sa->args[1] = locr0->a1;
412 sa->args[2] = locr0->a2;
413 sa->args[3] = locr0->a3;
415 #if defined (__mips_n32) || defined(__mips_n64)
416 #ifdef COMPAT_FREEBSD32
417 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
420 * Non-o32 ABIs support more arguments in registers.
422 sa->args[4] = locr0->a4;
423 sa->args[5] = locr0->a5;
424 sa->args[6] = locr0->a6;
425 sa->args[7] = locr0->a7;
427 #ifdef COMPAT_FREEBSD32
436 printf("SYSCALL #%d pid:%u\n", sa->code, td->td_proc->p_pid);
439 se = td->td_proc->p_sysent;
442 * Shouldn't this go before switching on the code?
445 sa->code &= se->sv_mask;
447 if (sa->code >= se->sv_size)
448 sa->callp = &se->sv_table[0];
450 sa->callp = &se->sv_table[sa->code];
452 sa->narg = sa->callp->sy_narg;
454 if (sa->narg > nsaved) {
455 #if defined(__mips_n32) || defined(__mips_n64)
458 * Is this right for new ABIs? I think the 4 there
459 * should be 8, size there are 8 registers to skip,
460 * not 4, but I'm not certain.
462 #ifdef COMPAT_FREEBSD32
463 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32))
465 printf("SYSCALL #%u pid:%u, narg (%u) > nsaved (%u).\n",
466 sa->code, td->td_proc->p_pid, sa->narg, nsaved);
468 #if (defined(__mips_n32) || defined(__mips_n64)) && defined(COMPAT_FREEBSD32)
469 if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
473 error = 0; /* XXX GCC is awful. */
474 for (i = nsaved; i < sa->narg; i++) {
475 error = copyin((caddr_t)(intptr_t)(locr0->sp +
476 (4 + (i - nsaved)) * sizeof(int32_t)),
477 (caddr_t)&arg, sizeof arg);
484 error = copyin((caddr_t)(intptr_t)(locr0->sp +
485 4 * sizeof(register_t)), (caddr_t)&sa->args[nsaved],
486 (u_int)(sa->narg - nsaved) * sizeof(register_t));
495 td->td_retval[0] = 0;
496 td->td_retval[1] = locr0->v1;
504 #include "../../kern/subr_syscall.c"
507 * Handle an exception.
508 * Called from MipsKernGenException() or MipsUserGenException()
509 * when a processor trap occurs.
510 * In the case of a kernel trap, we return the pc where to resume if
511 * p->p_addr->u_pcb.pcb_onfault is set, otherwise, return old pc.
514 trap(struct trapframe *trapframe)
519 struct thread *td = curthread;
520 struct proc *p = curproc;
529 register_t *frame_regs;
531 trapdebug_enter(trapframe, 0);
533 type = (trapframe->cause & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
534 if (TRAPF_USERMODE(trapframe)) {
542 * Enable hardware interrupts if they were on before the trap. If it
543 * was off disable all so we don't accidently enable it when doing a
544 * return to userland.
546 if (trapframe->sr & MIPS_SR_INT_IE) {
547 set_intr_mask(trapframe->sr & MIPS_SR_INT_MASK);
555 static vm_offset_t last_badvaddr = 0;
556 static vm_offset_t this_badvaddr = 0;
557 static int count = 0;
560 printf("trap type %x (%s - ", type,
561 trap_type[type & (~T_USER)]);
564 printf("user mode)\n");
566 printf("kernel mode)\n");
569 printf("cpuid = %d\n", PCPU_GET(cpuid));
571 pid = mips_rd_entryhi() & TLBHI_ASID_MASK;
572 printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n",
573 (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
574 (intmax_t)trapframe->sp, (intmax_t)trapframe->sr,
575 (curproc ? curproc->p_pid : -1), pid);
577 switch (type & ~T_USER) {
583 this_badvaddr = trapframe->badvaddr;
586 this_badvaddr = trapframe->ra;
589 this_badvaddr = trapframe->pc;
592 if ((last_badvaddr == this_badvaddr) &&
593 ((type & ~T_USER) != T_SYSCALL)) {
595 trap_frame_dump(trapframe);
596 panic("too many faults at %p\n", (void *)last_badvaddr);
599 last_badvaddr = this_badvaddr;
607 * A trap can occur while DTrace executes a probe. Before
608 * executing the probe, DTrace blocks re-scheduling and sets
609 * a flag in it's per-cpu flags to indicate that it doesn't
610 * want to fault. On returning from the probe, the no-fault
611 * flag is cleared and finally re-scheduling is enabled.
613 * If the DTrace kernel module has registered a trap handler,
614 * call it and if it returns non-zero, assume that it has
615 * handled the trap and modified the trap frame so that this
616 * function can return normally.
619 * XXXDTRACE: add pid probe handler here (if ever)
622 if (dtrace_trap_func != NULL && (*dtrace_trap_func)(trapframe, type))
623 return (trapframe->pc);
630 kdb_trap(type, 0, trapframe);
635 /* check for kernel address */
636 if (KERNLAND(trapframe->badvaddr)) {
637 if (pmap_emulate_modified(kernel_pmap,
638 trapframe->badvaddr) != 0) {
639 ftype = VM_PROT_WRITE;
642 return (trapframe->pc);
646 case T_TLB_MOD + T_USER:
647 pmap = &p->p_vmspace->vm_pmap;
648 if (pmap_emulate_modified(pmap, trapframe->badvaddr) != 0) {
649 ftype = VM_PROT_WRITE;
653 return (trapframe->pc);
658 ftype = (type == T_TLB_ST_MISS) ? VM_PROT_WRITE : VM_PROT_READ;
659 /* check for kernel address */
660 if (KERNLAND(trapframe->badvaddr)) {
665 va = trunc_page((vm_offset_t)trapframe->badvaddr);
666 rv = vm_fault(kernel_map, va, ftype, VM_FAULT_NORMAL);
667 if (rv == KERN_SUCCESS)
668 return (trapframe->pc);
669 if (td->td_pcb->pcb_onfault != NULL) {
670 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
671 td->td_pcb->pcb_onfault = NULL;
678 * It is an error for the kernel to access user space except
679 * through the copyin/copyout routines.
681 if (td->td_pcb->pcb_onfault == NULL)
684 /* check for fuswintr() or suswintr() getting a page fault */
685 /* XXX There must be a nicer way to do this. */
686 if (td->td_pcb->pcb_onfault == fswintrberr) {
687 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
688 td->td_pcb->pcb_onfault = NULL;
694 case T_TLB_LD_MISS + T_USER:
695 ftype = VM_PROT_READ;
698 case T_TLB_ST_MISS + T_USER:
699 ftype = VM_PROT_WRITE;
709 va = trunc_page((vm_offset_t)trapframe->badvaddr);
710 if (KERNLAND(trapframe->badvaddr)) {
712 * Don't allow user-mode faults in kernel
719 * Keep swapout from messing with us during this
726 rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
732 * XXXDTRACE: add dtrace_doubletrap_func here?
735 printf("vm_fault(%p (pmap %p), %p (%p), %x, %d) -> %x at pc %p\n",
736 map, &vm->vm_pmap, (void *)va, (void *)(intptr_t)trapframe->badvaddr,
737 ftype, VM_FAULT_NORMAL, rv, (void *)(intptr_t)trapframe->pc);
740 if (rv == KERN_SUCCESS) {
742 return (trapframe->pc);
748 if (td->td_pcb->pcb_onfault != NULL) {
749 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
750 td->td_pcb->pcb_onfault = NULL;
756 i = ((rv == KERN_PROTECTION_FAILURE) ? SIGBUS : SIGSEGV);
757 addr = trapframe->pc;
759 msg = "BAD_PAGE_FAULT";
760 log_bad_page_fault(msg, trapframe, type);
765 case T_ADDR_ERR_LD + T_USER: /* misaligned or kseg access */
766 case T_ADDR_ERR_ST + T_USER: /* misaligned or kseg access */
767 if (trapframe->badvaddr < 0 ||
768 trapframe->badvaddr >= VM_MAXUSER_ADDRESS) {
769 msg = "ADDRESS_SPACE_ERR";
770 } else if (allow_unaligned_acc) {
773 if (type == (T_ADDR_ERR_LD + T_USER))
776 mode = VM_PROT_WRITE;
778 access_type = emulate_unaligned_access(trapframe, mode);
779 if (access_type != 0)
781 msg = "ALIGNMENT_FIX_ERR";
788 case T_BUS_ERR_IFETCH + T_USER: /* BERR asserted to cpu */
789 case T_BUS_ERR_LD_ST + T_USER: /* BERR asserted to cpu */
790 ucode = 0; /* XXX should be VM_PROT_something */
792 addr = trapframe->pc;
795 log_bad_page_fault(msg, trapframe, type);
798 case T_SYSCALL + T_USER:
800 struct syscall_args sa;
803 sa.trapframe = trapframe;
804 error = syscallenter(td, &sa);
806 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
807 if (trp == trapdebug)
808 trapdebug[TRAPSIZE - 1].code = sa.code;
810 trp[-1].code = sa.code;
812 trapdebug_enter(td->td_frame, -sa.code);
815 * The sync'ing of I & D caches for SYS_ptrace() is
816 * done by procfs_domem() through procfs_rwmem()
817 * instead of being done here under a special check
820 syscallret(td, error, &sa);
821 return (trapframe->pc);
826 kdb_trap(type, 0, trapframe);
827 return (trapframe->pc);
830 case T_BREAK + T_USER:
835 /* compute address of break instruction */
837 if (DELAYBRANCH(trapframe->cause))
840 /* read break instruction */
841 instr = fuword32((caddr_t)va);
843 printf("trap: %s (%d) breakpoint %x at %x: (adr %x ins %x)\n",
844 p->p_comm, p->p_pid, instr, trapframe->pc,
845 p->p_md.md_ss_addr, p->p_md.md_ss_instr); /* XXX */
847 if (td->td_md.md_ss_addr != va ||
848 instr != MIPS_BREAK_SSTEP) {
850 addr = trapframe->pc;
854 * The restoration of the original instruction and
855 * the clearing of the berakpoint will be done later
856 * by the call to ptrace_clear_single_step() in
857 * issignal() when SIGTRAP is processed.
859 addr = trapframe->pc;
864 case T_IWATCH + T_USER:
865 case T_DWATCH + T_USER:
869 /* compute address of trapped instruction */
871 if (DELAYBRANCH(trapframe->cause))
873 printf("watch exception @ %p\n", (void *)va);
879 case T_TRAP + T_USER:
883 struct trapframe *locr0 = td->td_frame;
885 /* compute address of trap instruction */
887 if (DELAYBRANCH(trapframe->cause))
889 /* read break instruction */
890 instr = fuword32((caddr_t)va);
892 if (DELAYBRANCH(trapframe->cause)) { /* Check BD bit */
893 locr0->pc = MipsEmulateBranch(locr0, trapframe->pc, 0,
896 locr0->pc += sizeof(int);
899 i = SIGEMT; /* Stuff it with something for now */
903 case T_RES_INST + T_USER:
906 inst = *(InstFmt *)(intptr_t)trapframe->pc;
907 switch (inst.RType.op) {
909 switch (inst.RType.func) {
911 /* Register 29 used for TLS */
912 if (inst.RType.rd == 29) {
913 frame_regs = &(trapframe->zero);
914 frame_regs[inst.RType.rt] = (register_t)(intptr_t)td->td_md.md_tls;
915 #if defined(__mips_n64) && defined(COMPAT_FREEBSD32)
916 if (SV_PROC_FLAG(td->td_proc, SV_ILP32))
917 frame_regs[inst.RType.rt] += TLS_TP_OFFSET + TLS_TCB_SIZE32;
920 frame_regs[inst.RType.rt] += TLS_TP_OFFSET + TLS_TCB_SIZE;
921 trapframe->pc += sizeof(int);
929 log_illegal_instruction("RES_INST", trapframe);
931 addr = trapframe->pc;
940 cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
941 /* Handle only COP2 exception */
945 addr = trapframe->pc;
946 /* save userland cop2 context if it has been touched */
947 if ((td->td_md.md_flags & MDTD_COP2USED) &&
948 (td->td_md.md_cop2owner == COP2_OWNER_USERLAND)) {
949 if (td->td_md.md_ucop2)
950 octeon_cop2_save(td->td_md.md_ucop2);
952 panic("COP2 was used in user mode but md_ucop2 is NULL");
955 if (td->td_md.md_cop2 == NULL) {
956 td->td_md.md_cop2 = octeon_cop2_alloc_ctx();
957 if (td->td_md.md_cop2 == NULL)
958 panic("Failed to allocate COP2 context");
959 memset(td->td_md.md_cop2, 0, sizeof(*td->td_md.md_cop2));
962 octeon_cop2_restore(td->td_md.md_cop2);
964 /* Make userland re-request its context */
965 td->td_frame->sr &= ~MIPS_SR_COP_2_BIT;
966 td->td_md.md_flags |= MDTD_COP2USED;
967 td->td_md.md_cop2owner = COP2_OWNER_KERNEL;
968 /* Enable COP2, it will be disabled in cpu_switch */
969 mips_wr_status(mips_rd_status() | MIPS_SR_COP_2_BIT);
970 return (trapframe->pc);
976 case T_COP_UNUSABLE + T_USER:
977 cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
979 #if !defined(CPU_HAVEFPU)
980 /* FP (COP1) instruction */
981 log_illegal_instruction("COP1_UNUSABLE", trapframe);
985 addr = trapframe->pc;
986 MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame);
987 PCPU_SET(fpcurthread, td);
988 td->td_frame->sr |= MIPS_SR_COP_1_BIT;
989 td->td_md.md_flags |= MDTD_FPUSED;
995 addr = trapframe->pc;
996 if ((td->td_md.md_flags & MDTD_COP2USED) &&
997 (td->td_md.md_cop2owner == COP2_OWNER_KERNEL)) {
998 if (td->td_md.md_cop2)
999 octeon_cop2_save(td->td_md.md_cop2);
1001 panic("COP2 was used in kernel mode but md_cop2 is NULL");
1004 if (td->td_md.md_ucop2 == NULL) {
1005 td->td_md.md_ucop2 = octeon_cop2_alloc_ctx();
1006 if (td->td_md.md_ucop2 == NULL)
1007 panic("Failed to allocate userland COP2 context");
1008 memset(td->td_md.md_ucop2, 0, sizeof(*td->td_md.md_ucop2));
1011 octeon_cop2_restore(td->td_md.md_ucop2);
1013 td->td_frame->sr |= MIPS_SR_COP_2_BIT;
1014 td->td_md.md_flags |= MDTD_COP2USED;
1015 td->td_md.md_cop2owner = COP2_OWNER_USERLAND;
1020 log_illegal_instruction("COPn_UNUSABLE", trapframe);
1021 i = SIGILL; /* only FPU instructions allowed */
1026 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
1029 printf("FPU Trap: PC %#jx CR %x SR %x\n",
1030 (intmax_t)trapframe->pc, (unsigned)trapframe->cause, (unsigned)trapframe->sr);
1034 case T_FPE + T_USER:
1037 addr = trapframe->pc;
1040 MipsFPTrap(trapframe->sr, trapframe->cause, trapframe->pc);
1043 case T_OVFLOW + T_USER:
1045 addr = trapframe->pc;
1048 case T_ADDR_ERR_LD: /* misaligned access */
1049 case T_ADDR_ERR_ST: /* misaligned access */
1052 printf("+++ ADDR_ERR: type = %d, badvaddr = %#jx\n", type,
1053 (intmax_t)trapframe->badvaddr);
1056 /* Only allow emulation on a user address */
1057 if (allow_unaligned_acc &&
1058 ((vm_offset_t)trapframe->badvaddr < VM_MAXUSER_ADDRESS)) {
1061 if (type == T_ADDR_ERR_LD)
1062 mode = VM_PROT_READ;
1064 mode = VM_PROT_WRITE;
1066 access_type = emulate_unaligned_access(trapframe, mode);
1067 if (access_type != 0)
1068 return (trapframe->pc);
1072 case T_BUS_ERR_LD_ST: /* BERR asserted to cpu */
1073 if (td->td_pcb->pcb_onfault != NULL) {
1074 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
1075 td->td_pcb->pcb_onfault = NULL;
1084 #if !defined(SMP) && defined(DEBUG)
1085 stacktrace(!usermode ? trapframe : td->td_frame);
1089 printf("cpu:%d-", PCPU_GET(cpuid));
1091 printf("Trap cause = %d (%s - ", type,
1092 trap_type[type & (~T_USER)]);
1095 printf("user mode)\n");
1097 printf("kernel mode)\n");
1101 printf("badvaddr = %#jx, pc = %#jx, ra = %#jx, sr = %#jxx\n",
1102 (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
1103 (intmax_t)trapframe->sr);
1107 if (debugger_on_panic || kdb_active) {
1108 kdb_trap(type, 0, trapframe);
1113 td->td_frame->pc = trapframe->pc;
1114 td->td_frame->cause = trapframe->cause;
1115 td->td_frame->badvaddr = trapframe->badvaddr;
1116 ksiginfo_init_trap(&ksi);
1118 ksi.ksi_code = ucode;
1119 ksi.ksi_addr = (void *)addr;
1120 ksi.ksi_trapno = type;
1121 trapsignal(td, &ksi);
1125 * Note: we should only get here if returning to user mode.
1127 userret(td, trapframe);
1128 return (trapframe->pc);
1131 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
1139 printf("trapDump(%s)\n", msg);
1140 for (i = 0; i < TRAPSIZE; i++) {
1141 if (trp == trapdebug) {
1142 trp = &trapdebug[TRAPSIZE - 1];
1147 if (trp->cause == 0)
1150 printf("%s: ADR %jx PC %jx CR %jx SR %jx\n",
1151 trap_type[(trp->cause & MIPS_CR_EXC_CODE) >>
1152 MIPS_CR_EXC_CODE_SHIFT],
1153 (intmax_t)trp->vadr, (intmax_t)trp->pc,
1154 (intmax_t)trp->cause, (intmax_t)trp->status);
1156 printf(" RA %jx SP %jx code %d\n", (intmax_t)trp->ra,
1157 (intmax_t)trp->sp, (int)trp->code);
1165 * Return the resulting PC as if the branch was executed.
1168 MipsEmulateBranch(struct trapframe *framePtr, uintptr_t instPC, int fpcCSR,
1172 register_t *regsPtr = (register_t *) framePtr;
1173 uintptr_t retAddr = 0;
1176 #define GetBranchDest(InstPtr, inst) \
1177 (InstPtr + 4 + ((short)inst.IType.imm << 2))
1181 if (instptr < MIPS_KSEG0_START)
1182 inst.word = fuword32((void *)instptr);
1184 inst = *(InstFmt *) instptr;
1186 if ((vm_offset_t)instPC < MIPS_KSEG0_START)
1187 inst.word = fuword32((void *)instPC);
1189 inst = *(InstFmt *) instPC;
1192 switch ((int)inst.JType.op) {
1194 switch ((int)inst.RType.func) {
1197 retAddr = regsPtr[inst.RType.rs];
1201 retAddr = instPC + 4;
1207 switch ((int)inst.IType.rt) {
1212 if ((int)(regsPtr[inst.RType.rs]) < 0)
1213 retAddr = GetBranchDest(instPC, inst);
1215 retAddr = instPC + 8;
1222 if ((int)(regsPtr[inst.RType.rs]) >= 0)
1223 retAddr = GetBranchDest(instPC, inst);
1225 retAddr = instPC + 8;
1234 retAddr = instPC + 4; /* Like syscall... */
1238 panic("MipsEmulateBranch: Bad branch cond");
1244 retAddr = (inst.JType.target << 2) |
1245 ((unsigned)(instPC + 4) & 0xF0000000);
1250 if (regsPtr[inst.RType.rs] == regsPtr[inst.RType.rt])
1251 retAddr = GetBranchDest(instPC, inst);
1253 retAddr = instPC + 8;
1258 if (regsPtr[inst.RType.rs] != regsPtr[inst.RType.rt])
1259 retAddr = GetBranchDest(instPC, inst);
1261 retAddr = instPC + 8;
1266 if ((int)(regsPtr[inst.RType.rs]) <= 0)
1267 retAddr = GetBranchDest(instPC, inst);
1269 retAddr = instPC + 8;
1274 if ((int)(regsPtr[inst.RType.rs]) > 0)
1275 retAddr = GetBranchDest(instPC, inst);
1277 retAddr = instPC + 8;
1281 switch (inst.RType.rs) {
1284 if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)
1285 condition = fpcCSR & MIPS_FPU_COND_BIT;
1287 condition = !(fpcCSR & MIPS_FPU_COND_BIT);
1289 retAddr = GetBranchDest(instPC, inst);
1291 retAddr = instPC + 8;
1295 retAddr = instPC + 4;
1300 retAddr = instPC + 4;
1306 #if defined(DDB) || defined(DEBUG)
1308 * Print a stack backtrace.
1311 stacktrace(struct trapframe *regs)
1313 stacktrace_subr(regs->pc, regs->sp, regs->ra, printf);
1318 log_frame_dump(struct trapframe *frame)
1320 log(LOG_ERR, "Trapframe Register Dump:\n");
1321 log(LOG_ERR, "\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
1322 (intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
1324 log(LOG_ERR, "\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
1325 (intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
1327 #if defined(__mips_n32) || defined(__mips_n64)
1328 log(LOG_ERR, "\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta6: %#jx\n",
1329 (intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
1331 log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1332 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1334 log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1335 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1337 log(LOG_ERR, "\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
1338 (intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
1340 log(LOG_ERR, "\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
1341 (intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
1343 log(LOG_ERR, "\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
1344 (intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
1346 log(LOG_ERR, "\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
1347 (intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
1349 log(LOG_ERR, "\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
1350 (intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
1352 log(LOG_ERR, "\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
1353 (intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
1356 log(LOG_ERR, "\tcause: %#jx\tpc: %#jx\tic: %#jx\n",
1357 (intmax_t)frame->cause, (intmax_t)frame->pc, (intmax_t)frame->ic);
1359 log(LOG_ERR, "\tcause: %#jx\tpc: %#jx\n",
1360 (intmax_t)frame->cause, (intmax_t)frame->pc);
1366 trap_frame_dump(struct trapframe *frame)
1368 printf("Trapframe Register Dump:\n");
1369 printf("\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
1370 (intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
1372 printf("\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
1373 (intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
1374 #if defined(__mips_n32) || defined(__mips_n64)
1375 printf("\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta7: %#jx\n",
1376 (intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
1378 printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1379 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1381 printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1382 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1384 printf("\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
1385 (intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
1387 printf("\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
1388 (intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
1390 printf("\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
1391 (intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
1393 printf("\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
1394 (intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
1396 printf("\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
1397 (intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
1399 printf("\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
1400 (intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
1403 printf("\tcause: %#jx\tpc: %#jx\tic: %#jx\n",
1404 (intmax_t)frame->cause, (intmax_t)frame->pc, (intmax_t)frame->ic);
1406 printf("\tcause: %#jx\tpc: %#jx\n",
1407 (intmax_t)frame->cause, (intmax_t)frame->pc);
1415 get_mapping_info(vm_offset_t va, pd_entry_t **pdepp, pt_entry_t **ptepp)
1419 struct proc *p = curproc;
1421 pdep = (&(p->p_vmspace->vm_pmap.pm_segtab[(va >> SEGSHIFT) & (NPDEPG - 1)]));
1423 ptep = pmap_pte(&p->p_vmspace->vm_pmap, va);
1425 ptep = (pt_entry_t *)0;
1432 log_illegal_instruction(const char *msg, struct trapframe *frame)
1445 printf("cpuid = %d\n", PCPU_GET(cpuid));
1447 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1448 log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx ra %#jx\n",
1449 msg, p->p_pid, (long)td->td_tid, p->p_comm,
1450 p->p_ucred ? p->p_ucred->cr_uid : -1,
1452 (intmax_t)frame->ra);
1454 /* log registers in trap frame */
1455 log_frame_dump(frame);
1457 get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
1460 * Dump a few words around faulting instruction, if the addres is
1464 useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
1465 /* dump page table entry for faulting instruction */
1466 log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
1467 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1469 addr = (unsigned int *)(intptr_t)pc;
1470 log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
1472 log(LOG_ERR, "%08x %08x %08x %08x\n",
1473 addr[0], addr[1], addr[2], addr[3]);
1475 log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
1476 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1481 log_bad_page_fault(char *msg, struct trapframe *frame, int trap_type)
1488 char *read_or_write;
1491 trap_type &= ~T_USER;
1497 printf("cpuid = %d\n", PCPU_GET(cpuid));
1499 switch (trap_type) {
1503 read_or_write = "write";
1507 case T_BUS_ERR_IFETCH:
1508 read_or_write = "read";
1511 read_or_write = "unknown";
1514 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1515 log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx got a %s fault "
1516 "(type %#x) at %#jx\n",
1517 msg, p->p_pid, (long)td->td_tid, p->p_comm,
1518 p->p_ucred ? p->p_ucred->cr_uid : -1,
1522 (intmax_t)frame->badvaddr);
1524 /* log registers in trap frame */
1525 log_frame_dump(frame);
1527 get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
1530 * Dump a few words around faulting instruction, if the addres is
1533 if (!(pc & 3) && (pc != frame->badvaddr) &&
1534 (trap_type != T_BUS_ERR_IFETCH) &&
1535 useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
1536 /* dump page table entry for faulting instruction */
1537 log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
1538 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1540 addr = (unsigned int *)(intptr_t)pc;
1541 log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
1543 log(LOG_ERR, "%08x %08x %08x %08x\n",
1544 addr[0], addr[1], addr[2], addr[3]);
1546 log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
1547 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1550 get_mapping_info((vm_offset_t)frame->badvaddr, &pdep, &ptep);
1551 log(LOG_ERR, "Page table info for bad address %#jx: pde = %p, pte = %#jx\n",
1552 (intmax_t)frame->badvaddr, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1557 * Unaligned load/store emulation
1560 mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, register_t pc)
1562 register_t *reg = (register_t *) frame;
1563 u_int32_t inst = *((u_int32_t *)(intptr_t)pc);
1564 register_t value_msb, value;
1568 * ADDR_ERR faults have higher priority than TLB
1569 * Miss faults. Therefore, it is necessary to
1570 * verify that the faulting address is a valid
1571 * virtual address within the process' address space
1572 * before trying to emulate the unaligned access.
1574 switch (MIPS_INST_OPCODE(inst)) {
1575 case OP_LHU: case OP_LH:
1579 case OP_LWU: case OP_LW:
1588 printf("%s: unhandled opcode in address error: %#x\n", __func__, MIPS_INST_OPCODE(inst));
1592 if (!useracc((void *)((vm_offset_t)addr & ~(size - 1)), size * 2, mode))
1597 * Handle LL/SC LLD/SCD.
1599 switch (MIPS_INST_OPCODE(inst)) {
1601 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1602 lbu_macro(value_msb, addr);
1604 lbu_macro(value, addr);
1605 value |= value_msb << 8;
1606 reg[MIPS_INST_RT(inst)] = value;
1607 return (MIPS_LHU_ACCESS);
1610 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1611 lb_macro(value_msb, addr);
1613 lbu_macro(value, addr);
1614 value |= value_msb << 8;
1615 reg[MIPS_INST_RT(inst)] = value;
1616 return (MIPS_LH_ACCESS);
1619 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1620 lwl_macro(value, addr);
1622 lwr_macro(value, addr);
1623 value &= 0xffffffff;
1624 reg[MIPS_INST_RT(inst)] = value;
1625 return (MIPS_LWU_ACCESS);
1628 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1629 lwl_macro(value, addr);
1631 lwr_macro(value, addr);
1632 reg[MIPS_INST_RT(inst)] = value;
1633 return (MIPS_LW_ACCESS);
1635 #if defined(__mips_n32) || defined(__mips_n64)
1637 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1638 ldl_macro(value, addr);
1640 ldr_macro(value, addr);
1641 reg[MIPS_INST_RT(inst)] = value;
1642 return (MIPS_LD_ACCESS);
1646 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1647 value = reg[MIPS_INST_RT(inst)];
1648 value_msb = value >> 8;
1649 sb_macro(value_msb, addr);
1651 sb_macro(value, addr);
1652 return (MIPS_SH_ACCESS);
1655 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1656 value = reg[MIPS_INST_RT(inst)];
1657 swl_macro(value, addr);
1659 swr_macro(value, addr);
1660 return (MIPS_SW_ACCESS);
1662 #if defined(__mips_n32) || defined(__mips_n64)
1664 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1665 value = reg[MIPS_INST_RT(inst)];
1666 sdl_macro(value, addr);
1668 sdr_macro(value, addr);
1669 return (MIPS_SD_ACCESS);
1672 panic("%s: should not be reached.", __func__);
1677 emulate_unaligned_access(struct trapframe *frame, int mode)
1680 int access_type = 0;
1682 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1685 * Fall through if it's instruction fetch exception
1687 if (!((pc & 3) || (pc == frame->badvaddr))) {
1690 * Handle unaligned load and store
1694 * Return access type if the instruction was emulated.
1695 * Otherwise restore pc and fall through.
1697 access_type = mips_unaligned_load_store(frame,
1698 mode, frame->badvaddr, pc);
1701 if (DELAYBRANCH(frame->cause))
1702 frame->pc = MipsEmulateBranch(frame, frame->pc,
1707 log(LOG_INFO, "Unaligned %s: pc=%#jx, badvaddr=%#jx\n",
1708 access_name[access_type - 1], (intmax_t)pc,
1709 (intmax_t)frame->badvaddr);