1 /* $OpenBSD: trap.c,v 1.19 1998/09/30 12:40:41 pefo Exp $ */
4 * SPDX-License-Identifier: BSD-3-Clause
6 * Copyright (c) 1988 University of Utah.
7 * Copyright (c) 1992, 1993
8 * The Regents of the University of California. All rights reserved.
10 * This code is derived from software contributed to Berkeley by
11 * the Systems Programming Group of the University of Utah Computer
12 * Science Department and Ralph Campbell.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 3. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * from: Utah Hdr: trap.c 1.32 91/04/06
40 * from: @(#)trap.c 8.5 (Berkeley) 1/11/94
41 * JNPR: trap.c,v 1.13.2.2 2007/08/29 10:03:49 girish
43 #include <sys/cdefs.h>
44 __FBSDID("$FreeBSD$");
46 #include "opt_compat.h"
48 #include "opt_ktrace.h"
50 #include <sys/param.h>
51 #include <sys/systm.h>
52 #include <sys/sysent.h>
54 #include <sys/kernel.h>
55 #include <sys/signalvar.h>
56 #include <sys/syscall.h>
59 #include <vm/vm_extern.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_page.h>
62 #include <vm/vm_map.h>
63 #include <vm/vm_param.h>
64 #include <sys/vmmeter.h>
65 #include <sys/ptrace.h>
68 #include <sys/vnode.h>
69 #include <sys/pioctl.h>
70 #include <sys/sysctl.h>
71 #include <sys/syslog.h>
74 #include <sys/ktrace.h>
76 #include <net/netisr.h>
78 #include <machine/trap.h>
79 #include <machine/cpu.h>
80 #include <machine/cpuinfo.h>
81 #include <machine/pte.h>
82 #include <machine/pmap.h>
83 #include <machine/md_var.h>
84 #include <machine/mips_opcode.h>
85 #include <machine/frame.h>
86 #include <machine/regnum.h>
87 #include <machine/tls.h>
90 #include <machine/db_machdep.h>
91 #include <ddb/db_sym.h>
97 #include <sys/dtrace_bsd.h>
102 SYSCTL_INT(_machdep, OID_AUTO, trap_debug, CTLFLAG_RW,
103 &trap_debug, 0, "Debug information on all traps");
106 #define lbu_macro(data, addr) \
107 __asm __volatile ("lbu %0, 0x0(%1)" \
108 : "=r" (data) /* outputs */ \
109 : "r" (addr)); /* inputs */
111 #define lb_macro(data, addr) \
112 __asm __volatile ("lb %0, 0x0(%1)" \
113 : "=r" (data) /* outputs */ \
114 : "r" (addr)); /* inputs */
116 #define lwl_macro(data, addr) \
117 __asm __volatile ("lwl %0, 0x0(%1)" \
118 : "=r" (data) /* outputs */ \
119 : "r" (addr)); /* inputs */
121 #define lwr_macro(data, addr) \
122 __asm __volatile ("lwr %0, 0x0(%1)" \
123 : "=r" (data) /* outputs */ \
124 : "r" (addr)); /* inputs */
126 #define ldl_macro(data, addr) \
127 __asm __volatile ("ldl %0, 0x0(%1)" \
128 : "=r" (data) /* outputs */ \
129 : "r" (addr)); /* inputs */
131 #define ldr_macro(data, addr) \
132 __asm __volatile ("ldr %0, 0x0(%1)" \
133 : "=r" (data) /* outputs */ \
134 : "r" (addr)); /* inputs */
136 #define sb_macro(data, addr) \
137 __asm __volatile ("sb %0, 0x0(%1)" \
139 : "r" (data), "r" (addr)); /* inputs */
141 #define swl_macro(data, addr) \
142 __asm __volatile ("swl %0, 0x0(%1)" \
144 : "r" (data), "r" (addr)); /* inputs */
146 #define swr_macro(data, addr) \
147 __asm __volatile ("swr %0, 0x0(%1)" \
149 : "r" (data), "r" (addr)); /* inputs */
151 #define sdl_macro(data, addr) \
152 __asm __volatile ("sdl %0, 0x0(%1)" \
154 : "r" (data), "r" (addr)); /* inputs */
156 #define sdr_macro(data, addr) \
157 __asm __volatile ("sdr %0, 0x0(%1)" \
159 : "r" (data), "r" (addr)); /* inputs */
161 static void log_illegal_instruction(const char *, struct trapframe *);
162 static void log_bad_page_fault(char *, struct trapframe *, int);
163 static void log_frame_dump(struct trapframe *frame);
164 static void get_mapping_info(vm_offset_t, pd_entry_t **, pt_entry_t **);
166 int (*dtrace_invop_jump_addr)(struct trapframe *);
169 static void trap_frame_dump(struct trapframe *frame);
172 void (*machExceptionTable[]) (void)= {
174 * The kernel exception handlers.
176 MipsKernIntr, /* external interrupt */
177 MipsKernGenException, /* TLB modification */
178 MipsTLBInvalidException,/* TLB miss (load or instr. fetch) */
179 MipsTLBInvalidException,/* TLB miss (store) */
180 MipsKernGenException, /* address error (load or I-fetch) */
181 MipsKernGenException, /* address error (store) */
182 MipsKernGenException, /* bus error (I-fetch) */
183 MipsKernGenException, /* bus error (load or store) */
184 MipsKernGenException, /* system call */
185 MipsKernGenException, /* breakpoint */
186 MipsKernGenException, /* reserved instruction */
187 MipsKernGenException, /* coprocessor unusable */
188 MipsKernGenException, /* arithmetic overflow */
189 MipsKernGenException, /* trap exception */
190 MipsKernGenException, /* virtual coherence exception inst */
191 MipsKernGenException, /* floating point exception */
192 MipsKernGenException, /* reserved */
193 MipsKernGenException, /* reserved */
194 MipsKernGenException, /* reserved */
195 MipsKernGenException, /* reserved */
196 MipsKernGenException, /* reserved */
197 MipsKernGenException, /* reserved */
198 MipsKernGenException, /* reserved */
199 MipsKernGenException, /* watch exception */
200 MipsKernGenException, /* reserved */
201 MipsKernGenException, /* reserved */
202 MipsKernGenException, /* reserved */
203 MipsKernGenException, /* reserved */
204 MipsKernGenException, /* reserved */
205 MipsKernGenException, /* reserved */
206 MipsKernGenException, /* reserved */
207 MipsKernGenException, /* virtual coherence exception data */
209 * The user exception handlers.
211 MipsUserIntr, /* 0 */
212 MipsUserGenException, /* 1 */
213 MipsTLBInvalidException,/* 2 */
214 MipsTLBInvalidException,/* 3 */
215 MipsUserGenException, /* 4 */
216 MipsUserGenException, /* 5 */
217 MipsUserGenException, /* 6 */
218 MipsUserGenException, /* 7 */
219 MipsUserGenException, /* 8 */
220 MipsUserGenException, /* 9 */
221 MipsUserGenException, /* 10 */
222 MipsUserGenException, /* 11 */
223 MipsUserGenException, /* 12 */
224 MipsUserGenException, /* 13 */
225 MipsUserGenException, /* 14 */
226 MipsUserGenException, /* 15 */
227 MipsUserGenException, /* 16 */
228 MipsUserGenException, /* 17 */
229 MipsUserGenException, /* 18 */
230 MipsUserGenException, /* 19 */
231 MipsUserGenException, /* 20 */
232 MipsUserGenException, /* 21 */
233 MipsUserGenException, /* 22 */
234 MipsUserGenException, /* 23 */
235 MipsUserGenException, /* 24 */
236 MipsUserGenException, /* 25 */
237 MipsUserGenException, /* 26 */
238 MipsUserGenException, /* 27 */
239 MipsUserGenException, /* 28 */
240 MipsUserGenException, /* 29 */
241 MipsUserGenException, /* 20 */
242 MipsUserGenException, /* 31 */
245 char *trap_type[] = {
246 "external interrupt",
248 "TLB miss (load or instr. fetch)",
250 "address error (load or I-fetch)",
251 "address error (store)",
252 "bus error (I-fetch)",
253 "bus error (load or store)",
256 "reserved instruction",
257 "coprocessor unusable",
258 "arithmetic overflow",
260 "virtual coherency instruction",
277 "virtual coherency data",
280 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
281 struct trapdebug trapdebug[TRAPSIZE], *trp = trapdebug;
284 #define KERNLAND(x) ((vm_offset_t)(x) >= VM_MIN_KERNEL_ADDRESS && (vm_offset_t)(x) < VM_MAX_KERNEL_ADDRESS)
285 #define DELAYBRANCH(x) ((int)(x) < 0)
288 * MIPS load/store access type
301 char *access_name[] = {
302 "Load Halfword Unsigned",
304 "Load Word Unsigned",
313 #include <machine/octeon_cop2.h>
316 static int allow_unaligned_acc = 1;
318 SYSCTL_INT(_vm, OID_AUTO, allow_unaligned_acc, CTLFLAG_RW,
319 &allow_unaligned_acc, 0, "Allow unaligned accesses");
322 * FP emulation is assumed to work on O32, but the code is outdated and crufty
323 * enough that it's a more sensible default to have it disabled when using
324 * other ABIs. At the very least, it needs a lot of help in using
325 * type-semantic ABI-oblivious macros for everything it does.
327 #if defined(__mips_o32)
328 static int emulate_fp = 1;
330 static int emulate_fp = 0;
332 SYSCTL_INT(_machdep, OID_AUTO, emulate_fp, CTLFLAG_RW,
333 &emulate_fp, 0, "Emulate unimplemented FPU instructions");
335 static int emulate_unaligned_access(struct trapframe *frame, int mode);
337 extern void fswintrberr(void); /* XXX */
340 cpu_fetch_syscall_args(struct thread *td)
342 struct trapframe *locr0;
343 struct sysentvec *se;
344 struct syscall_args *sa;
347 locr0 = td->td_frame;
350 bzero(sa->args, sizeof(sa->args));
352 /* compute next PC after syscall instruction */
353 td->td_pcb->pcb_tpc = sa->trapframe->pc; /* Remember if restart */
354 if (DELAYBRANCH(sa->trapframe->cause)) /* Check BD bit */
355 locr0->pc = MipsEmulateBranch(locr0, sa->trapframe->pc, 0, 0);
357 locr0->pc += sizeof(int);
358 sa->code = locr0->v0;
364 * This is an indirect syscall, in which the code is the first argument.
366 #if (!defined(__mips_n32) && !defined(__mips_n64)) || defined(COMPAT_FREEBSD32)
367 if (sa->code == SYS___syscall && SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
369 * Like syscall, but code is a quad, so as to maintain alignment
370 * for the rest of the arguments.
372 if (_QUAD_LOWWORD == 0)
373 sa->code = locr0->a0;
375 sa->code = locr0->a1;
376 sa->args[0] = locr0->a2;
377 sa->args[1] = locr0->a3;
383 * This is either not a quad syscall, or is a quad syscall with a
384 * new ABI in which quads fit in a single register.
386 sa->code = locr0->a0;
387 sa->args[0] = locr0->a1;
388 sa->args[1] = locr0->a2;
389 sa->args[2] = locr0->a3;
391 #if defined(__mips_n32) || defined(__mips_n64)
392 #ifdef COMPAT_FREEBSD32
393 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
396 * Non-o32 ABIs support more arguments in registers.
398 sa->args[3] = locr0->a4;
399 sa->args[4] = locr0->a5;
400 sa->args[5] = locr0->a6;
401 sa->args[6] = locr0->a7;
403 #ifdef COMPAT_FREEBSD32
410 * A direct syscall, arguments are just parameters to the syscall.
412 sa->args[0] = locr0->a0;
413 sa->args[1] = locr0->a1;
414 sa->args[2] = locr0->a2;
415 sa->args[3] = locr0->a3;
417 #if defined (__mips_n32) || defined(__mips_n64)
418 #ifdef COMPAT_FREEBSD32
419 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
422 * Non-o32 ABIs support more arguments in registers.
424 sa->args[4] = locr0->a4;
425 sa->args[5] = locr0->a5;
426 sa->args[6] = locr0->a6;
427 sa->args[7] = locr0->a7;
429 #ifdef COMPAT_FREEBSD32
438 printf("SYSCALL #%d pid:%u\n", sa->code, td->td_proc->p_pid);
441 se = td->td_proc->p_sysent;
444 * Shouldn't this go before switching on the code?
447 sa->code &= se->sv_mask;
449 if (sa->code >= se->sv_size)
450 sa->callp = &se->sv_table[0];
452 sa->callp = &se->sv_table[sa->code];
454 sa->narg = sa->callp->sy_narg;
456 if (sa->narg > nsaved) {
457 #if defined(__mips_n32) || defined(__mips_n64)
460 * Is this right for new ABIs? I think the 4 there
461 * should be 8, size there are 8 registers to skip,
462 * not 4, but I'm not certain.
464 #ifdef COMPAT_FREEBSD32
465 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32))
467 printf("SYSCALL #%u pid:%u, narg (%u) > nsaved (%u).\n",
468 sa->code, td->td_proc->p_pid, sa->narg, nsaved);
470 #if (defined(__mips_n32) || defined(__mips_n64)) && defined(COMPAT_FREEBSD32)
471 if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
475 error = 0; /* XXX GCC is awful. */
476 for (i = nsaved; i < sa->narg; i++) {
477 error = copyin((caddr_t)(intptr_t)(locr0->sp +
478 (4 + (i - nsaved)) * sizeof(int32_t)),
479 (caddr_t)&arg, sizeof arg);
486 error = copyin((caddr_t)(intptr_t)(locr0->sp +
487 4 * sizeof(register_t)), (caddr_t)&sa->args[nsaved],
488 (u_int)(sa->narg - nsaved) * sizeof(register_t));
497 td->td_retval[0] = 0;
498 td->td_retval[1] = locr0->v1;
506 #include "../../kern/subr_syscall.c"
509 * Handle an exception.
510 * Called from MipsKernGenException() or MipsUserGenException()
511 * when a processor trap occurs.
512 * In the case of a kernel trap, we return the pc where to resume if
513 * p->p_addr->u_pcb.pcb_onfault is set, otherwise, return old pc.
516 trap(struct trapframe *trapframe)
521 struct thread *td = curthread;
522 struct proc *p = curproc;
531 register_t *frame_regs;
533 trapdebug_enter(trapframe, 0);
535 type = (trapframe->cause & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
536 if (TRAPF_USERMODE(trapframe)) {
544 * Enable hardware interrupts if they were on before the trap. If it
545 * was off disable all so we don't accidently enable it when doing a
546 * return to userland.
548 if (trapframe->sr & MIPS_SR_INT_IE) {
549 set_intr_mask(trapframe->sr & MIPS_SR_INT_MASK);
557 static vm_offset_t last_badvaddr = 0;
558 static vm_offset_t this_badvaddr = 0;
559 static int count = 0;
562 printf("trap type %x (%s - ", type,
563 trap_type[type & (~T_USER)]);
566 printf("user mode)\n");
568 printf("kernel mode)\n");
571 printf("cpuid = %d\n", PCPU_GET(cpuid));
573 pid = mips_rd_entryhi() & TLBHI_ASID_MASK;
574 printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n",
575 (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
576 (intmax_t)trapframe->sp, (intmax_t)trapframe->sr,
577 (curproc ? curproc->p_pid : -1), pid);
579 switch (type & ~T_USER) {
585 this_badvaddr = trapframe->badvaddr;
588 this_badvaddr = trapframe->ra;
591 this_badvaddr = trapframe->pc;
594 if ((last_badvaddr == this_badvaddr) &&
595 ((type & ~T_USER) != T_SYSCALL) &&
596 ((type & ~T_USER) != T_COP_UNUSABLE)) {
598 trap_frame_dump(trapframe);
599 panic("too many faults at %p\n", (void *)last_badvaddr);
602 last_badvaddr = this_badvaddr;
610 * A trap can occur while DTrace executes a probe. Before
611 * executing the probe, DTrace blocks re-scheduling and sets
612 * a flag in its per-cpu flags to indicate that it doesn't
613 * want to fault. On returning from the probe, the no-fault
614 * flag is cleared and finally re-scheduling is enabled.
616 * If the DTrace kernel module has registered a trap handler,
617 * call it and if it returns non-zero, assume that it has
618 * handled the trap and modified the trap frame so that this
619 * function can return normally.
622 * XXXDTRACE: add pid probe handler here (if ever)
625 if (dtrace_trap_func != NULL &&
626 (*dtrace_trap_func)(trapframe, type) != 0)
627 return (trapframe->pc);
634 kdb_trap(type, 0, trapframe);
639 /* check for kernel address */
640 if (KERNLAND(trapframe->badvaddr)) {
641 if (pmap_emulate_modified(kernel_pmap,
642 trapframe->badvaddr) != 0) {
643 ftype = VM_PROT_WRITE;
646 return (trapframe->pc);
650 case T_TLB_MOD + T_USER:
651 pmap = &p->p_vmspace->vm_pmap;
652 if (pmap_emulate_modified(pmap, trapframe->badvaddr) != 0) {
653 ftype = VM_PROT_WRITE;
657 return (trapframe->pc);
662 ftype = (type == T_TLB_ST_MISS) ? VM_PROT_WRITE : VM_PROT_READ;
663 /* check for kernel address */
664 if (KERNLAND(trapframe->badvaddr)) {
669 va = trunc_page((vm_offset_t)trapframe->badvaddr);
670 rv = vm_fault(kernel_map, va, ftype, VM_FAULT_NORMAL);
671 if (rv == KERN_SUCCESS)
672 return (trapframe->pc);
673 if (td->td_pcb->pcb_onfault != NULL) {
674 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
675 td->td_pcb->pcb_onfault = NULL;
682 * It is an error for the kernel to access user space except
683 * through the copyin/copyout routines.
685 if (td->td_pcb->pcb_onfault == NULL)
688 /* check for fuswintr() or suswintr() getting a page fault */
689 /* XXX There must be a nicer way to do this. */
690 if (td->td_pcb->pcb_onfault == fswintrberr) {
691 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
692 td->td_pcb->pcb_onfault = NULL;
698 case T_TLB_LD_MISS + T_USER:
699 ftype = VM_PROT_READ;
702 case T_TLB_ST_MISS + T_USER:
703 ftype = VM_PROT_WRITE;
713 va = trunc_page((vm_offset_t)trapframe->badvaddr);
714 if (KERNLAND(trapframe->badvaddr)) {
716 * Don't allow user-mode faults in kernel
722 rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
724 * XXXDTRACE: add dtrace_doubletrap_func here?
727 printf("vm_fault(%p (pmap %p), %p (%p), %x, %d) -> %x at pc %p\n",
728 map, &vm->vm_pmap, (void *)va, (void *)(intptr_t)trapframe->badvaddr,
729 ftype, VM_FAULT_NORMAL, rv, (void *)(intptr_t)trapframe->pc);
732 if (rv == KERN_SUCCESS) {
734 return (trapframe->pc);
740 if (td->td_pcb->pcb_onfault != NULL) {
741 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
742 td->td_pcb->pcb_onfault = NULL;
748 if (rv == KERN_PROTECTION_FAILURE)
752 addr = trapframe->pc;
754 msg = "BAD_PAGE_FAULT";
755 log_bad_page_fault(msg, trapframe, type);
760 case T_ADDR_ERR_LD + T_USER: /* misaligned or kseg access */
761 case T_ADDR_ERR_ST + T_USER: /* misaligned or kseg access */
762 if (trapframe->badvaddr < 0 ||
763 trapframe->badvaddr >= VM_MAXUSER_ADDRESS) {
764 msg = "ADDRESS_SPACE_ERR";
765 } else if (allow_unaligned_acc) {
768 if (type == (T_ADDR_ERR_LD + T_USER))
771 mode = VM_PROT_WRITE;
773 access_type = emulate_unaligned_access(trapframe, mode);
774 if (access_type != 0)
776 msg = "ALIGNMENT_FIX_ERR";
783 case T_BUS_ERR_IFETCH + T_USER: /* BERR asserted to cpu */
784 case T_BUS_ERR_LD_ST + T_USER: /* BERR asserted to cpu */
785 ucode = 0; /* XXX should be VM_PROT_something */
787 addr = trapframe->pc;
790 log_bad_page_fault(msg, trapframe, type);
793 case T_SYSCALL + T_USER:
797 td->td_sa.trapframe = trapframe;
798 error = syscallenter(td);
800 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
801 if (trp == trapdebug)
802 trapdebug[TRAPSIZE - 1].code = td->td_sa.code;
804 trp[-1].code = td->td_sa.code;
806 trapdebug_enter(td->td_frame, -td->td_sa.code);
809 * The sync'ing of I & D caches for SYS_ptrace() is
810 * done by procfs_domem() through procfs_rwmem()
811 * instead of being done here under a special check
814 syscallret(td, error);
815 return (trapframe->pc);
818 #if defined(KDTRACE_HOOKS) || defined(DDB)
821 if (!usermode && dtrace_invop_jump_addr != 0) {
822 dtrace_invop_jump_addr(trapframe);
823 return (trapframe->pc);
827 kdb_trap(type, 0, trapframe);
828 return (trapframe->pc);
832 case T_BREAK + T_USER:
837 /* compute address of break instruction */
839 if (DELAYBRANCH(trapframe->cause))
842 /* read break instruction */
843 instr = fuword32((caddr_t)va);
845 printf("trap: %s (%d) breakpoint %x at %x: (adr %x ins %x)\n",
846 p->p_comm, p->p_pid, instr, trapframe->pc,
847 p->p_md.md_ss_addr, p->p_md.md_ss_instr); /* XXX */
849 if (td->td_md.md_ss_addr != va ||
850 instr != MIPS_BREAK_SSTEP) {
852 addr = trapframe->pc;
856 * The restoration of the original instruction and
857 * the clearing of the breakpoint will be done later
858 * by the call to ptrace_clear_single_step() in
859 * issignal() when SIGTRAP is processed.
861 addr = trapframe->pc;
866 case T_IWATCH + T_USER:
867 case T_DWATCH + T_USER:
871 /* compute address of trapped instruction */
873 if (DELAYBRANCH(trapframe->cause))
875 printf("watch exception @ %p\n", (void *)va);
881 case T_TRAP + T_USER:
885 struct trapframe *locr0 = td->td_frame;
887 /* compute address of trap instruction */
889 if (DELAYBRANCH(trapframe->cause))
891 /* read break instruction */
892 instr = fuword32((caddr_t)va);
894 if (DELAYBRANCH(trapframe->cause)) { /* Check BD bit */
895 locr0->pc = MipsEmulateBranch(locr0, trapframe->pc, 0,
898 locr0->pc += sizeof(int);
901 i = SIGEMT; /* Stuff it with something for now */
905 case T_RES_INST + T_USER:
908 inst = *(InstFmt *)(intptr_t)trapframe->pc;
909 switch (inst.RType.op) {
911 switch (inst.RType.func) {
913 /* Register 29 used for TLS */
914 if (inst.RType.rd == 29) {
915 frame_regs = &(trapframe->zero);
916 frame_regs[inst.RType.rt] = (register_t)(intptr_t)td->td_md.md_tls;
917 frame_regs[inst.RType.rt] += td->td_md.md_tls_tcb_offset;
918 trapframe->pc += sizeof(int);
926 log_illegal_instruction("RES_INST", trapframe);
928 addr = trapframe->pc;
937 cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
938 /* Handle only COP2 exception */
942 addr = trapframe->pc;
943 /* save userland cop2 context if it has been touched */
944 if ((td->td_md.md_flags & MDTD_COP2USED) &&
945 (td->td_md.md_cop2owner == COP2_OWNER_USERLAND)) {
946 if (td->td_md.md_ucop2)
947 octeon_cop2_save(td->td_md.md_ucop2);
949 panic("COP2 was used in user mode but md_ucop2 is NULL");
952 if (td->td_md.md_cop2 == NULL) {
953 td->td_md.md_cop2 = octeon_cop2_alloc_ctx();
954 if (td->td_md.md_cop2 == NULL)
955 panic("Failed to allocate COP2 context");
956 memset(td->td_md.md_cop2, 0, sizeof(*td->td_md.md_cop2));
959 octeon_cop2_restore(td->td_md.md_cop2);
961 /* Make userland re-request its context */
962 td->td_frame->sr &= ~MIPS_SR_COP_2_BIT;
963 td->td_md.md_flags |= MDTD_COP2USED;
964 td->td_md.md_cop2owner = COP2_OWNER_KERNEL;
965 /* Enable COP2, it will be disabled in cpu_switch */
966 mips_wr_status(mips_rd_status() | MIPS_SR_COP_2_BIT);
967 return (trapframe->pc);
973 case T_COP_UNUSABLE + T_USER:
974 cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
976 /* FP (COP1) instruction */
977 if (cpuinfo.fpu_id == 0) {
978 log_illegal_instruction("COP1_UNUSABLE",
983 addr = trapframe->pc;
984 MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame);
985 PCPU_SET(fpcurthread, td);
986 #if defined(__mips_n32) || defined(__mips_n64)
987 td->td_frame->sr |= MIPS_SR_COP_1_BIT | MIPS_SR_FR;
989 td->td_frame->sr |= MIPS_SR_COP_1_BIT;
991 td->td_md.md_flags |= MDTD_FPUSED;
996 addr = trapframe->pc;
997 if ((td->td_md.md_flags & MDTD_COP2USED) &&
998 (td->td_md.md_cop2owner == COP2_OWNER_KERNEL)) {
999 if (td->td_md.md_cop2)
1000 octeon_cop2_save(td->td_md.md_cop2);
1002 panic("COP2 was used in kernel mode but md_cop2 is NULL");
1005 if (td->td_md.md_ucop2 == NULL) {
1006 td->td_md.md_ucop2 = octeon_cop2_alloc_ctx();
1007 if (td->td_md.md_ucop2 == NULL)
1008 panic("Failed to allocate userland COP2 context");
1009 memset(td->td_md.md_ucop2, 0, sizeof(*td->td_md.md_ucop2));
1012 octeon_cop2_restore(td->td_md.md_ucop2);
1014 td->td_frame->sr |= MIPS_SR_COP_2_BIT;
1015 td->td_md.md_flags |= MDTD_COP2USED;
1016 td->td_md.md_cop2owner = COP2_OWNER_USERLAND;
1021 log_illegal_instruction("COPn_UNUSABLE", trapframe);
1022 i = SIGILL; /* only FPU instructions allowed */
1027 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
1030 printf("FPU Trap: PC %#jx CR %x SR %x\n",
1031 (intmax_t)trapframe->pc, (unsigned)trapframe->cause, (unsigned)trapframe->sr);
1035 case T_FPE + T_USER:
1038 addr = trapframe->pc;
1041 MipsFPTrap(trapframe->sr, trapframe->cause, trapframe->pc);
1044 case T_OVFLOW + T_USER:
1046 addr = trapframe->pc;
1049 case T_ADDR_ERR_LD: /* misaligned access */
1050 case T_ADDR_ERR_ST: /* misaligned access */
1053 printf("+++ ADDR_ERR: type = %d, badvaddr = %#jx\n", type,
1054 (intmax_t)trapframe->badvaddr);
1057 /* Only allow emulation on a user address */
1058 if (allow_unaligned_acc &&
1059 ((vm_offset_t)trapframe->badvaddr < VM_MAXUSER_ADDRESS)) {
1062 if (type == T_ADDR_ERR_LD)
1063 mode = VM_PROT_READ;
1065 mode = VM_PROT_WRITE;
1067 access_type = emulate_unaligned_access(trapframe, mode);
1068 if (access_type != 0)
1069 return (trapframe->pc);
1073 case T_BUS_ERR_LD_ST: /* BERR asserted to cpu */
1074 if (td->td_pcb->pcb_onfault != NULL) {
1075 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
1076 td->td_pcb->pcb_onfault = NULL;
1085 #if !defined(SMP) && defined(DEBUG)
1089 printf("cpu:%d-", PCPU_GET(cpuid));
1091 printf("Trap cause = %d (%s - ", type,
1092 trap_type[type & (~T_USER)]);
1095 printf("user mode)\n");
1097 printf("kernel mode)\n");
1101 printf("badvaddr = %#jx, pc = %#jx, ra = %#jx, sr = %#jxx\n",
1102 (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
1103 (intmax_t)trapframe->sr);
1107 if (debugger_on_panic || kdb_active) {
1108 kdb_trap(type, 0, trapframe);
1113 td->td_frame->pc = trapframe->pc;
1114 td->td_frame->cause = trapframe->cause;
1115 td->td_frame->badvaddr = trapframe->badvaddr;
1116 ksiginfo_init_trap(&ksi);
1118 ksi.ksi_code = ucode;
1119 ksi.ksi_addr = (void *)addr;
1120 ksi.ksi_trapno = type;
1121 trapsignal(td, &ksi);
1125 * Note: we should only get here if returning to user mode.
1127 userret(td, trapframe);
1128 return (trapframe->pc);
1131 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
1139 printf("trapDump(%s)\n", msg);
1140 for (i = 0; i < TRAPSIZE; i++) {
1141 if (trp == trapdebug) {
1142 trp = &trapdebug[TRAPSIZE - 1];
1147 if (trp->cause == 0)
1150 printf("%s: ADR %jx PC %jx CR %jx SR %jx\n",
1151 trap_type[(trp->cause & MIPS_CR_EXC_CODE) >>
1152 MIPS_CR_EXC_CODE_SHIFT],
1153 (intmax_t)trp->vadr, (intmax_t)trp->pc,
1154 (intmax_t)trp->cause, (intmax_t)trp->status);
1156 printf(" RA %jx SP %jx code %d\n", (intmax_t)trp->ra,
1157 (intmax_t)trp->sp, (int)trp->code);
1165 * Return the resulting PC as if the branch was executed.
1168 MipsEmulateBranch(struct trapframe *framePtr, uintptr_t instPC, int fpcCSR,
1172 register_t *regsPtr = (register_t *) framePtr;
1173 uintptr_t retAddr = 0;
1176 #define GetBranchDest(InstPtr, inst) \
1177 (InstPtr + 4 + ((short)inst.IType.imm << 2))
1181 if (instptr < MIPS_KSEG0_START)
1182 inst.word = fuword32((void *)instptr);
1184 inst = *(InstFmt *) instptr;
1186 if ((vm_offset_t)instPC < MIPS_KSEG0_START)
1187 inst.word = fuword32((void *)instPC);
1189 inst = *(InstFmt *) instPC;
1192 switch ((int)inst.JType.op) {
1194 switch ((int)inst.RType.func) {
1197 retAddr = regsPtr[inst.RType.rs];
1201 retAddr = instPC + 4;
1207 switch ((int)inst.IType.rt) {
1212 if ((int)(regsPtr[inst.RType.rs]) < 0)
1213 retAddr = GetBranchDest(instPC, inst);
1215 retAddr = instPC + 8;
1222 if ((int)(regsPtr[inst.RType.rs]) >= 0)
1223 retAddr = GetBranchDest(instPC, inst);
1225 retAddr = instPC + 8;
1234 retAddr = instPC + 4; /* Like syscall... */
1238 panic("MipsEmulateBranch: Bad branch cond");
1244 retAddr = (inst.JType.target << 2) |
1245 ((unsigned)(instPC + 4) & 0xF0000000);
1250 if (regsPtr[inst.RType.rs] == regsPtr[inst.RType.rt])
1251 retAddr = GetBranchDest(instPC, inst);
1253 retAddr = instPC + 8;
1258 if (regsPtr[inst.RType.rs] != regsPtr[inst.RType.rt])
1259 retAddr = GetBranchDest(instPC, inst);
1261 retAddr = instPC + 8;
1266 if ((int)(regsPtr[inst.RType.rs]) <= 0)
1267 retAddr = GetBranchDest(instPC, inst);
1269 retAddr = instPC + 8;
1274 if ((int)(regsPtr[inst.RType.rs]) > 0)
1275 retAddr = GetBranchDest(instPC, inst);
1277 retAddr = instPC + 8;
1281 switch (inst.RType.rs) {
1284 if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)
1285 condition = fpcCSR & MIPS_FPU_COND_BIT;
1287 condition = !(fpcCSR & MIPS_FPU_COND_BIT);
1289 retAddr = GetBranchDest(instPC, inst);
1291 retAddr = instPC + 8;
1295 retAddr = instPC + 4;
1300 retAddr = instPC + 4;
1306 log_frame_dump(struct trapframe *frame)
1308 log(LOG_ERR, "Trapframe Register Dump:\n");
1309 log(LOG_ERR, "\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
1310 (intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
1312 log(LOG_ERR, "\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
1313 (intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
1315 #if defined(__mips_n32) || defined(__mips_n64)
1316 log(LOG_ERR, "\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta6: %#jx\n",
1317 (intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
1319 log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1320 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1322 log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1323 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1325 log(LOG_ERR, "\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
1326 (intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
1328 log(LOG_ERR, "\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
1329 (intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
1331 log(LOG_ERR, "\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
1332 (intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
1334 log(LOG_ERR, "\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
1335 (intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
1337 log(LOG_ERR, "\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
1338 (intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
1340 log(LOG_ERR, "\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
1341 (intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
1343 log(LOG_ERR, "\tcause: %#jx\tpc: %#jx\n",
1344 (intmax_t)frame->cause, (intmax_t)frame->pc);
1349 trap_frame_dump(struct trapframe *frame)
1351 printf("Trapframe Register Dump:\n");
1352 printf("\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
1353 (intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
1355 printf("\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
1356 (intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
1357 #if defined(__mips_n32) || defined(__mips_n64)
1358 printf("\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta7: %#jx\n",
1359 (intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
1361 printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1362 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1364 printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1365 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1367 printf("\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
1368 (intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
1370 printf("\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
1371 (intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
1373 printf("\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
1374 (intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
1376 printf("\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
1377 (intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
1379 printf("\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
1380 (intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
1382 printf("\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
1383 (intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
1385 printf("\tcause: %#jx\tpc: %#jx\n",
1386 (intmax_t)frame->cause, (intmax_t)frame->pc);
1393 get_mapping_info(vm_offset_t va, pd_entry_t **pdepp, pt_entry_t **ptepp)
1397 struct proc *p = curproc;
1399 pdep = (&(p->p_vmspace->vm_pmap.pm_segtab[(va >> SEGSHIFT) & (NPDEPG - 1)]));
1401 ptep = pmap_pte(&p->p_vmspace->vm_pmap, va);
1403 ptep = (pt_entry_t *)0;
1410 log_illegal_instruction(const char *msg, struct trapframe *frame)
1423 printf("cpuid = %d\n", PCPU_GET(cpuid));
1425 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1426 log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx ra %#jx\n",
1427 msg, p->p_pid, (long)td->td_tid, p->p_comm,
1428 p->p_ucred ? p->p_ucred->cr_uid : -1,
1430 (intmax_t)frame->ra);
1432 /* log registers in trap frame */
1433 log_frame_dump(frame);
1435 get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
1438 * Dump a few words around faulting instruction, if the addres is
1442 useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
1443 /* dump page table entry for faulting instruction */
1444 log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
1445 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1447 addr = (unsigned int *)(intptr_t)pc;
1448 log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
1450 log(LOG_ERR, "%08x %08x %08x %08x\n",
1451 addr[0], addr[1], addr[2], addr[3]);
1453 log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
1454 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1459 log_bad_page_fault(char *msg, struct trapframe *frame, int trap_type)
1466 char *read_or_write;
1469 trap_type &= ~T_USER;
1475 printf("cpuid = %d\n", PCPU_GET(cpuid));
1477 switch (trap_type) {
1481 read_or_write = "write";
1485 case T_BUS_ERR_IFETCH:
1486 read_or_write = "read";
1489 read_or_write = "unknown";
1492 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1493 log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx got a %s fault "
1494 "(type %#x) at %#jx\n",
1495 msg, p->p_pid, (long)td->td_tid, p->p_comm,
1496 p->p_ucred ? p->p_ucred->cr_uid : -1,
1500 (intmax_t)frame->badvaddr);
1502 /* log registers in trap frame */
1503 log_frame_dump(frame);
1505 get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
1508 * Dump a few words around faulting instruction, if the addres is
1511 if (!(pc & 3) && (pc != frame->badvaddr) &&
1512 (trap_type != T_BUS_ERR_IFETCH) &&
1513 useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
1514 /* dump page table entry for faulting instruction */
1515 log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
1516 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1518 addr = (unsigned int *)(intptr_t)pc;
1519 log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
1521 log(LOG_ERR, "%08x %08x %08x %08x\n",
1522 addr[0], addr[1], addr[2], addr[3]);
1524 log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
1525 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1528 get_mapping_info((vm_offset_t)frame->badvaddr, &pdep, &ptep);
1529 log(LOG_ERR, "Page table info for bad address %#jx: pde = %p, pte = %#jx\n",
1530 (intmax_t)frame->badvaddr, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1535 * Unaligned load/store emulation
1538 mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, register_t pc)
1540 register_t *reg = (register_t *) frame;
1541 u_int32_t inst = *((u_int32_t *)(intptr_t)pc);
1542 register_t value_msb, value;
1546 * ADDR_ERR faults have higher priority than TLB
1547 * Miss faults. Therefore, it is necessary to
1548 * verify that the faulting address is a valid
1549 * virtual address within the process' address space
1550 * before trying to emulate the unaligned access.
1552 switch (MIPS_INST_OPCODE(inst)) {
1553 case OP_LHU: case OP_LH:
1557 case OP_LWU: case OP_LW:
1566 printf("%s: unhandled opcode in address error: %#x\n", __func__, MIPS_INST_OPCODE(inst));
1570 if (!useracc((void *)rounddown2((vm_offset_t)addr, size), size * 2, mode))
1575 * Handle LL/SC LLD/SCD.
1577 switch (MIPS_INST_OPCODE(inst)) {
1579 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1580 lbu_macro(value_msb, addr);
1582 lbu_macro(value, addr);
1583 value |= value_msb << 8;
1584 reg[MIPS_INST_RT(inst)] = value;
1585 return (MIPS_LHU_ACCESS);
1588 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1589 lb_macro(value_msb, addr);
1591 lbu_macro(value, addr);
1592 value |= value_msb << 8;
1593 reg[MIPS_INST_RT(inst)] = value;
1594 return (MIPS_LH_ACCESS);
1597 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1598 lwl_macro(value, addr);
1600 lwr_macro(value, addr);
1601 value &= 0xffffffff;
1602 reg[MIPS_INST_RT(inst)] = value;
1603 return (MIPS_LWU_ACCESS);
1606 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1607 lwl_macro(value, addr);
1609 lwr_macro(value, addr);
1610 reg[MIPS_INST_RT(inst)] = value;
1611 return (MIPS_LW_ACCESS);
1613 #if defined(__mips_n32) || defined(__mips_n64)
1615 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1616 ldl_macro(value, addr);
1618 ldr_macro(value, addr);
1619 reg[MIPS_INST_RT(inst)] = value;
1620 return (MIPS_LD_ACCESS);
1624 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1625 value = reg[MIPS_INST_RT(inst)];
1626 value_msb = value >> 8;
1627 sb_macro(value_msb, addr);
1629 sb_macro(value, addr);
1630 return (MIPS_SH_ACCESS);
1633 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1634 value = reg[MIPS_INST_RT(inst)];
1635 swl_macro(value, addr);
1637 swr_macro(value, addr);
1638 return (MIPS_SW_ACCESS);
1640 #if defined(__mips_n32) || defined(__mips_n64)
1642 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1643 value = reg[MIPS_INST_RT(inst)];
1644 sdl_macro(value, addr);
1646 sdr_macro(value, addr);
1647 return (MIPS_SD_ACCESS);
1650 panic("%s: should not be reached.", __func__);
1657 static struct timeval unaligned_lasterr;
1658 static int unaligned_curerr;
1660 static int unaligned_pps_log_limit = 4;
1662 SYSCTL_INT(_machdep, OID_AUTO, unaligned_log_pps_limit, CTLFLAG_RWTUN,
1663 &unaligned_pps_log_limit, 0,
1664 "limit number of userland unaligned log messages per second");
1667 emulate_unaligned_access(struct trapframe *frame, int mode)
1670 int access_type = 0;
1671 struct thread *td = curthread;
1672 struct proc *p = curproc;
1674 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1677 * Fall through if it's instruction fetch exception
1679 if (!((pc & 3) || (pc == frame->badvaddr))) {
1682 * Handle unaligned load and store
1686 * Return access type if the instruction was emulated.
1687 * Otherwise restore pc and fall through.
1689 access_type = mips_unaligned_load_store(frame,
1690 mode, frame->badvaddr, pc);
1693 if (DELAYBRANCH(frame->cause))
1694 frame->pc = MipsEmulateBranch(frame, frame->pc,
1699 if (ppsratecheck(&unaligned_lasterr,
1700 &unaligned_curerr, unaligned_pps_log_limit)) {
1701 /* XXX TODO: keep global/tid/pid counters? */
1703 "Unaligned %s: pid=%ld (%s), tid=%ld, "
1704 "pc=%#jx, badvaddr=%#jx\n",
1705 access_name[access_type - 1],
1710 (intmax_t)frame->badvaddr);