1 /* $OpenBSD: trap.c,v 1.19 1998/09/30 12:40:41 pefo Exp $ */
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * from: Utah Hdr: trap.c 1.32 91/04/06
38 * from: @(#)trap.c 8.5 (Berkeley) 1/11/94
39 * JNPR: trap.c,v 1.13.2.2 2007/08/29 10:03:49 girish
41 #include <sys/cdefs.h>
42 __FBSDID("$FreeBSD$");
44 #include "opt_compat.h"
46 #include "opt_ktrace.h"
48 #include <sys/param.h>
49 #include <sys/systm.h>
50 #include <sys/sysent.h>
52 #include <sys/kernel.h>
53 #include <sys/signalvar.h>
54 #include <sys/syscall.h>
57 #include <vm/vm_extern.h>
58 #include <vm/vm_kern.h>
59 #include <vm/vm_page.h>
60 #include <vm/vm_map.h>
61 #include <vm/vm_param.h>
62 #include <sys/vmmeter.h>
63 #include <sys/ptrace.h>
66 #include <sys/vnode.h>
67 #include <sys/pioctl.h>
68 #include <sys/sysctl.h>
69 #include <sys/syslog.h>
72 #include <sys/ktrace.h>
74 #include <net/netisr.h>
76 #include <machine/trap.h>
77 #include <machine/cpu.h>
78 #include <machine/pte.h>
79 #include <machine/pmap.h>
80 #include <machine/md_var.h>
81 #include <machine/mips_opcode.h>
82 #include <machine/frame.h>
83 #include <machine/regnum.h>
84 #include <machine/tls.h>
87 #include <machine/db_machdep.h>
88 #include <ddb/db_sym.h>
94 #include <sys/dtrace_bsd.h>
99 SYSCTL_INT(_machdep, OID_AUTO, trap_debug, CTLFLAG_RW,
100 &trap_debug, 0, "Debug information on all traps");
103 #define lbu_macro(data, addr) \
104 __asm __volatile ("lbu %0, 0x0(%1)" \
105 : "=r" (data) /* outputs */ \
106 : "r" (addr)); /* inputs */
108 #define lb_macro(data, addr) \
109 __asm __volatile ("lb %0, 0x0(%1)" \
110 : "=r" (data) /* outputs */ \
111 : "r" (addr)); /* inputs */
113 #define lwl_macro(data, addr) \
114 __asm __volatile ("lwl %0, 0x0(%1)" \
115 : "=r" (data) /* outputs */ \
116 : "r" (addr)); /* inputs */
118 #define lwr_macro(data, addr) \
119 __asm __volatile ("lwr %0, 0x0(%1)" \
120 : "=r" (data) /* outputs */ \
121 : "r" (addr)); /* inputs */
123 #define ldl_macro(data, addr) \
124 __asm __volatile ("ldl %0, 0x0(%1)" \
125 : "=r" (data) /* outputs */ \
126 : "r" (addr)); /* inputs */
128 #define ldr_macro(data, addr) \
129 __asm __volatile ("ldr %0, 0x0(%1)" \
130 : "=r" (data) /* outputs */ \
131 : "r" (addr)); /* inputs */
133 #define sb_macro(data, addr) \
134 __asm __volatile ("sb %0, 0x0(%1)" \
136 : "r" (data), "r" (addr)); /* inputs */
138 #define swl_macro(data, addr) \
139 __asm __volatile ("swl %0, 0x0(%1)" \
141 : "r" (data), "r" (addr)); /* inputs */
143 #define swr_macro(data, addr) \
144 __asm __volatile ("swr %0, 0x0(%1)" \
146 : "r" (data), "r" (addr)); /* inputs */
148 #define sdl_macro(data, addr) \
149 __asm __volatile ("sdl %0, 0x0(%1)" \
151 : "r" (data), "r" (addr)); /* inputs */
153 #define sdr_macro(data, addr) \
154 __asm __volatile ("sdr %0, 0x0(%1)" \
156 : "r" (data), "r" (addr)); /* inputs */
158 static void log_illegal_instruction(const char *, struct trapframe *);
159 static void log_bad_page_fault(char *, struct trapframe *, int);
160 static void log_frame_dump(struct trapframe *frame);
161 static void get_mapping_info(vm_offset_t, pd_entry_t **, pt_entry_t **);
163 int (*dtrace_invop_jump_addr)(struct trapframe *);
166 static void trap_frame_dump(struct trapframe *frame);
169 void (*machExceptionTable[]) (void)= {
171 * The kernel exception handlers.
173 MipsKernIntr, /* external interrupt */
174 MipsKernGenException, /* TLB modification */
175 MipsTLBInvalidException,/* TLB miss (load or instr. fetch) */
176 MipsTLBInvalidException,/* TLB miss (store) */
177 MipsKernGenException, /* address error (load or I-fetch) */
178 MipsKernGenException, /* address error (store) */
179 MipsKernGenException, /* bus error (I-fetch) */
180 MipsKernGenException, /* bus error (load or store) */
181 MipsKernGenException, /* system call */
182 MipsKernGenException, /* breakpoint */
183 MipsKernGenException, /* reserved instruction */
184 MipsKernGenException, /* coprocessor unusable */
185 MipsKernGenException, /* arithmetic overflow */
186 MipsKernGenException, /* trap exception */
187 MipsKernGenException, /* virtual coherence exception inst */
188 MipsKernGenException, /* floating point exception */
189 MipsKernGenException, /* reserved */
190 MipsKernGenException, /* reserved */
191 MipsKernGenException, /* reserved */
192 MipsKernGenException, /* reserved */
193 MipsKernGenException, /* reserved */
194 MipsKernGenException, /* reserved */
195 MipsKernGenException, /* reserved */
196 MipsKernGenException, /* watch exception */
197 MipsKernGenException, /* reserved */
198 MipsKernGenException, /* reserved */
199 MipsKernGenException, /* reserved */
200 MipsKernGenException, /* reserved */
201 MipsKernGenException, /* reserved */
202 MipsKernGenException, /* reserved */
203 MipsKernGenException, /* reserved */
204 MipsKernGenException, /* virtual coherence exception data */
206 * The user exception handlers.
208 MipsUserIntr, /* 0 */
209 MipsUserGenException, /* 1 */
210 MipsTLBInvalidException,/* 2 */
211 MipsTLBInvalidException,/* 3 */
212 MipsUserGenException, /* 4 */
213 MipsUserGenException, /* 5 */
214 MipsUserGenException, /* 6 */
215 MipsUserGenException, /* 7 */
216 MipsUserGenException, /* 8 */
217 MipsUserGenException, /* 9 */
218 MipsUserGenException, /* 10 */
219 MipsUserGenException, /* 11 */
220 MipsUserGenException, /* 12 */
221 MipsUserGenException, /* 13 */
222 MipsUserGenException, /* 14 */
223 MipsUserGenException, /* 15 */
224 MipsUserGenException, /* 16 */
225 MipsUserGenException, /* 17 */
226 MipsUserGenException, /* 18 */
227 MipsUserGenException, /* 19 */
228 MipsUserGenException, /* 20 */
229 MipsUserGenException, /* 21 */
230 MipsUserGenException, /* 22 */
231 MipsUserGenException, /* 23 */
232 MipsUserGenException, /* 24 */
233 MipsUserGenException, /* 25 */
234 MipsUserGenException, /* 26 */
235 MipsUserGenException, /* 27 */
236 MipsUserGenException, /* 28 */
237 MipsUserGenException, /* 29 */
238 MipsUserGenException, /* 20 */
239 MipsUserGenException, /* 31 */
242 char *trap_type[] = {
243 "external interrupt",
245 "TLB miss (load or instr. fetch)",
247 "address error (load or I-fetch)",
248 "address error (store)",
249 "bus error (I-fetch)",
250 "bus error (load or store)",
253 "reserved instruction",
254 "coprocessor unusable",
255 "arithmetic overflow",
257 "virtual coherency instruction",
274 "virtual coherency data",
277 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
278 struct trapdebug trapdebug[TRAPSIZE], *trp = trapdebug;
281 #define KERNLAND(x) ((vm_offset_t)(x) >= VM_MIN_KERNEL_ADDRESS && (vm_offset_t)(x) < VM_MAX_KERNEL_ADDRESS)
282 #define DELAYBRANCH(x) ((int)(x) < 0)
285 * MIPS load/store access type
298 char *access_name[] = {
299 "Load Halfword Unsigned",
301 "Load Word Unsigned",
310 #include <machine/octeon_cop2.h>
313 static int allow_unaligned_acc = 1;
315 SYSCTL_INT(_vm, OID_AUTO, allow_unaligned_acc, CTLFLAG_RW,
316 &allow_unaligned_acc, 0, "Allow unaligned accesses");
319 * FP emulation is assumed to work on O32, but the code is outdated and crufty
320 * enough that it's a more sensible default to have it disabled when using
321 * other ABIs. At the very least, it needs a lot of help in using
322 * type-semantic ABI-oblivious macros for everything it does.
324 #if defined(__mips_o32)
325 static int emulate_fp = 1;
327 static int emulate_fp = 0;
329 SYSCTL_INT(_machdep, OID_AUTO, emulate_fp, CTLFLAG_RW,
330 &emulate_fp, 0, "Emulate unimplemented FPU instructions");
332 static int emulate_unaligned_access(struct trapframe *frame, int mode);
334 extern void fswintrberr(void); /* XXX */
337 cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
339 struct trapframe *locr0 = td->td_frame;
340 struct sysentvec *se;
343 bzero(sa->args, sizeof(sa->args));
345 /* compute next PC after syscall instruction */
346 td->td_pcb->pcb_tpc = sa->trapframe->pc; /* Remember if restart */
347 if (DELAYBRANCH(sa->trapframe->cause)) /* Check BD bit */
348 locr0->pc = MipsEmulateBranch(locr0, sa->trapframe->pc, 0, 0);
350 locr0->pc += sizeof(int);
351 sa->code = locr0->v0;
357 * This is an indirect syscall, in which the code is the first argument.
359 #if (!defined(__mips_n32) && !defined(__mips_n64)) || defined(COMPAT_FREEBSD32)
360 if (sa->code == SYS___syscall && SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
362 * Like syscall, but code is a quad, so as to maintain alignment
363 * for the rest of the arguments.
365 if (_QUAD_LOWWORD == 0)
366 sa->code = locr0->a0;
368 sa->code = locr0->a1;
369 sa->args[0] = locr0->a2;
370 sa->args[1] = locr0->a3;
376 * This is either not a quad syscall, or is a quad syscall with a
377 * new ABI in which quads fit in a single register.
379 sa->code = locr0->a0;
380 sa->args[0] = locr0->a1;
381 sa->args[1] = locr0->a2;
382 sa->args[2] = locr0->a3;
384 #if defined(__mips_n32) || defined(__mips_n64)
385 #ifdef COMPAT_FREEBSD32
386 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
389 * Non-o32 ABIs support more arguments in registers.
391 sa->args[3] = locr0->a4;
392 sa->args[4] = locr0->a5;
393 sa->args[5] = locr0->a6;
394 sa->args[6] = locr0->a7;
396 #ifdef COMPAT_FREEBSD32
403 * A direct syscall, arguments are just parameters to the syscall.
405 sa->args[0] = locr0->a0;
406 sa->args[1] = locr0->a1;
407 sa->args[2] = locr0->a2;
408 sa->args[3] = locr0->a3;
410 #if defined (__mips_n32) || defined(__mips_n64)
411 #ifdef COMPAT_FREEBSD32
412 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
415 * Non-o32 ABIs support more arguments in registers.
417 sa->args[4] = locr0->a4;
418 sa->args[5] = locr0->a5;
419 sa->args[6] = locr0->a6;
420 sa->args[7] = locr0->a7;
422 #ifdef COMPAT_FREEBSD32
431 printf("SYSCALL #%d pid:%u\n", sa->code, td->td_proc->p_pid);
434 se = td->td_proc->p_sysent;
437 * Shouldn't this go before switching on the code?
440 sa->code &= se->sv_mask;
442 if (sa->code >= se->sv_size)
443 sa->callp = &se->sv_table[0];
445 sa->callp = &se->sv_table[sa->code];
447 sa->narg = sa->callp->sy_narg;
449 if (sa->narg > nsaved) {
450 #if defined(__mips_n32) || defined(__mips_n64)
453 * Is this right for new ABIs? I think the 4 there
454 * should be 8, size there are 8 registers to skip,
455 * not 4, but I'm not certain.
457 #ifdef COMPAT_FREEBSD32
458 if (!SV_PROC_FLAG(td->td_proc, SV_ILP32))
460 printf("SYSCALL #%u pid:%u, narg (%u) > nsaved (%u).\n",
461 sa->code, td->td_proc->p_pid, sa->narg, nsaved);
463 #if (defined(__mips_n32) || defined(__mips_n64)) && defined(COMPAT_FREEBSD32)
464 if (SV_PROC_FLAG(td->td_proc, SV_ILP32)) {
468 error = 0; /* XXX GCC is awful. */
469 for (i = nsaved; i < sa->narg; i++) {
470 error = copyin((caddr_t)(intptr_t)(locr0->sp +
471 (4 + (i - nsaved)) * sizeof(int32_t)),
472 (caddr_t)&arg, sizeof arg);
479 error = copyin((caddr_t)(intptr_t)(locr0->sp +
480 4 * sizeof(register_t)), (caddr_t)&sa->args[nsaved],
481 (u_int)(sa->narg - nsaved) * sizeof(register_t));
490 td->td_retval[0] = 0;
491 td->td_retval[1] = locr0->v1;
499 #include "../../kern/subr_syscall.c"
502 * Handle an exception.
503 * Called from MipsKernGenException() or MipsUserGenException()
504 * when a processor trap occurs.
505 * In the case of a kernel trap, we return the pc where to resume if
506 * p->p_addr->u_pcb.pcb_onfault is set, otherwise, return old pc.
509 trap(struct trapframe *trapframe)
514 struct thread *td = curthread;
515 struct proc *p = curproc;
524 register_t *frame_regs;
526 trapdebug_enter(trapframe, 0);
528 type = (trapframe->cause & MIPS_CR_EXC_CODE) >> MIPS_CR_EXC_CODE_SHIFT;
529 if (TRAPF_USERMODE(trapframe)) {
537 * Enable hardware interrupts if they were on before the trap. If it
538 * was off disable all so we don't accidently enable it when doing a
539 * return to userland.
541 if (trapframe->sr & MIPS_SR_INT_IE) {
542 set_intr_mask(trapframe->sr & MIPS_SR_INT_MASK);
550 static vm_offset_t last_badvaddr = 0;
551 static vm_offset_t this_badvaddr = 0;
552 static int count = 0;
555 printf("trap type %x (%s - ", type,
556 trap_type[type & (~T_USER)]);
559 printf("user mode)\n");
561 printf("kernel mode)\n");
564 printf("cpuid = %d\n", PCPU_GET(cpuid));
566 pid = mips_rd_entryhi() & TLBHI_ASID_MASK;
567 printf("badaddr = %#jx, pc = %#jx, ra = %#jx, sp = %#jx, sr = %jx, pid = %d, ASID = %u\n",
568 (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
569 (intmax_t)trapframe->sp, (intmax_t)trapframe->sr,
570 (curproc ? curproc->p_pid : -1), pid);
572 switch (type & ~T_USER) {
578 this_badvaddr = trapframe->badvaddr;
581 this_badvaddr = trapframe->ra;
584 this_badvaddr = trapframe->pc;
587 if ((last_badvaddr == this_badvaddr) &&
588 ((type & ~T_USER) != T_SYSCALL) &&
589 ((type & ~T_USER) != T_COP_UNUSABLE)) {
591 trap_frame_dump(trapframe);
592 panic("too many faults at %p\n", (void *)last_badvaddr);
595 last_badvaddr = this_badvaddr;
603 * A trap can occur while DTrace executes a probe. Before
604 * executing the probe, DTrace blocks re-scheduling and sets
605 * a flag in its per-cpu flags to indicate that it doesn't
606 * want to fault. On returning from the probe, the no-fault
607 * flag is cleared and finally re-scheduling is enabled.
609 * If the DTrace kernel module has registered a trap handler,
610 * call it and if it returns non-zero, assume that it has
611 * handled the trap and modified the trap frame so that this
612 * function can return normally.
615 * XXXDTRACE: add pid probe handler here (if ever)
618 if (dtrace_trap_func != NULL &&
619 (*dtrace_trap_func)(trapframe, type) != 0)
620 return (trapframe->pc);
627 kdb_trap(type, 0, trapframe);
632 /* check for kernel address */
633 if (KERNLAND(trapframe->badvaddr)) {
634 if (pmap_emulate_modified(kernel_pmap,
635 trapframe->badvaddr) != 0) {
636 ftype = VM_PROT_WRITE;
639 return (trapframe->pc);
643 case T_TLB_MOD + T_USER:
644 pmap = &p->p_vmspace->vm_pmap;
645 if (pmap_emulate_modified(pmap, trapframe->badvaddr) != 0) {
646 ftype = VM_PROT_WRITE;
650 return (trapframe->pc);
655 ftype = (type == T_TLB_ST_MISS) ? VM_PROT_WRITE : VM_PROT_READ;
656 /* check for kernel address */
657 if (KERNLAND(trapframe->badvaddr)) {
662 va = trunc_page((vm_offset_t)trapframe->badvaddr);
663 rv = vm_fault(kernel_map, va, ftype, VM_FAULT_NORMAL);
664 if (rv == KERN_SUCCESS)
665 return (trapframe->pc);
666 if (td->td_pcb->pcb_onfault != NULL) {
667 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
668 td->td_pcb->pcb_onfault = NULL;
675 * It is an error for the kernel to access user space except
676 * through the copyin/copyout routines.
678 if (td->td_pcb->pcb_onfault == NULL)
681 /* check for fuswintr() or suswintr() getting a page fault */
682 /* XXX There must be a nicer way to do this. */
683 if (td->td_pcb->pcb_onfault == fswintrberr) {
684 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
685 td->td_pcb->pcb_onfault = NULL;
691 case T_TLB_LD_MISS + T_USER:
692 ftype = VM_PROT_READ;
695 case T_TLB_ST_MISS + T_USER:
696 ftype = VM_PROT_WRITE;
706 va = trunc_page((vm_offset_t)trapframe->badvaddr);
707 if (KERNLAND(trapframe->badvaddr)) {
709 * Don't allow user-mode faults in kernel
715 rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
717 * XXXDTRACE: add dtrace_doubletrap_func here?
720 printf("vm_fault(%p (pmap %p), %p (%p), %x, %d) -> %x at pc %p\n",
721 map, &vm->vm_pmap, (void *)va, (void *)(intptr_t)trapframe->badvaddr,
722 ftype, VM_FAULT_NORMAL, rv, (void *)(intptr_t)trapframe->pc);
725 if (rv == KERN_SUCCESS) {
727 return (trapframe->pc);
733 if (td->td_pcb->pcb_onfault != NULL) {
734 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
735 td->td_pcb->pcb_onfault = NULL;
741 if (rv == KERN_PROTECTION_FAILURE)
745 addr = trapframe->pc;
747 msg = "BAD_PAGE_FAULT";
748 log_bad_page_fault(msg, trapframe, type);
753 case T_ADDR_ERR_LD + T_USER: /* misaligned or kseg access */
754 case T_ADDR_ERR_ST + T_USER: /* misaligned or kseg access */
755 if (trapframe->badvaddr < 0 ||
756 trapframe->badvaddr >= VM_MAXUSER_ADDRESS) {
757 msg = "ADDRESS_SPACE_ERR";
758 } else if (allow_unaligned_acc) {
761 if (type == (T_ADDR_ERR_LD + T_USER))
764 mode = VM_PROT_WRITE;
766 access_type = emulate_unaligned_access(trapframe, mode);
767 if (access_type != 0)
769 msg = "ALIGNMENT_FIX_ERR";
776 case T_BUS_ERR_IFETCH + T_USER: /* BERR asserted to cpu */
777 case T_BUS_ERR_LD_ST + T_USER: /* BERR asserted to cpu */
778 ucode = 0; /* XXX should be VM_PROT_something */
780 addr = trapframe->pc;
783 log_bad_page_fault(msg, trapframe, type);
786 case T_SYSCALL + T_USER:
788 struct syscall_args sa;
791 sa.trapframe = trapframe;
792 error = syscallenter(td, &sa);
794 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
795 if (trp == trapdebug)
796 trapdebug[TRAPSIZE - 1].code = sa.code;
798 trp[-1].code = sa.code;
800 trapdebug_enter(td->td_frame, -sa.code);
803 * The sync'ing of I & D caches for SYS_ptrace() is
804 * done by procfs_domem() through procfs_rwmem()
805 * instead of being done here under a special check
808 syscallret(td, error, &sa);
809 return (trapframe->pc);
812 #if defined(KDTRACE_HOOKS) || defined(DDB)
815 if (!usermode && dtrace_invop_jump_addr != 0) {
816 dtrace_invop_jump_addr(trapframe);
817 return (trapframe->pc);
821 kdb_trap(type, 0, trapframe);
822 return (trapframe->pc);
826 case T_BREAK + T_USER:
831 /* compute address of break instruction */
833 if (DELAYBRANCH(trapframe->cause))
836 /* read break instruction */
837 instr = fuword32((caddr_t)va);
839 printf("trap: %s (%d) breakpoint %x at %x: (adr %x ins %x)\n",
840 p->p_comm, p->p_pid, instr, trapframe->pc,
841 p->p_md.md_ss_addr, p->p_md.md_ss_instr); /* XXX */
843 if (td->td_md.md_ss_addr != va ||
844 instr != MIPS_BREAK_SSTEP) {
846 addr = trapframe->pc;
850 * The restoration of the original instruction and
851 * the clearing of the breakpoint will be done later
852 * by the call to ptrace_clear_single_step() in
853 * issignal() when SIGTRAP is processed.
855 addr = trapframe->pc;
860 case T_IWATCH + T_USER:
861 case T_DWATCH + T_USER:
865 /* compute address of trapped instruction */
867 if (DELAYBRANCH(trapframe->cause))
869 printf("watch exception @ %p\n", (void *)va);
875 case T_TRAP + T_USER:
879 struct trapframe *locr0 = td->td_frame;
881 /* compute address of trap instruction */
883 if (DELAYBRANCH(trapframe->cause))
885 /* read break instruction */
886 instr = fuword32((caddr_t)va);
888 if (DELAYBRANCH(trapframe->cause)) { /* Check BD bit */
889 locr0->pc = MipsEmulateBranch(locr0, trapframe->pc, 0,
892 locr0->pc += sizeof(int);
895 i = SIGEMT; /* Stuff it with something for now */
899 case T_RES_INST + T_USER:
902 inst = *(InstFmt *)(intptr_t)trapframe->pc;
903 switch (inst.RType.op) {
905 switch (inst.RType.func) {
907 /* Register 29 used for TLS */
908 if (inst.RType.rd == 29) {
909 frame_regs = &(trapframe->zero);
910 frame_regs[inst.RType.rt] = (register_t)(intptr_t)td->td_md.md_tls;
911 frame_regs[inst.RType.rt] += td->td_md.md_tls_tcb_offset;
912 trapframe->pc += sizeof(int);
920 log_illegal_instruction("RES_INST", trapframe);
922 addr = trapframe->pc;
931 cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
932 /* Handle only COP2 exception */
936 addr = trapframe->pc;
937 /* save userland cop2 context if it has been touched */
938 if ((td->td_md.md_flags & MDTD_COP2USED) &&
939 (td->td_md.md_cop2owner == COP2_OWNER_USERLAND)) {
940 if (td->td_md.md_ucop2)
941 octeon_cop2_save(td->td_md.md_ucop2);
943 panic("COP2 was used in user mode but md_ucop2 is NULL");
946 if (td->td_md.md_cop2 == NULL) {
947 td->td_md.md_cop2 = octeon_cop2_alloc_ctx();
948 if (td->td_md.md_cop2 == NULL)
949 panic("Failed to allocate COP2 context");
950 memset(td->td_md.md_cop2, 0, sizeof(*td->td_md.md_cop2));
953 octeon_cop2_restore(td->td_md.md_cop2);
955 /* Make userland re-request its context */
956 td->td_frame->sr &= ~MIPS_SR_COP_2_BIT;
957 td->td_md.md_flags |= MDTD_COP2USED;
958 td->td_md.md_cop2owner = COP2_OWNER_KERNEL;
959 /* Enable COP2, it will be disabled in cpu_switch */
960 mips_wr_status(mips_rd_status() | MIPS_SR_COP_2_BIT);
961 return (trapframe->pc);
967 case T_COP_UNUSABLE + T_USER:
968 cop = (trapframe->cause & MIPS_CR_COP_ERR) >> MIPS_CR_COP_ERR_SHIFT;
970 #if !defined(CPU_HAVEFPU)
971 /* FP (COP1) instruction */
972 log_illegal_instruction("COP1_UNUSABLE", trapframe);
976 addr = trapframe->pc;
977 MipsSwitchFPState(PCPU_GET(fpcurthread), td->td_frame);
978 PCPU_SET(fpcurthread, td);
979 #if defined(__mips_n64)
980 td->td_frame->sr |= MIPS_SR_COP_1_BIT | MIPS_SR_FR;
982 td->td_frame->sr |= MIPS_SR_COP_1_BIT;
984 td->td_md.md_flags |= MDTD_FPUSED;
990 addr = trapframe->pc;
991 if ((td->td_md.md_flags & MDTD_COP2USED) &&
992 (td->td_md.md_cop2owner == COP2_OWNER_KERNEL)) {
993 if (td->td_md.md_cop2)
994 octeon_cop2_save(td->td_md.md_cop2);
996 panic("COP2 was used in kernel mode but md_cop2 is NULL");
999 if (td->td_md.md_ucop2 == NULL) {
1000 td->td_md.md_ucop2 = octeon_cop2_alloc_ctx();
1001 if (td->td_md.md_ucop2 == NULL)
1002 panic("Failed to allocate userland COP2 context");
1003 memset(td->td_md.md_ucop2, 0, sizeof(*td->td_md.md_ucop2));
1006 octeon_cop2_restore(td->td_md.md_ucop2);
1008 td->td_frame->sr |= MIPS_SR_COP_2_BIT;
1009 td->td_md.md_flags |= MDTD_COP2USED;
1010 td->td_md.md_cop2owner = COP2_OWNER_USERLAND;
1015 log_illegal_instruction("COPn_UNUSABLE", trapframe);
1016 i = SIGILL; /* only FPU instructions allowed */
1021 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
1024 printf("FPU Trap: PC %#jx CR %x SR %x\n",
1025 (intmax_t)trapframe->pc, (unsigned)trapframe->cause, (unsigned)trapframe->sr);
1029 case T_FPE + T_USER:
1032 addr = trapframe->pc;
1035 MipsFPTrap(trapframe->sr, trapframe->cause, trapframe->pc);
1038 case T_OVFLOW + T_USER:
1040 addr = trapframe->pc;
1043 case T_ADDR_ERR_LD: /* misaligned access */
1044 case T_ADDR_ERR_ST: /* misaligned access */
1047 printf("+++ ADDR_ERR: type = %d, badvaddr = %#jx\n", type,
1048 (intmax_t)trapframe->badvaddr);
1051 /* Only allow emulation on a user address */
1052 if (allow_unaligned_acc &&
1053 ((vm_offset_t)trapframe->badvaddr < VM_MAXUSER_ADDRESS)) {
1056 if (type == T_ADDR_ERR_LD)
1057 mode = VM_PROT_READ;
1059 mode = VM_PROT_WRITE;
1061 access_type = emulate_unaligned_access(trapframe, mode);
1062 if (access_type != 0)
1063 return (trapframe->pc);
1067 case T_BUS_ERR_LD_ST: /* BERR asserted to cpu */
1068 if (td->td_pcb->pcb_onfault != NULL) {
1069 pc = (register_t)(intptr_t)td->td_pcb->pcb_onfault;
1070 td->td_pcb->pcb_onfault = NULL;
1079 #if !defined(SMP) && defined(DEBUG)
1083 printf("cpu:%d-", PCPU_GET(cpuid));
1085 printf("Trap cause = %d (%s - ", type,
1086 trap_type[type & (~T_USER)]);
1089 printf("user mode)\n");
1091 printf("kernel mode)\n");
1095 printf("badvaddr = %#jx, pc = %#jx, ra = %#jx, sr = %#jxx\n",
1096 (intmax_t)trapframe->badvaddr, (intmax_t)trapframe->pc, (intmax_t)trapframe->ra,
1097 (intmax_t)trapframe->sr);
1101 if (debugger_on_panic || kdb_active) {
1102 kdb_trap(type, 0, trapframe);
1107 td->td_frame->pc = trapframe->pc;
1108 td->td_frame->cause = trapframe->cause;
1109 td->td_frame->badvaddr = trapframe->badvaddr;
1110 ksiginfo_init_trap(&ksi);
1112 ksi.ksi_code = ucode;
1113 ksi.ksi_addr = (void *)addr;
1114 ksi.ksi_trapno = type;
1115 trapsignal(td, &ksi);
1119 * Note: we should only get here if returning to user mode.
1121 userret(td, trapframe);
1122 return (trapframe->pc);
1125 #if !defined(SMP) && (defined(DDB) || defined(DEBUG))
1133 printf("trapDump(%s)\n", msg);
1134 for (i = 0; i < TRAPSIZE; i++) {
1135 if (trp == trapdebug) {
1136 trp = &trapdebug[TRAPSIZE - 1];
1141 if (trp->cause == 0)
1144 printf("%s: ADR %jx PC %jx CR %jx SR %jx\n",
1145 trap_type[(trp->cause & MIPS_CR_EXC_CODE) >>
1146 MIPS_CR_EXC_CODE_SHIFT],
1147 (intmax_t)trp->vadr, (intmax_t)trp->pc,
1148 (intmax_t)trp->cause, (intmax_t)trp->status);
1150 printf(" RA %jx SP %jx code %d\n", (intmax_t)trp->ra,
1151 (intmax_t)trp->sp, (int)trp->code);
1159 * Return the resulting PC as if the branch was executed.
1162 MipsEmulateBranch(struct trapframe *framePtr, uintptr_t instPC, int fpcCSR,
1166 register_t *regsPtr = (register_t *) framePtr;
1167 uintptr_t retAddr = 0;
1170 #define GetBranchDest(InstPtr, inst) \
1171 (InstPtr + 4 + ((short)inst.IType.imm << 2))
1175 if (instptr < MIPS_KSEG0_START)
1176 inst.word = fuword32((void *)instptr);
1178 inst = *(InstFmt *) instptr;
1180 if ((vm_offset_t)instPC < MIPS_KSEG0_START)
1181 inst.word = fuword32((void *)instPC);
1183 inst = *(InstFmt *) instPC;
1186 switch ((int)inst.JType.op) {
1188 switch ((int)inst.RType.func) {
1191 retAddr = regsPtr[inst.RType.rs];
1195 retAddr = instPC + 4;
1201 switch ((int)inst.IType.rt) {
1206 if ((int)(regsPtr[inst.RType.rs]) < 0)
1207 retAddr = GetBranchDest(instPC, inst);
1209 retAddr = instPC + 8;
1216 if ((int)(regsPtr[inst.RType.rs]) >= 0)
1217 retAddr = GetBranchDest(instPC, inst);
1219 retAddr = instPC + 8;
1228 retAddr = instPC + 4; /* Like syscall... */
1232 panic("MipsEmulateBranch: Bad branch cond");
1238 retAddr = (inst.JType.target << 2) |
1239 ((unsigned)(instPC + 4) & 0xF0000000);
1244 if (regsPtr[inst.RType.rs] == regsPtr[inst.RType.rt])
1245 retAddr = GetBranchDest(instPC, inst);
1247 retAddr = instPC + 8;
1252 if (regsPtr[inst.RType.rs] != regsPtr[inst.RType.rt])
1253 retAddr = GetBranchDest(instPC, inst);
1255 retAddr = instPC + 8;
1260 if ((int)(regsPtr[inst.RType.rs]) <= 0)
1261 retAddr = GetBranchDest(instPC, inst);
1263 retAddr = instPC + 8;
1268 if ((int)(regsPtr[inst.RType.rs]) > 0)
1269 retAddr = GetBranchDest(instPC, inst);
1271 retAddr = instPC + 8;
1275 switch (inst.RType.rs) {
1278 if ((inst.RType.rt & COPz_BC_TF_MASK) == COPz_BC_TRUE)
1279 condition = fpcCSR & MIPS_FPU_COND_BIT;
1281 condition = !(fpcCSR & MIPS_FPU_COND_BIT);
1283 retAddr = GetBranchDest(instPC, inst);
1285 retAddr = instPC + 8;
1289 retAddr = instPC + 4;
1294 retAddr = instPC + 4;
1300 log_frame_dump(struct trapframe *frame)
1302 log(LOG_ERR, "Trapframe Register Dump:\n");
1303 log(LOG_ERR, "\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
1304 (intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
1306 log(LOG_ERR, "\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
1307 (intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
1309 #if defined(__mips_n32) || defined(__mips_n64)
1310 log(LOG_ERR, "\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta6: %#jx\n",
1311 (intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
1313 log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1314 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1316 log(LOG_ERR, "\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1317 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1319 log(LOG_ERR, "\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
1320 (intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
1322 log(LOG_ERR, "\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
1323 (intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
1325 log(LOG_ERR, "\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
1326 (intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
1328 log(LOG_ERR, "\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
1329 (intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
1331 log(LOG_ERR, "\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
1332 (intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
1334 log(LOG_ERR, "\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
1335 (intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
1338 log(LOG_ERR, "\tcause: %#jx\tpc: %#jx\tic: %#jx\n",
1339 (intmax_t)frame->cause, (intmax_t)frame->pc, (intmax_t)frame->ic);
1341 log(LOG_ERR, "\tcause: %#jx\tpc: %#jx\n",
1342 (intmax_t)frame->cause, (intmax_t)frame->pc);
1348 trap_frame_dump(struct trapframe *frame)
1350 printf("Trapframe Register Dump:\n");
1351 printf("\tzero: %#jx\tat: %#jx\tv0: %#jx\tv1: %#jx\n",
1352 (intmax_t)0, (intmax_t)frame->ast, (intmax_t)frame->v0, (intmax_t)frame->v1);
1354 printf("\ta0: %#jx\ta1: %#jx\ta2: %#jx\ta3: %#jx\n",
1355 (intmax_t)frame->a0, (intmax_t)frame->a1, (intmax_t)frame->a2, (intmax_t)frame->a3);
1356 #if defined(__mips_n32) || defined(__mips_n64)
1357 printf("\ta4: %#jx\ta5: %#jx\ta6: %#jx\ta7: %#jx\n",
1358 (intmax_t)frame->a4, (intmax_t)frame->a5, (intmax_t)frame->a6, (intmax_t)frame->a7);
1360 printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1361 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1363 printf("\tt0: %#jx\tt1: %#jx\tt2: %#jx\tt3: %#jx\n",
1364 (intmax_t)frame->t0, (intmax_t)frame->t1, (intmax_t)frame->t2, (intmax_t)frame->t3);
1366 printf("\tt4: %#jx\tt5: %#jx\tt6: %#jx\tt7: %#jx\n",
1367 (intmax_t)frame->t4, (intmax_t)frame->t5, (intmax_t)frame->t6, (intmax_t)frame->t7);
1369 printf("\tt8: %#jx\tt9: %#jx\ts0: %#jx\ts1: %#jx\n",
1370 (intmax_t)frame->t8, (intmax_t)frame->t9, (intmax_t)frame->s0, (intmax_t)frame->s1);
1372 printf("\ts2: %#jx\ts3: %#jx\ts4: %#jx\ts5: %#jx\n",
1373 (intmax_t)frame->s2, (intmax_t)frame->s3, (intmax_t)frame->s4, (intmax_t)frame->s5);
1375 printf("\ts6: %#jx\ts7: %#jx\tk0: %#jx\tk1: %#jx\n",
1376 (intmax_t)frame->s6, (intmax_t)frame->s7, (intmax_t)frame->k0, (intmax_t)frame->k1);
1378 printf("\tgp: %#jx\tsp: %#jx\ts8: %#jx\tra: %#jx\n",
1379 (intmax_t)frame->gp, (intmax_t)frame->sp, (intmax_t)frame->s8, (intmax_t)frame->ra);
1381 printf("\tsr: %#jx\tmullo: %#jx\tmulhi: %#jx\tbadvaddr: %#jx\n",
1382 (intmax_t)frame->sr, (intmax_t)frame->mullo, (intmax_t)frame->mulhi, (intmax_t)frame->badvaddr);
1385 printf("\tcause: %#jx\tpc: %#jx\tic: %#jx\n",
1386 (intmax_t)frame->cause, (intmax_t)frame->pc, (intmax_t)frame->ic);
1388 printf("\tcause: %#jx\tpc: %#jx\n",
1389 (intmax_t)frame->cause, (intmax_t)frame->pc);
1397 get_mapping_info(vm_offset_t va, pd_entry_t **pdepp, pt_entry_t **ptepp)
1401 struct proc *p = curproc;
1403 pdep = (&(p->p_vmspace->vm_pmap.pm_segtab[(va >> SEGSHIFT) & (NPDEPG - 1)]));
1405 ptep = pmap_pte(&p->p_vmspace->vm_pmap, va);
1407 ptep = (pt_entry_t *)0;
1414 log_illegal_instruction(const char *msg, struct trapframe *frame)
1427 printf("cpuid = %d\n", PCPU_GET(cpuid));
1429 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1430 log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx ra %#jx\n",
1431 msg, p->p_pid, (long)td->td_tid, p->p_comm,
1432 p->p_ucred ? p->p_ucred->cr_uid : -1,
1434 (intmax_t)frame->ra);
1436 /* log registers in trap frame */
1437 log_frame_dump(frame);
1439 get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
1442 * Dump a few words around faulting instruction, if the addres is
1446 useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
1447 /* dump page table entry for faulting instruction */
1448 log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
1449 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1451 addr = (unsigned int *)(intptr_t)pc;
1452 log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
1454 log(LOG_ERR, "%08x %08x %08x %08x\n",
1455 addr[0], addr[1], addr[2], addr[3]);
1457 log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
1458 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1463 log_bad_page_fault(char *msg, struct trapframe *frame, int trap_type)
1470 char *read_or_write;
1473 trap_type &= ~T_USER;
1479 printf("cpuid = %d\n", PCPU_GET(cpuid));
1481 switch (trap_type) {
1485 read_or_write = "write";
1489 case T_BUS_ERR_IFETCH:
1490 read_or_write = "read";
1493 read_or_write = "unknown";
1496 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1497 log(LOG_ERR, "%s: pid %d tid %ld (%s), uid %d: pc %#jx got a %s fault "
1498 "(type %#x) at %#jx\n",
1499 msg, p->p_pid, (long)td->td_tid, p->p_comm,
1500 p->p_ucred ? p->p_ucred->cr_uid : -1,
1504 (intmax_t)frame->badvaddr);
1506 /* log registers in trap frame */
1507 log_frame_dump(frame);
1509 get_mapping_info((vm_offset_t)pc, &pdep, &ptep);
1512 * Dump a few words around faulting instruction, if the addres is
1515 if (!(pc & 3) && (pc != frame->badvaddr) &&
1516 (trap_type != T_BUS_ERR_IFETCH) &&
1517 useracc((caddr_t)(intptr_t)pc, sizeof(int) * 4, VM_PROT_READ)) {
1518 /* dump page table entry for faulting instruction */
1519 log(LOG_ERR, "Page table info for pc address %#jx: pde = %p, pte = %#jx\n",
1520 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1522 addr = (unsigned int *)(intptr_t)pc;
1523 log(LOG_ERR, "Dumping 4 words starting at pc address %p: \n",
1525 log(LOG_ERR, "%08x %08x %08x %08x\n",
1526 addr[0], addr[1], addr[2], addr[3]);
1528 log(LOG_ERR, "pc address %#jx is inaccessible, pde = %p, pte = %#jx\n",
1529 (intmax_t)pc, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1532 get_mapping_info((vm_offset_t)frame->badvaddr, &pdep, &ptep);
1533 log(LOG_ERR, "Page table info for bad address %#jx: pde = %p, pte = %#jx\n",
1534 (intmax_t)frame->badvaddr, (void *)(intptr_t)*pdep, (uintmax_t)(ptep ? *ptep : 0));
1539 * Unaligned load/store emulation
1542 mips_unaligned_load_store(struct trapframe *frame, int mode, register_t addr, register_t pc)
1544 register_t *reg = (register_t *) frame;
1545 u_int32_t inst = *((u_int32_t *)(intptr_t)pc);
1546 register_t value_msb, value;
1550 * ADDR_ERR faults have higher priority than TLB
1551 * Miss faults. Therefore, it is necessary to
1552 * verify that the faulting address is a valid
1553 * virtual address within the process' address space
1554 * before trying to emulate the unaligned access.
1556 switch (MIPS_INST_OPCODE(inst)) {
1557 case OP_LHU: case OP_LH:
1561 case OP_LWU: case OP_LW:
1570 printf("%s: unhandled opcode in address error: %#x\n", __func__, MIPS_INST_OPCODE(inst));
1574 if (!useracc((void *)rounddown2((vm_offset_t)addr, size), size * 2, mode))
1579 * Handle LL/SC LLD/SCD.
1581 switch (MIPS_INST_OPCODE(inst)) {
1583 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1584 lbu_macro(value_msb, addr);
1586 lbu_macro(value, addr);
1587 value |= value_msb << 8;
1588 reg[MIPS_INST_RT(inst)] = value;
1589 return (MIPS_LHU_ACCESS);
1592 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1593 lb_macro(value_msb, addr);
1595 lbu_macro(value, addr);
1596 value |= value_msb << 8;
1597 reg[MIPS_INST_RT(inst)] = value;
1598 return (MIPS_LH_ACCESS);
1601 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1602 lwl_macro(value, addr);
1604 lwr_macro(value, addr);
1605 value &= 0xffffffff;
1606 reg[MIPS_INST_RT(inst)] = value;
1607 return (MIPS_LWU_ACCESS);
1610 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1611 lwl_macro(value, addr);
1613 lwr_macro(value, addr);
1614 reg[MIPS_INST_RT(inst)] = value;
1615 return (MIPS_LW_ACCESS);
1617 #if defined(__mips_n32) || defined(__mips_n64)
1619 KASSERT(mode == VM_PROT_READ, ("access mode must be read for load instruction."));
1620 ldl_macro(value, addr);
1622 ldr_macro(value, addr);
1623 reg[MIPS_INST_RT(inst)] = value;
1624 return (MIPS_LD_ACCESS);
1628 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1629 value = reg[MIPS_INST_RT(inst)];
1630 value_msb = value >> 8;
1631 sb_macro(value_msb, addr);
1633 sb_macro(value, addr);
1634 return (MIPS_SH_ACCESS);
1637 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1638 value = reg[MIPS_INST_RT(inst)];
1639 swl_macro(value, addr);
1641 swr_macro(value, addr);
1642 return (MIPS_SW_ACCESS);
1644 #if defined(__mips_n32) || defined(__mips_n64)
1646 KASSERT(mode == VM_PROT_WRITE, ("access mode must be write for store instruction."));
1647 value = reg[MIPS_INST_RT(inst)];
1648 sdl_macro(value, addr);
1650 sdr_macro(value, addr);
1651 return (MIPS_SD_ACCESS);
1654 panic("%s: should not be reached.", __func__);
1661 static struct timeval unaligned_lasterr;
1662 static int unaligned_curerr;
1664 static int unaligned_pps_log_limit = 4;
1666 SYSCTL_INT(_machdep, OID_AUTO, unaligned_log_pps_limit, CTLFLAG_RWTUN,
1667 &unaligned_pps_log_limit, 0,
1668 "limit number of userland unaligned log messages per second");
1671 emulate_unaligned_access(struct trapframe *frame, int mode)
1674 int access_type = 0;
1675 struct thread *td = curthread;
1676 struct proc *p = curproc;
1678 pc = frame->pc + (DELAYBRANCH(frame->cause) ? 4 : 0);
1681 * Fall through if it's instruction fetch exception
1683 if (!((pc & 3) || (pc == frame->badvaddr))) {
1686 * Handle unaligned load and store
1690 * Return access type if the instruction was emulated.
1691 * Otherwise restore pc and fall through.
1693 access_type = mips_unaligned_load_store(frame,
1694 mode, frame->badvaddr, pc);
1697 if (DELAYBRANCH(frame->cause))
1698 frame->pc = MipsEmulateBranch(frame, frame->pc,
1703 if (ppsratecheck(&unaligned_lasterr,
1704 &unaligned_curerr, unaligned_pps_log_limit)) {
1705 /* XXX TODO: keep global/tid/pid counters? */
1707 "Unaligned %s: pid=%ld (%s), tid=%ld, "
1708 "pc=%#jx, badvaddr=%#jx\n",
1709 access_name[access_type - 1],
1714 (intmax_t)frame->badvaddr);