2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32 #include <sys/types.h>
33 #include <sys/systm.h>
35 #include <machine/cpufunc.h>
36 #include <mips/nlm/hal/mips-extns.h>
37 #include <mips/nlm/hal/haldefs.h>
38 #include <mips/nlm/hal/iomap.h>
39 #include <mips/nlm/hal/fmn.h>
41 /* XLP can take upto 16K of FMN messages per hardware queue, as spill.
42 * But, configuring all 16K causes the total spill memory to required
43 * to blow upto 192MB for single chip configuration, and 768MB in four
44 * chip configuration. Hence for now, we will setup the per queue spill
45 * as 1K FMN messages. With this, the total spill memory needed for 1024
46 * hardware queues (with 12bytes per single entry FMN message) becomes
47 * (1*1024)*12*1024queues = 12MB. For the four chip config, the memory
48 * needed = 12 * 4 = 48MB.
50 uint64_t nlm_cms_spill_total_messages = 1 * 1024;
52 /* On a XLP832, we have the following FMN stations:
65 * Total : 18 stations per chip
67 * For all 4 nodes, there are 18*4 = 72 FMN stations
69 uint32_t nlm_cms_total_stations = 18 * 4 /*xlp_num_nodes*/;
72 * Takes inputs as node, queue_size and maximum number of queues.
73 * Calculates the base, start & end and returns the same for a
76 * The output queues are maintained in the internal output buffer
77 * which is a on-chip SRAM structure. For the actial hardware
78 * internal implementation, It is a structure which consists
79 * of eight banks of 4096-entry x message-width SRAMs. The SRAM
80 * implementation is designed to run at 1GHz with a 1-cycle read/write
81 * access. A read/write transaction can be initiated for each bank
82 * every cycle for a total of eight accesses per cycle. Successive
83 * entries of the same output queue are placed in successive banks.
84 * This is done to spread different read & write accesses to same/different
85 * output queue over as many different banks as possible so that they
86 * can be scheduled concurrently. Spreading the accesses to as many banks
87 * as possible to maximize the concurrency internally is important for
88 * achieving the desired peak throughput. This is done by h/w implementation
91 * Output queues are allocated from this internal output buffer by
92 * software. The total capacity of the output buffer is 32K-entry.
93 * Each output queue can be sized from 32-entry to 1024-entry in
94 * increments of 32-entry. This is done by specifying a Start & a
95 * End pointer: pointers to the first & last 32-entry chunks allocated
96 * to the output queue.
98 * To optimize the storage required for 1024 OQ pointers, the upper 5-bits
99 * are shared by the Start & the End pointer. The side-effect of this
100 * optimization is that an OQ can't cross a 1024-entry boundary. Also, the
101 * lower 5-bits don't need to be specified in the Start & the End pointer
102 * as the allocation is in increments of 32-entries.
104 * Queue occupancy is tracked by a Head & a Tail pointer. Tail pointer
105 * indicates the location to which next entry will be written & Head
106 * pointer indicates the location from which next entry will be read. When
107 * these pointers reach the top of the allocated space (indicated by the
108 * End pointer), they are reset to the bottom of the allocated space
109 * (indicated by the Start pointer).
111 * Output queue pointer information:
112 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
124 * ------------------------------------
126 * ------------------------------------
127 * ------------------------------------
129 * ------------------------------------
131 * A total of 1024 segments can sit on one software-visible "bank"
132 * of internal SRAM. Each segment contains 32 entries. Also note
133 * that sw-visible "banks" are not the same as the actual internal
134 * 8-bank implementation of hardware. It is an optimization of
139 void nlm_cms_setup_credits(uint64_t base, int destid, int srcid, int credit)
143 val = (((uint64_t)credit << 24) | (destid << 12) | (srcid << 0));
144 nlm_write_cms_reg(base, CMS_OUTPUTQ_CREDIT_CFG, val);
149 * base - CMS module base address for this node.
150 * qid - is the output queue id otherwise called as vc id
151 * spill_base - is the 40-bit physical address of spill memory. Must be
153 * nsegs - No of segments where a "1" indicates 4KB. Spill size must be
156 int nlm_cms_alloc_spill_q(uint64_t base, int qid, uint64_t spill_base,
159 uint64_t queue_config;
160 uint32_t spill_start;
162 if (nsegs > CMS_MAX_SPILL_SEGMENTS_PER_QUEUE) {
166 queue_config = nlm_read_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)));
168 spill_start = ((spill_base >> 12) & 0x3F);
169 /* Spill configuration */
170 queue_config = (((uint64_t)CMS_SPILL_ENA << 62) |
171 (((spill_base >> 18) & 0x3FFFFF) << 27) |
172 (spill_start + nsegs - 1) << 21 |
173 (spill_start << 15));
175 nlm_write_cms_reg(base,(CMS_OUTPUTQ_CONFIG(qid)),queue_config);
180 uint64_t nlm_cms_get_onchip_queue (uint64_t base, int qid)
182 return nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
185 void nlm_cms_set_onchip_queue (uint64_t base, int qid, uint64_t val)
189 rdval = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
191 nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), rdval);
194 void nlm_cms_per_queue_level_intr(uint64_t base, int qid, int sub_type,
199 val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
201 val &= ~((0x7ULL << 56) | (0x3ULL << 54));
203 val |= (((uint64_t)sub_type<<54) |
204 ((uint64_t)intr_val<<56));
206 nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
209 void nlm_cms_per_queue_timer_intr(uint64_t base, int qid, int sub_type,
214 val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
216 val &= ~((0x7ULL << 51) | (0x3ULL << 49));
218 val |= (((uint64_t)sub_type<<49) |
219 ((uint64_t)intr_val<<51));
221 nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
224 /* returns 1 if interrupt has been generated for this output queue */
225 int nlm_cms_outputq_intr_check(uint64_t base, int qid)
228 val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
230 return ((val >> 59) & 0x1);
233 void nlm_cms_outputq_clr_intr(uint64_t base, int qid)
236 val = nlm_read_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid));
238 nlm_write_cms_reg(base, CMS_OUTPUTQ_CONFIG(qid), val);
241 void nlm_cms_illegal_dst_error_intr(uint64_t base, int en)
245 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
247 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
250 void nlm_cms_timeout_error_intr(uint64_t base, int en)
254 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
256 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
259 void nlm_cms_biu_error_resp_intr(uint64_t base, int en)
263 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
265 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
268 void nlm_cms_spill_uncorrectable_ecc_error_intr(uint64_t base, int en)
272 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
273 val |= (en<<5) | (en<<3);
274 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
277 void nlm_cms_spill_correctable_ecc_error_intr(uint64_t base, int en)
281 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
282 val |= (en<<4) | (en<<2);
283 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
286 void nlm_cms_outputq_uncorrectable_ecc_error_intr(uint64_t base, int en)
290 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
292 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
295 void nlm_cms_outputq_correctable_ecc_error_intr(uint64_t base, int en)
299 val = nlm_read_cms_reg(base, CMS_MSG_CONFIG);
301 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
304 uint64_t nlm_cms_network_error_status(uint64_t base)
306 return nlm_read_cms_reg(base, CMS_MSG_ERR);
309 int nlm_cms_get_net_error_code(uint64_t err)
311 return ((err >> 12) & 0xf);
314 int nlm_cms_get_net_error_syndrome(uint64_t err)
316 return ((err >> 32) & 0x1ff);
319 int nlm_cms_get_net_error_ramindex(uint64_t err)
321 return ((err >> 44) & 0x7fff);
324 int nlm_cms_get_net_error_outputq(uint64_t err)
326 return ((err >> 16) & 0xfff);
329 /*========================= FMN Tracing related APIs ================*/
331 void nlm_cms_trace_setup(uint64_t base, int en, uint64_t trace_base,
332 uint64_t trace_limit, int match_dstid_en,
333 int dst_id, int match_srcid_en, int src_id,
338 nlm_write_cms_reg(base, CMS_TRACE_BASE_ADDR, trace_base);
339 nlm_write_cms_reg(base, CMS_TRACE_LIMIT_ADDR, trace_limit);
341 val = nlm_read_cms_reg(base, CMS_TRACE_CONFIG);
342 val |= (((uint64_t)match_dstid_en << 39) |
343 ((dst_id & 0xfff) << 24) |
344 (match_srcid_en << 23) |
345 ((src_id & 0xfff) << 8) |
348 nlm_write_cms_reg(base, CMS_MSG_CONFIG, val);
351 void nlm_cms_endian_byte_swap (uint64_t base, int en)
353 nlm_write_cms_reg(base, CMS_MSG_ENDIAN_SWAP, en);