2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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34 #ifndef __XLP_PCIBUS_H__
35 #define __XLP_PCIBUS_H__
37 #define MSI_MIPS_ADDR_BASE 0xfee00000
39 #define MSI_MIPS_ADDR_DEST 0x000ff000
40 #define MSI_MIPS_ADDR_RH 0x00000008
41 #define MSI_MIPS_ADDR_RH_OFF 0x00000000
42 #define MSI_MIPS_ADDR_RH_ON 0x00000008
43 #define MSI_MIPS_ADDR_DM 0x00000004
44 #define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
45 #define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
47 /* Fields in data for Intel MSI messages. */
48 #define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
49 #define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
50 #define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
52 #define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
53 #define MSI_MIPS_DATA_DEASSERT 0x00000000
54 #define MSI_MIPS_DATA_ASSERT 0x00004000
56 #define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
57 #define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
58 #define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
60 #define MSI_MIPS_DATA_INTVEC 0x000000ff
62 /* PCIE Memory and IO regions */
63 #define PCIE_MEM_BASE 0xd0000000ULL
64 #define PCIE_MEM_LIMIT 0xdfffffffULL
65 #define PCIE_IO_BASE 0x14000000ULL
66 #define PCIE_IO_LIMIT 0x15ffffffULL
68 #define PCIE_BRIDGE_CMD 0x1
69 #define PCIE_BRIDGE_MSI_CAP 0x14
70 #define PCIE_BRIDGE_MSI_ADDRL 0x15
71 #define PCIE_BRIDGE_MSI_ADDRH 0x16
72 #define PCIE_BRIDGE_MSI_DATA 0x17
74 /* XLP Global PCIE configuration space registers */
75 #define PCIE_BYTE_SWAP_MEM_BASE 0x247
76 #define PCIE_BYTE_SWAP_MEM_LIM 0x248
77 #define PCIE_BYTE_SWAP_IO_BASE 0x249
78 #define PCIE_BYTE_SWAP_IO_LIM 0x24A
79 #define PCIE_MSI_STATUS 0x25A
80 #define PCIE_MSI_EN 0x25B
81 #define PCIE_INT_EN0 0x261
84 #define PCIE_MSI_VECTOR_INT_EN 0xFFFFFFFF
87 #define PCIE_MSI_INT_EN (1 << 9)
89 /* XXXJC: Ax workaround */
90 #define PCIE_LINK0_IRT 78
92 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
94 #define nlm_read_pcie_reg(b, r) nlm_read_reg(b, r)
95 #define nlm_write_pcie_reg(b, r, v) nlm_write_reg(b, r, v)
96 #define nlm_get_pcie_base(node, inst) \
97 nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node, inst))
98 #define nlm_get_pcie_regbase(node, inst) \
99 (nlm_get_pcie_base(node, inst) + XLP_IO_PCI_HDRSZ)
102 xlp_pcie_link_irt(int link)
104 if ((link < 0) || (link > 3))
107 return (PCIE_LINK0_IRT + link);
111 * Build Intel MSI message and data values from a source. AMD64 systems
112 * seem to be compatible, so we use the same function for both.
114 #define MIPS_MSI_ADDR(cpu) \
115 (MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
116 MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
118 #define MIPS_MSI_DATA(irq) \
119 (MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
120 MSI_MIPS_DATA_ASSERT | (irq))
123 #endif /* __XLP_PCIBUS_H__ */