sys/mips/nlm/hal/pic.h

   1 /*-
   2  * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
   3  * reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in
  13  *    the documentation and/or other materials provided with the
  14  *    distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  19  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
  20  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  21  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  22  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  23  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  24  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  25  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  26  * THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * NETLOGIC_BSD
  29  * $FreeBSD$
  30  */
  31
  32 #ifndef _NLM_HAL_PIC_H
  33 #define _NLM_HAL_PIC_H
  34
  35 /* PIC Specific registers */
  36 #define PIC_CTRL                0x00
  37
  38 /* PIC control register defines */
  39 #define PIC_CTRL_ITV            32 /* interrupt timeout value */
  40 #define PIC_CTRL_ICI            19 /* ICI interrupt timeout enable */
  41 #define PIC_CTRL_ITE            18 /* interrupt timeout enable */
  42 #define PIC_CTRL_STE            10 /* system timer interrupt enable */
  43 #define PIC_CTRL_WWR1           8  /* watchdog 1 wraparound count for reset */
  44 #define PIC_CTRL_WWR0           6  /* watchdog 0 wraparound count for reset */
  45 #define PIC_CTRL_WWN1           4  /* watchdog 1 wraparound count for NMI */
  46 #define PIC_CTRL_WWN0           2  /* watchdog 0 wraparound count for NMI */
  47 #define PIC_CTRL_WTE            0  /* watchdog timer enable */
  48
  49 /* PIC Status register defines */
  50 #define PIC_ICI_STATUS          33 /* ICI interrupt timeout status */
  51 #define PIC_ITE_STATUS          32 /* interrupt timeout status */
  52 #define PIC_STS_STATUS          4  /* System timer interrupt status */
  53 #define PIC_WNS_STATUS          2  /* NMI status for watchdog timers */
  54 #define PIC_WIS_STATUS          0  /* Interrupt status for watchdog timers */
  55
  56 /* PIC IPI control register offsets */
  57 #define PIC_IPICTRL_NMI         32
  58 #define PIC_IPICTRL_RIV         20 /* received interrupt vector */
  59 #define PIC_IPICTRL_IDB         16 /* interrupt destination base */
  60 #define PIC_IPICTRL_DTE          0 /* interrupt destination thread enables */
  61
  62 /* PIC IRT register offsets */
  63 #define PIC_IRT_ENABLE          31
  64 #define PIC_IRT_NMI             29
  65 #define PIC_IRT_SCH             28 /* Scheduling scheme */
  66 #define PIC_IRT_RVEC            20 /* Interrupt receive vectors */
  67 #define PIC_IRT_DT              19 /* Destination type */
  68 #define PIC_IRT_DB              16 /* Destination base */
  69 #define PIC_IRT_DTE             0  /* Destination thread enables */
  70
  71 #define PIC_BYTESWAP            0x02
  72 #define PIC_STATUS              0x04
  73 #define PIC_INTR_TIMEOUT        0x06
  74 #define PIC_ICI0_INTR_TIMEOUT   0x08
  75 #define PIC_ICI1_INTR_TIMEOUT   0x0a
  76 #define PIC_ICI2_INTR_TIMEOUT   0x0c
  77 #define PIC_IPI_CTL             0x0e
  78 #define PIC_INT_ACK             0x10
  79 #define PIC_INT_PENDING0        0x12
  80 #define PIC_INT_PENDING1        0x14
  81 #define PIC_INT_PENDING2        0x16
  82
  83 #define PIC_WDOG0_MAXVAL        0x18
  84 #define PIC_WDOG0_COUNT         0x1a
  85 #define PIC_WDOG0_ENABLE0       0x1c
  86 #define PIC_WDOG0_ENABLE1       0x1e
  87 #define PIC_WDOG0_BEATCMD       0x20
  88 #define PIC_WDOG0_BEAT0         0x22
  89 #define PIC_WDOG0_BEAT1         0x24
  90
  91 #define PIC_WDOG1_MAXVAL        0x26
  92 #define PIC_WDOG1_COUNT         0x28
  93 #define PIC_WDOG1_ENABLE0       0x2a
  94 #define PIC_WDOG1_ENABLE1       0x2c
  95 #define PIC_WDOG1_BEATCMD       0x2e
  96 #define PIC_WDOG1_BEAT0         0x30
  97 #define PIC_WDOG1_BEAT1         0x32
  98
  99 #define PIC_WDOG_MAXVAL(i)      (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0))
 100 #define PIC_WDOG_COUNT(i)       (PIC_WDOG0_COUNT + ((i) ? 7 : 0))
 101 #define PIC_WDOG_ENABLE0(i)     (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0))
 102 #define PIC_WDOG_ENABLE1(i)     (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0))
 103 #define PIC_WDOG_BEATCMD(i)     (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0))
 104 #define PIC_WDOG_BEAT0(i)       (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0))
 105 #define PIC_WDOG_BEAT1(i)       (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0))
 106
 107 #define PIC_TIMER0_MAXVAL       0x34
 108 #define PIC_TIMER1_MAXVAL       0x36
 109 #define PIC_TIMER2_MAXVAL       0x38
 110 #define PIC_TIMER3_MAXVAL       0x3a
 111 #define PIC_TIMER4_MAXVAL       0x3c
 112 #define PIC_TIMER5_MAXVAL       0x3e
 113 #define PIC_TIMER6_MAXVAL       0x40
 114 #define PIC_TIMER7_MAXVAL       0x42
 115 #define PIC_TIMER_MAXVAL(i)     (PIC_TIMER0_MAXVAL + ((i) * 2))
 116
 117 #define PIC_TIMER0_COUNT        0x44
 118 #define PIC_TIMER1_COUNT        0x46
 119 #define PIC_TIMER2_COUNT        0x48
 120 #define PIC_TIMER3_COUNT        0x4a
 121 #define PIC_TIMER4_COUNT        0x4c
 122 #define PIC_TIMER5_COUNT        0x4e
 123 #define PIC_TIMER6_COUNT        0x50
 124 #define PIC_TIMER7_COUNT        0x52
 125 #define PIC_TIMER_COUNT(i)      (PIC_TIMER0_COUNT + ((i) * 2))
 126
 127 #define PIC_ITE0_N0_N1          0x54
 128 #define PIC_ITE1_N0_N1          0x58
 129 #define PIC_ITE2_N0_N1          0x5c
 130 #define PIC_ITE3_N0_N1          0x60
 131 #define PIC_ITE4_N0_N1          0x64
 132 #define PIC_ITE5_N0_N1          0x68
 133 #define PIC_ITE6_N0_N1          0x6c
 134 #define PIC_ITE7_N0_N1          0x70
 135 #define PIC_ITE_N0_N1(i)        (PIC_ITE0_N0_N1 + ((i) * 4))
 136
 137 #define PIC_ITE0_N2_N3          0x56
 138 #define PIC_ITE1_N2_N3          0x5a
 139 #define PIC_ITE2_N2_N3          0x5e
 140 #define PIC_ITE3_N2_N3          0x62
 141 #define PIC_ITE4_N2_N3          0x66
 142 #define PIC_ITE5_N2_N3          0x6a
 143 #define PIC_ITE6_N2_N3          0x6e
 144 #define PIC_ITE7_N2_N3          0x72
 145 #define PIC_ITE_N2_N3(i)                (PIC_ITE0_N2_N3 + ((i) * 4))
 146
 147 #define PIC_IRT0                0x74
 148 #define PIC_IRT(i)              (PIC_IRT0 + ((i) * 2))
 149
 150 #define TIMER_CYCLES_MAXVAL     0xffffffffffffffffULL
 151
 152 /*
 153  *    IRT Map
 154  */
 155 #define PIC_IRT_WD_0_INDEX      0
 156 #define PIC_IRT_WD_1_INDEX      1
 157 #define PIC_IRT_WD_NMI_0_INDEX  2
 158 #define PIC_IRT_WD_NMI_1_INDEX  3
 159 #define PIC_IRT_TIMER_0_INDEX   4
 160 #define PIC_IRT_TIMER_1_INDEX   5
 161 #define PIC_IRT_TIMER_2_INDEX   6
 162 #define PIC_IRT_TIMER_3_INDEX   7
 163 #define PIC_IRT_TIMER_4_INDEX   8
 164 #define PIC_IRT_TIMER_5_INDEX   9
 165 #define PIC_IRT_TIMER_6_INDEX   10
 166 #define PIC_IRT_TIMER_7_INDEX   11
 167 #define PIC_IRT_CLOCK_INDEX     PIC_IRT_TIMER_7_INDEX
 168 #define PIC_IRT_TIMER_INDEX(num)        ((num) + PIC_IRT_TIMER_0_INDEX)
 169
 170 #define PIC_CLOCK_TIMER                 7
 171
 172 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
 173
 174 /*
 175  *   Misc
 176  */
 177 #define PIC_IRT_VALID                   1
 178 #define PIC_LOCAL_SCHEDULING            1
 179 #define PIC_GLOBAL_SCHEDULING           0
 180
 181 #define nlm_read_pic_reg(b, r)  nlm_read_reg64(b, r)
 182 #define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v)
 183 #define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node))
 184 #define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ)
 185
 186 /* IRT and h/w interrupt routines */
 187 static inline int
 188 nlm_pic_read_irt(uint64_t base, int irt_index)
 189 {
 190         return nlm_read_pic_reg(base, PIC_IRT(irt_index));
 191 }
 192
 193 static inline void
 194 nlm_pic_send_ipi(uint64_t base, int cpu, int vec, int nmi)
 195 {
 196         uint64_t ipi;
 197         int     node, ncpu;
 198
 199         node = cpu / 32;
 200         ncpu = cpu & 0x1f;
 201         ipi = ((uint64_t)nmi << 31) | (vec << 20) | (node << 17) |
 202                 (1 << (cpu & 0xf));
 203         if (ncpu > 15)
 204                 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */
 205
 206         nlm_write_pic_reg(base, PIC_IPI_CTL, ipi);
 207 }
 208
 209 static inline uint64_t
 210 nlm_pic_read_control(uint64_t base)
 211 {
 212         return nlm_read_pic_reg(base, PIC_CTRL);
 213 }
 214
 215 static inline void
 216 nlm_pic_write_control(uint64_t base, uint64_t control)
 217 {
 218         nlm_write_pic_reg(base, PIC_CTRL, control);
 219 }
 220
 221 static inline void
 222 nlm_pic_update_control(uint64_t base, uint64_t control)
 223 {
 224         uint64_t val;
 225
 226         val = nlm_read_pic_reg(base, PIC_CTRL);
 227         nlm_write_pic_reg(base, PIC_CTRL, control | val);
 228 }
 229
 230 static inline void
 231 nlm_pic_ack(uint64_t base, int irt_num)
 232 {
 233         nlm_write_pic_reg(base, PIC_INT_ACK, irt_num);
 234
 235         /* Ack the Status register for Watchdog & System timers */
 236         if (irt_num < 12)
 237                 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num));
 238 }
 239
 240 static inline void
 241 nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu)
 242 {
 243         uint64_t val;
 244
 245         val = nlm_read_pic_reg(base, PIC_IRT(irt));
 246         val |= cpu & 0xf;
 247         if (cpu > 15)
 248                 val |= 1 << 16;
 249         nlm_write_pic_reg(base, PIC_IRT(irt), val);
 250 }
 251
 252 static inline void
 253 nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi,
 254         int sch, int vec, int dt, int db, int dte)
 255 {
 256         uint64_t val;
 257
 258         val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) |
 259                         ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) |
 260                         ((dt & 0x1) << 19) | ((db & 0x7) << 16) |
 261                         (dte & 0xffff);
 262
 263         nlm_write_pic_reg(base, PIC_IRT(irt_num), val);
 264 }
 265
 266 static inline void
 267 nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi,
 268         int sch, int vec, int cpu)
 269 {
 270         nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1,
 271                 (cpu >> 4),             /* thread group */
 272                 1 << (cpu & 0xf));      /* thread mask */
 273 }
 274
 275 static inline uint64_t
 276 nlm_pic_read_timer(uint64_t base, int timer)
 277 {
 278         return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer));
 279 }
 280
 281 static inline void
 282 nlm_pic_write_timer(uint64_t base, int timer, uint64_t value)
 283 {
 284         nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value);
 285 }
 286
 287 static inline void
 288 nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu)
 289 {
 290         uint64_t pic_ctrl;
 291         int en, nmi;
 292
 293         en = nmi = 0;
 294         if (irq > 0)
 295                 en = 1;
 296         else if (irq < 0) {
 297                 en = nmi = 1;
 298                 irq = -irq;
 299         }
 300         nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value);
 301         nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer),
 302                 en, nmi, 0, irq, cpu);
 303
 304         /* enable the timer */
 305         pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL);
 306         pic_ctrl |= (1 << (PIC_CTRL_STE + timer));
 307         nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl);
 308 }
 309
 310 #endif /* __ASSEMBLY__ */
 311 #endif /* _NLM_HAL_PIC_H */