2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
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21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
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34 #ifndef __XLP_HAL_UART_H__
35 #define __XLP_HAL_UART_H__
37 /* UART Specific registers */
38 #define UART_RX_DATA 0x00
39 #define UART_TX_DATA 0x00
41 #define UART_INT_EN 0x01
42 #define UART_INT_ID 0x02
43 #define UART_FIFO_CTL 0x02
44 #define UART_LINE_CTL 0x03
45 #define UART_MODEM_CTL 0x04
46 #define UART_LINE_STS 0x05
47 #define UART_MODEM_STS 0x06
49 #define UART_DIVISOR0 0x00
50 #define UART_DIVISOR1 0x01
52 #define BASE_BAUD (XLP_IO_CLK/16)
53 #define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
56 #define LCR_5BITS 0x00
57 #define LCR_6BITS 0x01
58 #define LCR_7BITS 0x02
59 #define LCR_8BITS 0x03
60 #define LCR_STOPB 0x04
61 #define LCR_PENAB 0x08
63 #define LCR_PEVEN 0x10
65 #define LCR_PZERO 0x30
66 #define LCR_SBREAK 0x40
67 #define LCR_EFR_ENABLE 0xbf
75 #define MCR_LOOPBACK 0x10
78 #define FCR_RCV_RST 0x02
79 #define FCR_XMT_RST 0x04
80 #define FCR_RX_LOW 0x00
81 #define FCR_RX_MEDL 0x40
82 #define FCR_RX_MEDH 0x80
83 #define FCR_RX_HIGH 0xc0
86 #define IER_ERXRDY 0x1
87 #define IER_ETXRDY 0x2
91 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
93 #define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
94 #define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
95 #define nlm_get_uart_pcibase(node, inst) \
96 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
97 #define nlm_get_uart_regbase(node, inst) \
98 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
101 nlm_uart_set_baudrate(uint64_t base, int baud)
105 lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
107 /* enable divisor register, and write baud values */
108 nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
109 nlm_write_uart_reg(base, UART_DIVISOR0,
110 (BAUD_DIVISOR(baud) & 0xff));
111 nlm_write_uart_reg(base, UART_DIVISOR1,
112 ((BAUD_DIVISOR(baud) >> 8) & 0xff));
114 /* restore default lcr */
115 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
119 nlm_uart_outbyte(uint64_t base, char c)
124 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
129 nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
133 nlm_uart_inbyte(uint64_t base)
138 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
139 if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
143 if (lsr & 0x01) { /* Rx data */
144 data = nlm_read_uart_reg(base, UART_RX_DATA);
153 nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
154 int parity, int int_en, int loopback)
161 else if (databits == 7)
163 else if (databits == 6)
173 /* setup default lcr */
174 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
176 /* Reset the FIFOs */
177 nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
179 nlm_uart_set_baudrate(base, baud);
182 nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
185 nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
189 #endif /* !LOCORE && !__ASSEMBLY__ */
190 #endif /* __XLP_HAL_UART_H__ */