2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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6 * modification, are permitted provided that the following conditions are
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32 #ifndef __XLP_HAL_UART_H__
33 #define __XLP_HAL_UART_H__
35 /* UART Specific registers */
36 #define UART_RX_DATA 0x00
37 #define UART_TX_DATA 0x00
39 #define UART_INT_EN 0x01
40 #define UART_INT_ID 0x02
41 #define UART_FIFO_CTL 0x02
42 #define UART_LINE_CTL 0x03
43 #define UART_MODEM_CTL 0x04
44 #define UART_LINE_STS 0x05
45 #define UART_MODEM_STS 0x06
47 #define UART_DIVISOR0 0x00
48 #define UART_DIVISOR1 0x01
50 #define BASE_BAUD (XLP_IO_CLK/16)
51 #define BAUD_DIVISOR(baud) (BASE_BAUD / baud)
54 #define LCR_5BITS 0x00
55 #define LCR_6BITS 0x01
56 #define LCR_7BITS 0x02
57 #define LCR_8BITS 0x03
58 #define LCR_STOPB 0x04
59 #define LCR_PENAB 0x08
61 #define LCR_PEVEN 0x10
63 #define LCR_PZERO 0x30
64 #define LCR_SBREAK 0x40
65 #define LCR_EFR_ENABLE 0xbf
73 #define MCR_LOOPBACK 0x10
76 #define FCR_RCV_RST 0x02
77 #define FCR_XMT_RST 0x04
78 #define FCR_RX_LOW 0x00
79 #define FCR_RX_MEDL 0x40
80 #define FCR_RX_MEDH 0x80
81 #define FCR_RX_HIGH 0xc0
84 #define IER_ERXRDY 0x1
85 #define IER_ETXRDY 0x2
89 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
91 #define nlm_read_uart_reg(b, r) nlm_read_reg(b, r)
92 #define nlm_write_uart_reg(b, r, v) nlm_write_reg(b, r, v)
93 #define nlm_get_uart_pcibase(node, inst) \
94 nlm_pcicfg_base(XLP_IO_UART_OFFSET(node, inst))
95 #define nlm_get_uart_regbase(node, inst) \
96 (nlm_get_uart_pcibase(node, inst) + XLP_IO_PCI_HDRSZ)
99 nlm_uart_set_baudrate(uint64_t base, int baud)
103 lcr = nlm_read_uart_reg(base, UART_LINE_CTL);
105 /* enable divisor register, and write baud values */
106 nlm_write_uart_reg(base, UART_LINE_CTL, lcr | (1 << 7));
107 nlm_write_uart_reg(base, UART_DIVISOR0,
108 (BAUD_DIVISOR(baud) & 0xff));
109 nlm_write_uart_reg(base, UART_DIVISOR1,
110 ((BAUD_DIVISOR(baud) >> 8) & 0xff));
112 /* restore default lcr */
113 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
117 nlm_uart_outbyte(uint64_t base, char c)
122 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
127 nlm_write_uart_reg(base, UART_TX_DATA, (int)c);
131 nlm_uart_inbyte(uint64_t base)
136 lsr = nlm_read_uart_reg(base, UART_LINE_STS);
137 if (lsr & 0x80) { /* parity/frame/break-error - push a zero */
141 if (lsr & 0x01) { /* Rx data */
142 data = nlm_read_uart_reg(base, UART_RX_DATA);
151 nlm_uart_init(uint64_t base, int baud, int databits, int stopbits,
152 int parity, int int_en, int loopback)
159 else if (databits == 7)
161 else if (databits == 6)
171 /* setup default lcr */
172 nlm_write_uart_reg(base, UART_LINE_CTL, lcr);
174 /* Reset the FIFOs */
175 nlm_write_uart_reg(base, UART_LINE_CTL, FCR_RCV_RST | FCR_XMT_RST);
177 nlm_uart_set_baudrate(base, baud);
180 nlm_write_uart_reg(base, UART_MODEM_CTL, 0x1f);
183 nlm_write_uart_reg(base, UART_INT_EN, IER_ERXRDY | IER_ETXRDY);
187 #endif /* !LOCORE && !__ASSEMBLY__ */
188 #endif /* __XLP_HAL_UART_H__ */