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33 #ifndef __NLM_UCORE_LOADER_H__
34 #define __NLM_UCORE_LOADER_H__
37 * @file_name ucore_loader.h
38 * @author Netlogic Microsystems
39 * @brief Ucore loader API header
42 #define CODE_SIZE_PER_UCORE (4 << 10)
44 static __inline__ void
45 nlm_ucore_load_image(uint64_t nae_base, int ucore)
47 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET +
48 (ucore * CODE_SIZE_PER_UCORE);
49 uint32_t *p = (uint32_t *)ucore_app_bin;
52 size = sizeof(ucore_app_bin)/sizeof(uint32_t);
53 for (i = 0; i < size; i++, addr += 4)
54 nlm_store_word_daddr(addr, htobe32(p[i]));
56 /* add a 'nop' if number of instructions are odd */
58 nlm_store_word_daddr(addr, 0x0);
62 nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data)
65 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
70 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
71 /* set iram to zero */
72 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
73 (ucore_cfg & ~(0x1 << 7)));
75 nlm_store_word_daddr(addr + (index * 4), data);
77 /* restore ucore config */
78 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
82 static __inline uint32_t
83 nlm_ucore_read_sharedmem(uint64_t nae_base, int index)
85 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
86 uint32_t ucore_cfg, val;
88 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
89 /* set iram to zero */
90 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
91 (ucore_cfg & ~(0x1 << 7)));
93 val = nlm_load_word_daddr(addr + (index * 4));
95 /* restore ucore config */
96 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
101 static __inline__ int
102 nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done)
106 uint32_t ucore_cfg = 0;
108 mask = ucore_mask & 0xffff;
110 /* Stop all ucores */
111 if (nae_reset_done == 0) { /* Skip the Ucore reset if NAE reset is done */
112 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
113 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
114 ucore_cfg | (1 << 24));
116 /* poll for ucore to get in to a wait state */
118 ucore_cfg = nlm_read_nae_reg(nae_base,
120 } while ((ucore_cfg & (1 << 25)) == 0);
123 for (i = 0; i < sizeof(ucore_mask) * NBBY; i++) {
124 if ((mask & (1 << i)) == 0)
126 nlm_ucore_load_image(nae_base, i);
130 /* Enable per-domain ucores */
131 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
133 /* write one to reset bits to put the ucores in reset */
134 ucore_cfg = ucore_cfg | (((mask) & 0xffff) << 8);
135 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
137 /* write zero to reset bits to pull them out of reset */
138 ucore_cfg = ucore_cfg & (~(((mask) & 0xffff) << 8)) & ~(1 << 24);
139 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);