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31 #ifndef __NLM_UCORE_LOADER_H__
32 #define __NLM_UCORE_LOADER_H__
35 * @file_name ucore_loader.h
36 * @author Netlogic Microsystems
37 * @brief Ucore loader API header
40 #define CODE_SIZE_PER_UCORE (4 << 10)
42 static __inline__ void
43 nlm_ucore_load_image(uint64_t nae_base, int ucore)
45 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET +
46 (ucore * CODE_SIZE_PER_UCORE);
47 uint32_t *p = (uint32_t *)ucore_app_bin;
50 size = sizeof(ucore_app_bin)/sizeof(uint32_t);
51 for (i = 0; i < size; i++, addr += 4)
52 nlm_store_word_daddr(addr, htobe32(p[i]));
54 /* add a 'nop' if number of instructions are odd */
56 nlm_store_word_daddr(addr, 0x0);
60 nlm_ucore_write_sharedmem(uint64_t nae_base, int index, uint32_t data)
63 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
68 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
69 /* set iram to zero */
70 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
71 (ucore_cfg & ~(0x1 << 7)));
73 nlm_store_word_daddr(addr + (index * 4), data);
75 /* restore ucore config */
76 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
80 static __inline uint32_t
81 nlm_ucore_read_sharedmem(uint64_t nae_base, int index)
83 uint64_t addr = nae_base + NAE_UCORE_SHARED_RAM_OFFSET;
84 uint32_t ucore_cfg, val;
86 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
87 /* set iram to zero */
88 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
89 (ucore_cfg & ~(0x1 << 7)));
91 val = nlm_load_word_daddr(addr + (index * 4));
93 /* restore ucore config */
94 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
100 nlm_ucore_load_all(uint64_t nae_base, uint32_t ucore_mask, int nae_reset_done)
104 uint32_t ucore_cfg = 0;
106 mask = ucore_mask & 0xffff;
108 /* Stop all ucores */
109 if (nae_reset_done == 0) { /* Skip the Ucore reset if NAE reset is done */
110 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
111 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG,
112 ucore_cfg | (1 << 24));
114 /* poll for ucore to get in to a wait state */
116 ucore_cfg = nlm_read_nae_reg(nae_base,
118 } while ((ucore_cfg & (1 << 25)) == 0);
121 for (i = 0; i < sizeof(ucore_mask) * NBBY; i++) {
122 if ((mask & (1 << i)) == 0)
124 nlm_ucore_load_image(nae_base, i);
128 /* Enable per-domain ucores */
129 ucore_cfg = nlm_read_nae_reg(nae_base, NAE_RX_UCORE_CFG);
131 /* write one to reset bits to put the ucores in reset */
132 ucore_cfg = ucore_cfg | (((mask) & 0xffff) << 8);
133 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);
135 /* write zero to reset bits to pull them out of reset */
136 ucore_cfg = ucore_cfg & (~(((mask) & 0xffff) << 8)) & ~(1 << 24);
137 nlm_write_nae_reg(nae_base, NAE_RX_UCORE_CFG, ucore_cfg);