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32 #include <machine/asm.h>
33 #include <machine/cpu.h>
34 #include <machine/cpuregs.h>
35 #include <mips/nlm/hal/iomap.h>
36 #include <mips/nlm/hal/sys.h>
37 #include <mips/nlm/hal/cpucontrol.h>
39 #define SYS_REG_KSEG1(node, reg) (0xa0000000 + XLP_DEFAULT_IO_BASE + \
40 XLP_IO_SYS_OFFSET(node) + XLP_IO_PCI_HDRSZ + (reg) * 4)
48 #define MFCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x18))
49 #define MTCR(rt,rs) .word ((0x1c<<26)|((rs)<<21)|((rt)<<16)|(0x19))
51 * We need to do this to really flush the dcache before splitting it
53 .macro flush_l1_dcache
56 li $8, LSU_DEBUG_DATA0 /* use register number to handle */
57 li $9, LSU_DEBUG_ADDR /* different ABIs */
59 li t3, 0x1000 /* loop count, 512 sets * 8 whatever? */
63 ori v1, v0, 0x3 /* way0 | write_enable | write_active */
67 andi v1, 0x1 /* wait for write_active == 0 */
71 ori v1, v0, 0x7 /* way1 | write_enable | write_active */
75 andi v1, 0x1 /* wait for write_active == 0 */
84 VECTOR(XLPResetEntry, unknown)
85 mfc0 t0, MIPS_COP_0_STATUS
92 /* Reset entry for secordary cores */
93 mfc0 t0, MIPS_COP_0_PRID, 1
94 srl t0, t0, 2 /* discard thread id */
95 andi t0, t0, 0x7 /* core id */
98 nor t0, t0, zero /* mask with core id bit clear */
100 /* clear CPU non-coherent bit */
101 li t2, SYS_REG_KSEG1(0, SYS_CPU_NONCOHERENT_MODE)
105 lw t1, 0(t2) /* read-back ensures operation complete */
114 VECTOR_END(XLPResetEntry)
125 * Enable other threads in the core, called from thread 0
128 LEAF(xlp_enable_threads)
130 * Save and restore callee saved registers of all ABIs
131 * Enabling threads trashes the registers
133 dmtc0 sp, $4, 2 /* SP saved in UserLocal */
135 xori sp, sp, 0x7 /* align 64 bit */
137 mfc0 t1, MIPS_COP_0_STATUS
153 /* Use register number to work in o32 and n32 */
154 li $9, ((CPU_BLOCKID_MAP << 8) | MAP_THREADMODE)
158 mfc0 t0, MIPS_COP_0_PRID, 1
162 dla t1, mpentry /* child thread, go to hardware init */
168 * Parent hardware thread, restore registers, return
172 * A0 Errata - Write MMU_SETUP after changing thread mode register.
179 dmfc0 t0, $4, 2 /* SP saved in UserLocal */
181 xori sp, sp, 0x7 /* align 64 bit */
195 mfc0 t1, MIPS_COP_0_STATUS
197 move sp, t0 /* Restore the real SP */
200 END(xlp_enable_threads)