2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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31 * Simple driver for the 32-bit interval counter built in to all
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/sysctl.h>
42 #include <sys/kernel.h>
43 #include <sys/module.h>
45 #include <sys/power.h>
48 #include <sys/timeet.h>
49 #include <sys/timetc.h>
51 #include <machine/hwfunc.h>
52 #include <machine/clock.h>
53 #include <machine/locore.h>
54 #include <machine/md_var.h>
55 #include <machine/intr_machdep.h>
57 #include <mips/nlm/interrupt.h>
59 uint64_t counter_freq;
61 struct timecounter *platform_timecounter;
63 static DPCPU_DEFINE(uint32_t, cycles_per_tick);
64 static uint32_t cycles_per_usec;
66 static DPCPU_DEFINE(volatile uint32_t, counter_upper);
67 static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
68 static DPCPU_DEFINE(uint32_t, compare_ticks);
69 static DPCPU_DEFINE(uint32_t, lost_ticks);
73 struct resource *intr_res;
75 struct timecounter tc;
78 static struct clock_softc *softc;
83 static int clock_probe(device_t);
84 static void clock_identify(driver_t *, device_t);
85 static int clock_attach(device_t);
86 static unsigned counter_get_timecount(struct timecounter *tc);
89 mips_timer_early_init(uint64_t clock_hz)
91 /* Initialize clock early so that we can use DELAY sooner */
92 counter_freq = clock_hz;
93 cycles_per_usec = (clock_hz / (1000 * 1000));
97 platform_initclocks(void)
100 if (platform_timecounter != NULL)
101 tc_init(platform_timecounter);
109 uint32_t t_lower_last, t_upper;
112 * Disable preemption because we are working with cpu specific data.
117 * Note that even though preemption is disabled, interrupts are
118 * still enabled. In particular there is a race with clock_intr()
119 * reading the values of 'counter_upper' and 'counter_lower_last'.
121 * XXX this depends on clock_intr() being executed periodically
122 * so that 'counter_upper' and 'counter_lower_last' are not stale.
125 t_upper = DPCPU_GET(counter_upper);
126 t_lower_last = DPCPU_GET(counter_lower_last);
127 } while (t_upper != DPCPU_GET(counter_upper));
129 ticktock = mips_rd_count();
133 /* COUNT register wrapped around */
134 if (ticktock < t_lower_last)
137 ret = ((uint64_t)t_upper << 32) | ticktock;
142 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
146 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
147 * function should be called before cninit.
149 counter_freq = platform_counter_freq;
151 * XXX: Some MIPS32 cores update the Count register only every two
153 * We know this because of status registers in CP0, make it automatic.
155 if (double_count != 0)
158 cycles_per_usec = counter_freq / (1 * 1000 * 1000);
159 set_cputicker(tick_ticker, counter_freq, 1);
163 sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
171 error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
172 if (error == 0 && req->newptr != NULL) {
174 softc->et.et_frequency = counter_freq;
175 softc->tc.tc_frequency = counter_freq;
180 SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
181 NULL, 0, sysctl_machdep_counter_freq, "QU",
182 "Timecounter frequency in Hz");
185 counter_get_timecount(struct timecounter *tc)
188 return (mips_rd_count());
192 * Wait for about n microseconds (at least!).
197 uint32_t cur, last, delta, usecs;
200 * This works by polling the timer and counting the number of
201 * microseconds that go by.
203 last = mips_rd_count();
207 cur = mips_rd_count();
209 /* Check to see if the timer has wrapped around. */
211 delta += cur + (0xffffffff - last) + 1;
217 if (delta >= cycles_per_usec) {
218 usecs += delta / cycles_per_usec;
219 delta %= cycles_per_usec;
225 clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
227 uint32_t fdiv, div, next;
230 div = (et->et_frequency * period) >> 32;
234 fdiv = (et->et_frequency * first) >> 32;
237 DPCPU_SET(cycles_per_tick, div);
238 next = mips_rd_count() + fdiv;
239 DPCPU_SET(compare_ticks, next);
240 mips_wr_compare(next);
245 clock_stop(struct eventtimer *et)
248 DPCPU_SET(cycles_per_tick, 0);
249 mips_wr_compare(0xffffffff);
254 * Device section of file below
257 clock_intr(void *arg)
259 struct clock_softc *sc = (struct clock_softc *)arg;
260 uint32_t cycles_per_tick;
261 uint32_t count, compare_last, compare_next, lost_ticks;
263 cycles_per_tick = DPCPU_GET(cycles_per_tick);
265 * Set next clock edge.
267 count = mips_rd_count();
268 compare_last = DPCPU_GET(compare_ticks);
269 if (cycles_per_tick > 0) {
270 compare_next = count + cycles_per_tick;
271 DPCPU_SET(compare_ticks, compare_next);
272 mips_wr_compare(compare_next);
273 } else /* In one-shot mode timer should be stopped after the event. */
274 mips_wr_compare(0xffffffff);
276 /* COUNT register wrapped around */
277 if (count < DPCPU_GET(counter_lower_last)) {
278 DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
280 DPCPU_SET(counter_lower_last, count);
282 if (cycles_per_tick > 0) {
285 * Account for the "lost time" between when the timer interrupt
286 * fired and when 'clock_intr' actually started executing.
288 lost_ticks = DPCPU_GET(lost_ticks);
289 lost_ticks += count - compare_last;
292 * If the COUNT and COMPARE registers are no longer in sync
293 * then make up some reasonable value for the 'lost_ticks'.
295 * This could happen, for e.g., after we resume normal
296 * operations after exiting the debugger.
298 if (lost_ticks > 2 * cycles_per_tick)
299 lost_ticks = cycles_per_tick;
301 while (lost_ticks >= cycles_per_tick) {
302 if (sc->et.et_active)
303 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
304 lost_ticks -= cycles_per_tick;
306 DPCPU_SET(lost_ticks, lost_ticks);
308 if (sc->et.et_active)
309 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
310 return (FILTER_HANDLED);
314 clock_probe(device_t dev)
317 if (device_get_unit(dev) != 0)
318 panic("can't attach more clocks");
320 device_set_desc(dev, "Generic MIPS32 ticker");
325 clock_identify(driver_t * drv, device_t parent)
328 BUS_ADD_CHILD(parent, 0, "clock", 0);
332 clock_attach(device_t dev)
334 struct clock_softc *sc;
336 softc = sc = device_get_softc(dev);
337 cpu_establish_hardintr("compare", clock_intr, NULL,
338 sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
340 sc->tc.tc_get_timecount = counter_get_timecount;
341 sc->tc.tc_counter_mask = 0xffffffff;
342 sc->tc.tc_frequency = counter_freq;
343 sc->tc.tc_name = "MIPS32";
344 sc->tc.tc_quality = 800;
347 sc->et.et_name = "MIPS32";
349 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
352 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_PERCPU;
353 sc->et.et_quality = 800;
354 sc->et.et_frequency = counter_freq;
355 sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
356 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
357 sc->et.et_start = clock_start;
358 sc->et.et_stop = clock_stop;
360 et_register(&sc->et);
364 static device_method_t clock_methods[] = {
365 /* Device interface */
366 DEVMETHOD(device_probe, clock_probe),
367 DEVMETHOD(device_identify, clock_identify),
368 DEVMETHOD(device_attach, clock_attach),
369 DEVMETHOD(device_detach, bus_generic_detach),
370 DEVMETHOD(device_shutdown, bus_generic_shutdown),
375 static driver_t clock_driver = {
378 sizeof(struct clock_softc),
381 static devclass_t clock_devclass;
383 DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);