2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
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8 * modification, are permitted provided that the following conditions are
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33 * Simple driver for the 32-bit interval counter built in to all
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/sysctl.h>
44 #include <sys/kernel.h>
45 #include <sys/module.h>
47 #include <sys/power.h>
50 #include <sys/timeet.h>
51 #include <sys/timetc.h>
53 #include <machine/hwfunc.h>
54 #include <machine/clock.h>
55 #include <machine/locore.h>
56 #include <machine/md_var.h>
57 #include <machine/intr_machdep.h>
59 #include <mips/nlm/interrupt.h>
61 uint64_t counter_freq;
63 struct timecounter *platform_timecounter;
65 DPCPU_DEFINE_STATIC(uint32_t, cycles_per_tick);
66 static uint32_t cycles_per_usec;
68 DPCPU_DEFINE_STATIC(volatile uint32_t, counter_upper);
69 DPCPU_DEFINE_STATIC(volatile uint32_t, counter_lower_last);
70 DPCPU_DEFINE_STATIC(uint32_t, compare_ticks);
71 DPCPU_DEFINE_STATIC(uint32_t, lost_ticks);
75 struct resource *intr_res;
77 struct timecounter tc;
80 static struct clock_softc *softc;
85 static int clock_probe(device_t);
86 static void clock_identify(driver_t *, device_t);
87 static int clock_attach(device_t);
88 static unsigned counter_get_timecount(struct timecounter *tc);
91 mips_timer_early_init(uint64_t clock_hz)
93 /* Initialize clock early so that we can use DELAY sooner */
94 counter_freq = clock_hz;
95 cycles_per_usec = (clock_hz / (1000 * 1000));
99 platform_initclocks(void)
102 if (platform_timecounter != NULL)
103 tc_init(platform_timecounter);
111 uint32_t t_lower_last, t_upper;
114 * Disable preemption because we are working with cpu specific data.
119 * Note that even though preemption is disabled, interrupts are
120 * still enabled. In particular there is a race with clock_intr()
121 * reading the values of 'counter_upper' and 'counter_lower_last'.
123 * XXX this depends on clock_intr() being executed periodically
124 * so that 'counter_upper' and 'counter_lower_last' are not stale.
127 t_upper = DPCPU_GET(counter_upper);
128 t_lower_last = DPCPU_GET(counter_lower_last);
129 } while (t_upper != DPCPU_GET(counter_upper));
131 ticktock = mips_rd_count();
135 /* COUNT register wrapped around */
136 if (ticktock < t_lower_last)
139 ret = ((uint64_t)t_upper << 32) | ticktock;
144 mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
148 * XXX: Do not use printf here: uart code 8250 may use DELAY so this
149 * function should be called before cninit.
151 counter_freq = platform_counter_freq;
153 * XXX: Some MIPS32 cores update the Count register only every two
155 * We know this because of status registers in CP0, make it automatic.
157 if (double_count != 0)
160 cycles_per_usec = counter_freq / (1 * 1000 * 1000);
161 set_cputicker(tick_ticker, counter_freq, 1);
165 sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
173 error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
174 if (error == 0 && req->newptr != NULL) {
176 softc->et.et_frequency = counter_freq;
177 softc->tc.tc_frequency = counter_freq;
182 SYSCTL_PROC(_machdep, OID_AUTO, counter_freq,
183 CTLTYPE_U64 | CTLFLAG_RW | CTLFLAG_NEEDGIANT, NULL, 0,
184 sysctl_machdep_counter_freq, "QU",
185 "Timecounter frequency in Hz");
188 counter_get_timecount(struct timecounter *tc)
191 return (mips_rd_count());
195 * Wait for about n microseconds (at least!).
200 uint32_t cur, last, delta, usecs;
204 * This works by polling the timer and counting the number of
205 * microseconds that go by.
207 last = mips_rd_count();
211 cur = mips_rd_count();
213 /* Check to see if the timer has wrapped around. */
215 delta += cur + (0xffffffff - last) + 1;
221 if (delta >= cycles_per_usec) {
222 usecs += delta / cycles_per_usec;
223 delta %= cycles_per_usec;
230 clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
232 uint32_t fdiv, div, next;
235 div = (et->et_frequency * period) >> 32;
239 fdiv = (et->et_frequency * first) >> 32;
242 DPCPU_SET(cycles_per_tick, div);
243 next = mips_rd_count() + fdiv;
244 DPCPU_SET(compare_ticks, next);
245 mips_wr_compare(next);
250 clock_stop(struct eventtimer *et)
253 DPCPU_SET(cycles_per_tick, 0);
254 mips_wr_compare(0xffffffff);
259 * Device section of file below
262 clock_intr(void *arg)
264 struct clock_softc *sc = (struct clock_softc *)arg;
265 uint32_t cycles_per_tick;
266 uint32_t count, compare_last, compare_next, lost_ticks;
268 cycles_per_tick = DPCPU_GET(cycles_per_tick);
270 * Set next clock edge.
272 count = mips_rd_count();
273 compare_last = DPCPU_GET(compare_ticks);
274 if (cycles_per_tick > 0) {
275 compare_next = count + cycles_per_tick;
276 DPCPU_SET(compare_ticks, compare_next);
277 mips_wr_compare(compare_next);
278 } else /* In one-shot mode timer should be stopped after the event. */
279 mips_wr_compare(0xffffffff);
281 /* COUNT register wrapped around */
282 if (count < DPCPU_GET(counter_lower_last)) {
283 DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
285 DPCPU_SET(counter_lower_last, count);
287 if (cycles_per_tick > 0) {
289 * Account for the "lost time" between when the timer interrupt
290 * fired and when 'clock_intr' actually started executing.
292 lost_ticks = DPCPU_GET(lost_ticks);
293 lost_ticks += count - compare_last;
296 * If the COUNT and COMPARE registers are no longer in sync
297 * then make up some reasonable value for the 'lost_ticks'.
299 * This could happen, for e.g., after we resume normal
300 * operations after exiting the debugger.
302 if (lost_ticks > 2 * cycles_per_tick)
303 lost_ticks = cycles_per_tick;
305 while (lost_ticks >= cycles_per_tick) {
306 if (sc->et.et_active)
307 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
308 lost_ticks -= cycles_per_tick;
310 DPCPU_SET(lost_ticks, lost_ticks);
312 if (sc->et.et_active)
313 sc->et.et_event_cb(&sc->et, sc->et.et_arg);
314 return (FILTER_HANDLED);
318 clock_probe(device_t dev)
321 device_set_desc(dev, "Generic MIPS32 ticker");
322 return (BUS_PROBE_NOWILDCARD);
326 clock_identify(driver_t * drv, device_t parent)
329 BUS_ADD_CHILD(parent, 0, "clock", 0);
333 clock_attach(device_t dev)
335 struct clock_softc *sc;
337 if (device_get_unit(dev) != 0)
338 panic("can't attach more clocks");
340 softc = sc = device_get_softc(dev);
341 cpu_establish_hardintr("compare", clock_intr, NULL,
342 sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
344 sc->tc.tc_get_timecount = counter_get_timecount;
345 sc->tc.tc_counter_mask = 0xffffffff;
346 sc->tc.tc_frequency = counter_freq;
347 sc->tc.tc_name = "MIPS32";
348 sc->tc.tc_quality = 800;
351 sc->et.et_name = "MIPS32";
353 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
356 sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_PERCPU;
357 sc->et.et_quality = 800;
358 sc->et.et_frequency = counter_freq;
359 sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
360 sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
361 sc->et.et_start = clock_start;
362 sc->et.et_stop = clock_stop;
364 et_register(&sc->et);
368 static device_method_t clock_methods[] = {
369 /* Device interface */
370 DEVMETHOD(device_probe, clock_probe),
371 DEVMETHOD(device_identify, clock_identify),
372 DEVMETHOD(device_attach, clock_attach),
373 DEVMETHOD(device_detach, bus_generic_detach),
374 DEVMETHOD(device_shutdown, bus_generic_shutdown),
378 static driver_t clock_driver = {
381 sizeof(struct clock_softc),
384 static devclass_t clock_devclass;
386 DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);