2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
4 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
18 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
21 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28 * THE POSSIBILITY OF SUCH DAMAGE.
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
36 #include "opt_platform.h"
38 #include <sys/param.h>
41 #include <sys/rtprio.h>
42 #include <sys/systm.h>
43 #include <sys/interrupt.h>
44 #include <sys/limits.h>
46 #include <sys/malloc.h>
47 #include <sys/mutex.h>
48 #include <sys/random.h>
50 #include <sys/cons.h> /* cinit() */
53 #include <sys/reboot.h>
54 #include <sys/queue.h>
56 #include <sys/timetc.h>
59 #include <vm/vm_page.h>
61 #include <machine/cpu.h>
62 #include <machine/cpufunc.h>
63 #include <machine/cpuinfo.h>
64 #include <machine/tlb.h>
65 #include <machine/cpuregs.h>
66 #include <machine/frame.h>
67 #include <machine/hwfunc.h>
68 #include <machine/md_var.h>
69 #include <machine/asm.h>
70 #include <machine/pmap.h>
71 #include <machine/trap.h>
72 #include <machine/clock.h>
73 #include <machine/fls64.h>
74 #include <machine/intr_machdep.h>
75 #include <machine/smp.h>
77 #include <mips/nlm/hal/mips-extns.h>
78 #include <mips/nlm/hal/haldefs.h>
79 #include <mips/nlm/hal/iomap.h>
80 #include <mips/nlm/hal/sys.h>
81 #include <mips/nlm/hal/pic.h>
82 #include <mips/nlm/hal/uart.h>
83 #include <mips/nlm/hal/mmu.h>
84 #include <mips/nlm/hal/bridge.h>
85 #include <mips/nlm/hal/cpucontrol.h>
86 #include <mips/nlm/hal/cop2.h>
88 #include <mips/nlm/clock.h>
89 #include <mips/nlm/interrupt.h>
90 #include <mips/nlm/board.h>
91 #include <mips/nlm/xlp.h>
92 #include <mips/nlm/msgring.h>
95 #include <dev/fdt/fdt_common.h>
96 #include <dev/ofw/openfirm.h>
99 /* 4KB static data aread to keep a copy of the bootload env until
100 the dynamic kenv is setup */
101 char boot1_env[4096];
103 uint64_t xlp_cpu_frequency;
104 uint64_t xlp_io_base = MIPS_PHYS_TO_DIRECT_UNCACHED(XLP_DEFAULT_IO_BASE);
107 int xlp_threads_per_core;
108 uint32_t xlp_hw_thread_mask;
109 int xlp_cpuid_to_hwtid[MAXCPU];
110 int xlp_hwtid_to_cpuid[MAXCPU];
111 uint64_t xlp_pic_base;
113 static int xlp_mmuval;
115 extern uint32_t _end;
116 extern char XLPResetEntry[], XLPResetEntryEnd[];
123 reg = nlm_mfcr(LSU_DEFEATURE);
124 /* Enable Unaligned and L2HPE */
125 reg |= (1 << 30) | (1 << 23);
127 * Experimental : Enable SUE
128 * Speculative Unmap Enable. Enable speculative L2 cache request for
132 /* Clear S1RCM - A0 errata */
134 nlm_mtcr(LSU_DEFEATURE, reg);
136 reg = nlm_mfcr(SCHED_DEFEATURE);
137 /* Experimental: Disable BRU accepting ALU ops - A0 errata */
139 nlm_mtcr(SCHED_DEFEATURE, reg);
147 if (nlm_threadid() == 0) {
148 nlm_setup_extended_pagemask(0);
149 nlm_large_variable_tlb_en(1);
150 nlm_extended_tlb_en(1);
151 nlm_mmu_setup(0, 0, 0);
154 /* Enable no-read, no-exec, large-physical-address */
155 pagegrain = mips_rd_pagegrain();
156 pagegrain |= (1U << 31) | /* RIE */
157 (1 << 30) | /* XIE */
158 (1 << 29); /* ELPA */
159 mips_wr_pagegrain(pagegrain);
163 xlp_enable_blocks(void)
168 for (i = 0; i < XLP_MAX_NODES; i++) {
169 if (!nlm_dev_exists(XLP_IO_SYS_OFFSET(i)))
171 sysbase = nlm_get_sys_regbase(i);
172 nlm_sys_enable_block(sysbase, DFS_DEVICE_RSA);
177 xlp_parse_mmu_options(void)
180 uint32_t cpu_map = xlp_hw_thread_mask;
181 uint32_t core0_thr_mask, core_thr_mask, cpu_rst_mask;
186 cpu_map = 0xffffffff;
187 #else /* Uniprocessor! */
190 else if (cpu_map != 0x1) {
191 printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n"
192 "WARNING: Other CPUs will be unused.\n", (u_long)cpu_map);
198 core0_thr_mask = cpu_map & 0xf;
199 switch (core0_thr_mask) {
201 xlp_threads_per_core = 1;
205 xlp_threads_per_core = 2;
209 xlp_threads_per_core = 4;
216 /* Try to find the enabled cores from SYS block */
217 sysbase = nlm_get_sys_regbase(0);
218 cpu_rst_mask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET) & 0xff;
220 /* XLP 416 does not report this correctly, fix */
221 if (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_416)
224 /* Take out cores which do not exist on chip */
225 for (i = 1; i < XLP_MAX_CORES; i++) {
226 if ((cpu_rst_mask & (1 << i)) == 0)
227 cpu_map &= ~(0xfu << (4 * i));
230 /* Verify other cores' CPU masks */
231 for (i = 1; i < XLP_MAX_CORES; i++) {
232 core_thr_mask = (cpu_map >> (4 * i)) & 0xf;
233 if (core_thr_mask == 0)
235 if (core_thr_mask != core0_thr_mask)
240 xlp_hw_thread_mask = cpu_map;
241 /* setup hardware processor id to cpu id mapping */
242 for (i = 0; i< MAXCPU; i++)
243 xlp_cpuid_to_hwtid[i] =
244 xlp_hwtid_to_cpuid[i] = -1;
245 for (i = 0, k = 0; i < XLP_MAX_CORES; i++) {
246 if (((cpu_map >> (i * 4)) & 0xf) == 0)
248 for (j = 0; j < xlp_threads_per_core; j++) {
249 xlp_cpuid_to_hwtid[k] = i * 4 + j;
250 xlp_hwtid_to_cpuid[i * 4 + j] = k;
258 printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
259 "\tcore0 thread mask [%lx], boot cpu mask [%lx].\n",
260 (u_long)core0_thr_mask, (u_long)cpu_map);
261 panic("Invalid CPU mask - halting.\n");
267 xlp_bootargs_init(__register_t arg)
269 char buf[2048]; /* early stack is big enough */
274 dtbp = (void *)(intptr_t)arg;
275 #if defined(FDT_DTB_STATIC)
277 * In case the device tree blob was not passed as argument try
278 * to use the statically embedded one.
281 dtbp = &fdt_static_dtb;
283 if (OF_install(OFW_FDT, 0) == FALSE)
285 if (OF_init((void *)dtbp) != 0)
287 OF_interpret("perform-fixup", 0);
289 chosen = OF_finddevice("/chosen");
290 if (OF_getprop(chosen, "cpumask", &mask, sizeof(mask)) != -1) {
291 xlp_hw_thread_mask = mask;
294 if (OF_getprop(chosen, "bootargs", buf, sizeof(buf)) != -1)
295 boothowto |= boot_parse_cmdline(buf);
299 * arg is a pointer to the environment block, the format of the block is
303 xlp_bootargs_init(__register_t arg)
305 char buf[2048]; /* early stack is big enough */
310 * provide backward compat for passing cpu mask as arg
313 xlp_hw_thread_mask = arg;
317 p = (void *)(intptr_t)arg;
319 strlcpy(buf, p, sizeof(buf));
329 /* CPU mask can be passed thru env */
330 if (getenv_uint("cpumask", &mask) != 0)
331 xlp_hw_thread_mask = mask;
333 /* command line argument */
334 v = kern_getenv("bootargs");
336 strlcpy(buf, v, sizeof(buf));
337 boothowto |= boot_parse_cmdline(buf);
347 init_param2(physmem);
350 cpuinfo.cache_coherent_dma = TRUE;
356 if (boothowto & RB_KDB) {
357 kdb_enter("Boot flags requested debugger", NULL);
363 platform_get_timecount(struct timecounter *tc __unused)
365 uint64_t count = nlm_pic_read_timer(xlp_pic_base, PIC_CLOCK_TIMER);
367 return (unsigned int)~count;
373 struct timecounter pic_timecounter = {
374 platform_get_timecount, /* get_timecount */
376 ~0U, /* counter_mask */
377 XLP_IO_CLK, /* frequency */
379 2000, /* quality (adjusted in code) */
384 xlp_pic_base = nlm_get_pic_regbase(0); /* TOOD: Add other nodes */
385 maxirt = nlm_read_reg(nlm_get_pic_pcibase(nlm_nodeid()),
386 XLP_PCI_DEVINFO_REG0);
387 printf("Initializing PIC...@%jx %d IRTs\n", (uintmax_t)xlp_pic_base,
389 /* Bind all PIC irqs to cpu 0 */
390 for (i = 0; i < maxirt; i++)
391 nlm_pic_write_irt(xlp_pic_base, i, 0, 0, 1, 0,
394 nlm_pic_set_timer(xlp_pic_base, PIC_CLOCK_TIMER, ~0ULL, 0, 0);
395 platform_timecounter = &pic_timecounter;
398 #if defined(__mips_n32) || defined(__mips_n64) /* PHYSADDR_64_BIT */
400 #define XLP_MEM_LIM 0x200000000ULL
402 #define XLP_MEM_LIM 0x10000000000ULL
405 #define XLP_MEM_LIM 0xfffff000UL
407 static vm_paddr_t xlp_mem_excl[] = {
408 0, 0, /* for kernel image region, see xlp_mem_init */
409 0x0c000000, 0x14000000, /* uboot area, cms queue and other stuff */
410 0x1fc00000, 0x1fd00000, /* reset vec */
411 0x1e000000, 0x1e200000, /* poe buffers */
415 mem_exclude_add(vm_paddr_t *avail, vm_paddr_t mstart, vm_paddr_t mend)
420 for (i = 0; i < nitems(xlp_mem_excl); i += 2) {
421 if (mstart > xlp_mem_excl[i + 1])
423 if (mstart < xlp_mem_excl[i]) {
424 avail[pos++] = mstart;
425 if (mend < xlp_mem_excl[i])
428 avail[pos++] = xlp_mem_excl[i];
430 mstart = xlp_mem_excl[i + 1];
435 avail[pos++] = mstart;
444 vm_paddr_t physsz, tmp;
445 uint64_t bridgebase, base, lim, val;
448 /* update kernel image area in exclude regions */
449 tmp = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(&_end);
450 tmp = round_page(tmp) + 0x20000; /* round up */
451 xlp_mem_excl[1] = tmp;
453 printf("Memory (from DRAM BARs):\n");
454 bridgebase = nlm_get_bridge_regbase(0); /* TODO: Add other nodes */
456 for (i = 0, j = 0; i < 8; i++) {
457 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
458 val = (val >> 12) & 0xfffff;
460 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
461 val = (val >> 12) & 0xfffff;
462 if (val == 0) /* BAR not enabled */
464 lim = (val + 1) << 20;
465 printf(" BAR %d: %#jx - %#jx : ", i, (intmax_t)base,
469 printf("\tskipped - malformed %#jx -> %#jx\n",
470 (intmax_t)base, (intmax_t)lim);
472 } else if (base >= XLP_MEM_LIM) {
473 printf(" skipped - outside usable limit %#jx.\n",
474 (intmax_t)XLP_MEM_LIM);
476 } else if (lim >= XLP_MEM_LIM) {
478 printf(" truncated to %#jx.\n", (intmax_t)XLP_MEM_LIM);
482 /* exclude unusable regions from BAR and add rest */
483 n = mem_exclude_add(&phys_avail[j], base, lim);
484 for (k = j; k < j + n; k += 2) {
485 physsz += phys_avail[k + 1] - phys_avail[k];
486 printf("\tMem[%d]: %#jx - %#jx\n", k/2,
487 (intmax_t)phys_avail[k], (intmax_t)phys_avail[k+1]);
492 /* setup final entry with 0 */
493 phys_avail[j] = phys_avail[j + 1] = 0;
495 /* copy phys_avail to dump_avail */
496 for (i = 0; i <= j + 1; i++)
497 dump_avail[i] = phys_avail[i];
499 realmem = physmem = btoc(physsz);
503 platform_start(__register_t a0 __unused,
504 __register_t a1 __unused,
505 __register_t a2 __unused,
506 __register_t a3 __unused)
509 /* Initialize pcpu stuff */
512 /* initialize console so that we have printf */
513 boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
515 init_static_kenv(boot1_env, sizeof(boot1_env));
516 xlp_bootargs_init(a0);
518 /* clockrate used by delay, so initialize it here */
519 xlp_cpu_frequency = xlp_get_cpu_frequency(0, 0);
520 cpu_clock = xlp_cpu_frequency / 1000000;
521 mips_timer_early_init(xlp_cpu_frequency);
523 /* Init console please */
526 /* Early core init and fixes for errata */
529 xlp_parse_mmu_options();
532 bcopy(XLPResetEntry, (void *)MIPS_RESET_EXC_VEC,
533 XLPResetEntryEnd - XLPResetEntry);
536 * We will enable the other threads in core 0 here
537 * so that the TLB and cache info is correct when
540 xlp_enable_threads(xlp_mmuval);
542 /* setup for the startup core */
547 /* Read/Guess/setup board information */
548 nlm_board_info_setup();
550 /* MIPS generic init */
554 * XLP specific post initialization
555 * initialize other on chip stuff
559 mips_timer_init_params(xlp_cpu_frequency, 0);
570 uint64_t sysbase = nlm_get_sys_regbase(0);
572 nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
574 __asm __volatile("wait");
579 * XLP threads are started simultaneously when we enable threads, this will
580 * ensure that the threads are blocked in platform_init_ap, until they are
581 * ready to proceed to smp_init_secondary()
583 static volatile int thr_unblock[4];
586 platform_start_ap(int cpuid)
588 uint32_t coremask, val;
589 uint64_t sysbase = nlm_get_sys_regbase(0);
590 int hwtid = xlp_cpuid_to_hwtid[cpuid];
596 /* First thread in core, do core wake up */
597 coremask = 1u << core;
599 /* Enable core clock */
600 val = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
602 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, val);
604 /* Remove CPU Reset */
605 val = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
606 val &= ~coremask & 0xff;
607 nlm_write_sys_reg(sysbase, SYS_CPU_RESET, val);
610 printf("Waking up core %d ...", core);
612 /* Poll for CPU to mark itself coherent */
614 val = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
615 } while ((val & coremask) != 0);
619 /* otherwise release the threads stuck in platform_init_ap */
620 thr_unblock[thr] = 1;
627 platform_init_ap(int cpuid)
632 /* The first thread has to setup the MMU and enable other threads */
633 thr = nlm_threadid();
636 xlp_enable_threads(xlp_mmuval);
639 * FIXME busy wait here eats too many cycles, especially
640 * in the core 0 while bootup
642 while (thr_unblock[thr] == 0)
643 __asm__ __volatile__ ("nop;nop;nop;nop");
644 thr_unblock[thr] = 0;
648 stat = mips_rd_status();
649 KASSERT((stat & MIPS_SR_INT_IE) == 0,
650 ("Interrupts enabled in %s!", __func__));
651 stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
652 mips_wr_status(stat);
654 nlm_write_c0_eimr(0ull);
655 xlp_enable_irq(IRQ_IPI);
656 xlp_enable_irq(IRQ_TIMER);
657 xlp_enable_irq(IRQ_MSGRING);
663 platform_ipi_hardintr_num(void)
670 platform_ipi_softintr_num(void)
677 platform_ipi_send(int cpuid)
680 nlm_pic_send_ipi(xlp_pic_base, xlp_cpuid_to_hwtid[cpuid],
681 platform_ipi_hardintr_num(), 0);
685 platform_ipi_clear(void)
690 platform_processor_id(void)
693 return (xlp_hwtid_to_cpuid[nlm_cpuid()]);
697 platform_cpu_mask(cpuset_t *mask)
702 s = xlp_ncores * xlp_threads_per_core;
703 for (i = 0; i < s; i++)
711 return (smp_topo_2level(CG_SHARE_L2, xlp_ncores, CG_SHARE_L1,
712 xlp_threads_per_core, CG_FLAG_THREAD));