2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE
20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
26 * THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 #include "opt_platform.h"
36 #include <sys/param.h>
39 #include <sys/rtprio.h>
40 #include <sys/systm.h>
41 #include <sys/interrupt.h>
42 #include <sys/limits.h>
44 #include <sys/malloc.h>
45 #include <sys/mutex.h>
46 #include <sys/random.h>
48 #include <sys/cons.h> /* cinit() */
50 #include <sys/reboot.h>
51 #include <sys/queue.h>
53 #include <sys/timetc.h>
56 #include <vm/vm_page.h>
58 #include <machine/cpu.h>
59 #include <machine/cpufunc.h>
60 #include <machine/cpuinfo.h>
61 #include <machine/tlb.h>
62 #include <machine/cpuregs.h>
63 #include <machine/frame.h>
64 #include <machine/hwfunc.h>
65 #include <machine/md_var.h>
66 #include <machine/asm.h>
67 #include <machine/pmap.h>
68 #include <machine/trap.h>
69 #include <machine/clock.h>
70 #include <machine/fls64.h>
71 #include <machine/intr_machdep.h>
72 #include <machine/smp.h>
74 #include <mips/nlm/hal/mips-extns.h>
75 #include <mips/nlm/hal/haldefs.h>
76 #include <mips/nlm/hal/iomap.h>
77 #include <mips/nlm/hal/sys.h>
78 #include <mips/nlm/hal/pic.h>
79 #include <mips/nlm/hal/uart.h>
80 #include <mips/nlm/hal/mmu.h>
81 #include <mips/nlm/hal/bridge.h>
82 #include <mips/nlm/hal/cpucontrol.h>
83 #include <mips/nlm/hal/cop2.h>
85 #include <mips/nlm/clock.h>
86 #include <mips/nlm/interrupt.h>
87 #include <mips/nlm/board.h>
88 #include <mips/nlm/xlp.h>
89 #include <mips/nlm/msgring.h>
92 #include <dev/fdt/fdt_common.h>
93 #include <dev/ofw/openfirm.h>
96 /* 4KB static data aread to keep a copy of the bootload env until
97 the dynamic kenv is setup */
100 uint64_t xlp_cpu_frequency;
101 uint64_t xlp_io_base = MIPS_PHYS_TO_DIRECT_UNCACHED(XLP_DEFAULT_IO_BASE);
104 int xlp_threads_per_core;
105 uint32_t xlp_hw_thread_mask;
106 int xlp_cpuid_to_hwtid[MAXCPU];
107 int xlp_hwtid_to_cpuid[MAXCPU];
108 uint64_t xlp_pic_base;
110 static int xlp_mmuval;
112 extern uint32_t _end;
113 extern char XLPResetEntry[], XLPResetEntryEnd[];
120 reg = nlm_mfcr(LSU_DEFEATURE);
121 /* Enable Unaligned and L2HPE */
122 reg |= (1 << 30) | (1 << 23);
124 * Experimental : Enable SUE
125 * Speculative Unmap Enable. Enable speculative L2 cache request for
129 /* Clear S1RCM - A0 errata */
131 nlm_mtcr(LSU_DEFEATURE, reg);
133 reg = nlm_mfcr(SCHED_DEFEATURE);
134 /* Experimental: Disable BRU accepting ALU ops - A0 errata */
136 nlm_mtcr(SCHED_DEFEATURE, reg);
144 if (nlm_threadid() == 0) {
145 nlm_setup_extended_pagemask(0);
146 nlm_large_variable_tlb_en(1);
147 nlm_extended_tlb_en(1);
148 nlm_mmu_setup(0, 0, 0);
151 /* Enable no-read, no-exec, large-physical-address */
152 pagegrain = mips_rd_pagegrain();
153 pagegrain |= (1U << 31) | /* RIE */
154 (1 << 30) | /* XIE */
155 (1 << 29); /* ELPA */
156 mips_wr_pagegrain(pagegrain);
160 xlp_enable_blocks(void)
165 for (i = 0; i < XLP_MAX_NODES; i++) {
166 if (!nlm_dev_exists(XLP_IO_SYS_OFFSET(i)))
168 sysbase = nlm_get_sys_regbase(i);
169 nlm_sys_enable_block(sysbase, DFS_DEVICE_RSA);
174 xlp_parse_mmu_options(void)
177 uint32_t cpu_map = xlp_hw_thread_mask;
178 uint32_t core0_thr_mask, core_thr_mask, cpu_rst_mask;
183 cpu_map = 0xffffffff;
184 #else /* Uniprocessor! */
187 else if (cpu_map != 0x1) {
188 printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n"
189 "WARNING: Other CPUs will be unused.\n", (u_long)cpu_map);
195 core0_thr_mask = cpu_map & 0xf;
196 switch (core0_thr_mask) {
198 xlp_threads_per_core = 1;
202 xlp_threads_per_core = 2;
206 xlp_threads_per_core = 4;
213 /* Try to find the enabled cores from SYS block */
214 sysbase = nlm_get_sys_regbase(0);
215 cpu_rst_mask = nlm_read_sys_reg(sysbase, SYS_CPU_RESET) & 0xff;
217 /* XLP 416 does not report this correctly, fix */
218 if (nlm_processor_id() == CHIP_PROCESSOR_ID_XLP_416)
221 /* Take out cores which do not exist on chip */
222 for (i = 1; i < XLP_MAX_CORES; i++) {
223 if ((cpu_rst_mask & (1 << i)) == 0)
224 cpu_map &= ~(0xfu << (4 * i));
227 /* Verify other cores' CPU masks */
228 for (i = 1; i < XLP_MAX_CORES; i++) {
229 core_thr_mask = (cpu_map >> (4 * i)) & 0xf;
230 if (core_thr_mask == 0)
232 if (core_thr_mask != core0_thr_mask)
237 xlp_hw_thread_mask = cpu_map;
238 /* setup hardware processor id to cpu id mapping */
239 for (i = 0; i< MAXCPU; i++)
240 xlp_cpuid_to_hwtid[i] =
241 xlp_hwtid_to_cpuid[i] = -1;
242 for (i = 0, k = 0; i < XLP_MAX_CORES; i++) {
243 if (((cpu_map >> (i * 4)) & 0xf) == 0)
245 for (j = 0; j < xlp_threads_per_core; j++) {
246 xlp_cpuid_to_hwtid[k] = i * 4 + j;
247 xlp_hwtid_to_cpuid[i * 4 + j] = k;
255 printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
256 "\tcore0 thread mask [%lx], boot cpu mask [%lx].\n",
257 (u_long)core0_thr_mask, (u_long)cpu_map);
258 panic("Invalid CPU mask - halting.\n");
262 /* Parse cmd line args as env - copied from ar71xx */
264 xlp_parse_bootargs(char *cmdline)
268 while ((v = strsep(&cmdline, " \n")) != NULL) {
275 case 'a': boothowto |= RB_ASKNAME; break;
276 case 'd': boothowto |= RB_KDB; break;
277 case 'g': boothowto |= RB_GDB; break;
278 case 's': boothowto |= RB_SINGLE; break;
279 case 'v': boothowto |= RB_VERBOSE; break;
294 xlp_bootargs_init(__register_t arg)
296 char buf[2048]; /* early stack is big enough */
301 dtbp = (void *)(intptr_t)arg;
302 #if defined(FDT_DTB_STATIC)
304 * In case the device tree blob was not passed as argument try
305 * to use the statically embedded one.
308 dtbp = &fdt_static_dtb;
310 if (OF_install(OFW_FDT, 0) == FALSE)
312 if (OF_init((void *)dtbp) != 0)
314 OF_interpret("perform-fixup", 0);
316 chosen = OF_finddevice("/chosen");
317 if (OF_getprop(chosen, "cpumask", &mask, sizeof(mask)) != -1) {
318 xlp_hw_thread_mask = mask;
321 if (OF_getprop(chosen, "bootargs", buf, sizeof(buf)) != -1)
322 xlp_parse_bootargs(buf);
326 * arg is a pointer to the environment block, the format of the block is
330 xlp_bootargs_init(__register_t arg)
332 char buf[2048]; /* early stack is big enough */
337 * provide backward compat for passing cpu mask as arg
340 xlp_hw_thread_mask = arg;
344 p = (void *)(intptr_t)arg;
346 strlcpy(buf, p, sizeof(buf));
356 /* CPU mask can be passed thru env */
357 if (getenv_uint("cpumask", &mask) != 0)
358 xlp_hw_thread_mask = mask;
360 /* command line argument */
361 v = kern_getenv("bootargs");
363 strlcpy(buf, v, sizeof(buf));
364 xlp_parse_bootargs(buf);
374 init_param2(physmem);
377 cpuinfo.cache_coherent_dma = TRUE;
383 if (boothowto & RB_KDB) {
384 kdb_enter("Boot flags requested debugger", NULL);
390 platform_get_timecount(struct timecounter *tc __unused)
392 uint64_t count = nlm_pic_read_timer(xlp_pic_base, PIC_CLOCK_TIMER);
394 return (unsigned int)~count;
400 struct timecounter pic_timecounter = {
401 platform_get_timecount, /* get_timecount */
403 ~0U, /* counter_mask */
404 XLP_IO_CLK, /* frequency */
406 2000, /* quality (adjusted in code) */
411 xlp_pic_base = nlm_get_pic_regbase(0); /* TOOD: Add other nodes */
412 maxirt = nlm_read_reg(nlm_get_pic_pcibase(nlm_nodeid()),
413 XLP_PCI_DEVINFO_REG0);
414 printf("Initializing PIC...@%jx %d IRTs\n", (uintmax_t)xlp_pic_base,
416 /* Bind all PIC irqs to cpu 0 */
417 for (i = 0; i < maxirt; i++)
418 nlm_pic_write_irt(xlp_pic_base, i, 0, 0, 1, 0,
421 nlm_pic_set_timer(xlp_pic_base, PIC_CLOCK_TIMER, ~0ULL, 0, 0);
422 platform_timecounter = &pic_timecounter;
425 #if defined(__mips_n32) || defined(__mips_n64) /* PHYSADDR_64_BIT */
427 #define XLP_MEM_LIM 0x200000000ULL
429 #define XLP_MEM_LIM 0x10000000000ULL
432 #define XLP_MEM_LIM 0xfffff000UL
434 static vm_paddr_t xlp_mem_excl[] = {
435 0, 0, /* for kernel image region, see xlp_mem_init */
436 0x0c000000, 0x14000000, /* uboot area, cms queue and other stuff */
437 0x1fc00000, 0x1fd00000, /* reset vec */
438 0x1e000000, 0x1e200000, /* poe buffers */
442 mem_exclude_add(vm_paddr_t *avail, vm_paddr_t mstart, vm_paddr_t mend)
447 for (i = 0; i < nitems(xlp_mem_excl); i += 2) {
448 if (mstart > xlp_mem_excl[i + 1])
450 if (mstart < xlp_mem_excl[i]) {
451 avail[pos++] = mstart;
452 if (mend < xlp_mem_excl[i])
455 avail[pos++] = xlp_mem_excl[i];
457 mstart = xlp_mem_excl[i + 1];
462 avail[pos++] = mstart;
471 vm_paddr_t physsz, tmp;
472 uint64_t bridgebase, base, lim, val;
475 /* update kernel image area in exclude regions */
476 tmp = (vm_paddr_t)MIPS_KSEG0_TO_PHYS(&_end);
477 tmp = round_page(tmp) + 0x20000; /* round up */
478 xlp_mem_excl[1] = tmp;
480 printf("Memory (from DRAM BARs):\n");
481 bridgebase = nlm_get_bridge_regbase(0); /* TODO: Add other nodes */
483 for (i = 0, j = 0; i < 8; i++) {
484 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_BAR(i));
485 val = (val >> 12) & 0xfffff;
487 val = nlm_read_bridge_reg(bridgebase, BRIDGE_DRAM_LIMIT(i));
488 val = (val >> 12) & 0xfffff;
489 if (val == 0) /* BAR not enabled */
491 lim = (val + 1) << 20;
492 printf(" BAR %d: %#jx - %#jx : ", i, (intmax_t)base,
496 printf("\tskipped - malformed %#jx -> %#jx\n",
497 (intmax_t)base, (intmax_t)lim);
499 } else if (base >= XLP_MEM_LIM) {
500 printf(" skipped - outside usable limit %#jx.\n",
501 (intmax_t)XLP_MEM_LIM);
503 } else if (lim >= XLP_MEM_LIM) {
505 printf(" truncated to %#jx.\n", (intmax_t)XLP_MEM_LIM);
509 /* exclude unusable regions from BAR and add rest */
510 n = mem_exclude_add(&phys_avail[j], base, lim);
511 for (k = j; k < j + n; k += 2) {
512 physsz += phys_avail[k + 1] - phys_avail[k];
513 printf("\tMem[%d]: %#jx - %#jx\n", k/2,
514 (intmax_t)phys_avail[k], (intmax_t)phys_avail[k+1]);
519 /* setup final entry with 0 */
520 phys_avail[j] = phys_avail[j + 1] = 0;
522 /* copy phys_avail to dump_avail */
523 for (i = 0; i <= j + 1; i++)
524 dump_avail[i] = phys_avail[i];
526 realmem = physmem = btoc(physsz);
530 platform_start(__register_t a0 __unused,
531 __register_t a1 __unused,
532 __register_t a2 __unused,
533 __register_t a3 __unused)
536 /* Initialize pcpu stuff */
539 /* initialize console so that we have printf */
540 boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
542 init_static_kenv(boot1_env, sizeof(boot1_env));
543 xlp_bootargs_init(a0);
545 /* clockrate used by delay, so initialize it here */
546 xlp_cpu_frequency = xlp_get_cpu_frequency(0, 0);
547 cpu_clock = xlp_cpu_frequency / 1000000;
548 mips_timer_early_init(xlp_cpu_frequency);
550 /* Init console please */
553 /* Early core init and fixes for errata */
556 xlp_parse_mmu_options();
559 bcopy(XLPResetEntry, (void *)MIPS_RESET_EXC_VEC,
560 XLPResetEntryEnd - XLPResetEntry);
563 * We will enable the other threads in core 0 here
564 * so that the TLB and cache info is correct when
567 xlp_enable_threads(xlp_mmuval);
569 /* setup for the startup core */
574 /* Read/Guess/setup board information */
575 nlm_board_info_setup();
577 /* MIPS generic init */
581 * XLP specific post initialization
582 * initialize other on chip stuff
586 mips_timer_init_params(xlp_cpu_frequency, 0);
597 uint64_t sysbase = nlm_get_sys_regbase(0);
599 nlm_write_sys_reg(sysbase, SYS_CHIP_RESET, 1);
601 __asm __volatile("wait");
606 * XLP threads are started simultaneously when we enable threads, this will
607 * ensure that the threads are blocked in platform_init_ap, until they are
608 * ready to proceed to smp_init_secondary()
610 static volatile int thr_unblock[4];
613 platform_start_ap(int cpuid)
615 uint32_t coremask, val;
616 uint64_t sysbase = nlm_get_sys_regbase(0);
617 int hwtid = xlp_cpuid_to_hwtid[cpuid];
623 /* First thread in core, do core wake up */
624 coremask = 1u << core;
626 /* Enable core clock */
627 val = nlm_read_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL);
629 nlm_write_sys_reg(sysbase, SYS_CORE_DFS_DIS_CTRL, val);
631 /* Remove CPU Reset */
632 val = nlm_read_sys_reg(sysbase, SYS_CPU_RESET);
633 val &= ~coremask & 0xff;
634 nlm_write_sys_reg(sysbase, SYS_CPU_RESET, val);
637 printf("Waking up core %d ...", core);
639 /* Poll for CPU to mark itself coherent */
641 val = nlm_read_sys_reg(sysbase, SYS_CPU_NONCOHERENT_MODE);
642 } while ((val & coremask) != 0);
646 /* otherwise release the threads stuck in platform_init_ap */
647 thr_unblock[thr] = 1;
654 platform_init_ap(int cpuid)
659 /* The first thread has to setup the MMU and enable other threads */
660 thr = nlm_threadid();
663 xlp_enable_threads(xlp_mmuval);
666 * FIXME busy wait here eats too many cycles, especially
667 * in the core 0 while bootup
669 while (thr_unblock[thr] == 0)
670 __asm__ __volatile__ ("nop;nop;nop;nop");
671 thr_unblock[thr] = 0;
675 stat = mips_rd_status();
676 KASSERT((stat & MIPS_SR_INT_IE) == 0,
677 ("Interrupts enabled in %s!", __func__));
678 stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
679 mips_wr_status(stat);
681 nlm_write_c0_eimr(0ull);
682 xlp_enable_irq(IRQ_IPI);
683 xlp_enable_irq(IRQ_TIMER);
684 xlp_enable_irq(IRQ_MSGRING);
690 platform_ipi_hardintr_num(void)
697 platform_ipi_softintr_num(void)
704 platform_ipi_send(int cpuid)
707 nlm_pic_send_ipi(xlp_pic_base, xlp_cpuid_to_hwtid[cpuid],
708 platform_ipi_hardintr_num(), 0);
712 platform_ipi_clear(void)
717 platform_processor_id(void)
720 return (xlp_hwtid_to_cpuid[nlm_cpuid()]);
724 platform_cpu_mask(cpuset_t *mask)
729 s = xlp_ncores * xlp_threads_per_core;
730 for (i = 0; i < s; i++)
738 return (smp_topo_2level(CG_SHARE_L2, xlp_ncores, CG_SHARE_L1,
739 xlp_threads_per_core, CG_FLAG_THREAD));