2 * Copyright (c) 2003-2012 Broadcom Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in
13 * the documentation and/or other materials provided with the
16 * THIS SOFTWARE IS PROVIDED BY BROADCOM ``AS IS'' AND ANY EXPRESS OR
17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
34 #include <sys/types.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/malloc.h>
39 #include <sys/endian.h>
41 #include <sys/pciio.h>
44 #include <vm/vm_param.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pci_private.h>
51 #include <dev/uart/uart.h>
52 #include <dev/uart/uart_bus.h>
53 #include <dev/uart/uart_cpu.h>
55 #include <machine/bus.h>
56 #include <machine/md_var.h>
57 #include <machine/intr_machdep.h>
58 #include <machine/cpuregs.h>
60 #include <mips/nlm/hal/haldefs.h>
61 #include <mips/nlm/interrupt.h>
62 #include <mips/nlm/hal/iomap.h>
63 #include <mips/nlm/hal/mips-extns.h>
64 #include <mips/nlm/hal/pic.h>
65 #include <mips/nlm/hal/bridge.h>
66 #include <mips/nlm/hal/gbu.h>
67 #include <mips/nlm/hal/pcibus.h>
68 #include <mips/nlm/hal/uart.h>
69 #include <mips/nlm/xlp.h>
74 #define EMUL_MEM_START 0x16000000UL
75 #define EMUL_MEM_END 0x18ffffffUL
77 /* SoC device qurik handling */
78 static int irt_irq_map[4 * 256];
79 static int irq_irt_map[64];
82 xlp_add_irq(int node, int irt, int irq)
84 int nodeirt = node * 256 + irt;
86 irt_irq_map[nodeirt] = irq;
87 irq_irt_map[irq] = nodeirt;
91 xlp_irq_to_irt(int irq)
93 return irq_irt_map[irq];
97 xlp_irt_to_irq(int nodeirt)
99 return irt_irq_map[nodeirt];
102 /* Override PCI a bit for SoC devices */
105 INTERNAL_DEV = 0x1, /* internal device, skip on enumeration */
106 MEM_RES_EMUL = 0x2, /* no MEM or IO bar, custom res alloc */
108 DEV_MMIO32 = 0x8, /* byte access not allowed to mmio */
111 struct soc_dev_desc {
112 u_int devid; /* device ID */
113 int irqbase; /* start IRQ */
114 u_int flags; /* flags */
115 int ndevs; /* to keep track of number of devices */
118 struct soc_dev_desc xlp_dev_desc[] = {
119 { PCI_DEVICE_ID_NLM_ICI, 0, INTERNAL_DEV },
120 { PCI_DEVICE_ID_NLM_PIC, 0, INTERNAL_DEV },
121 { PCI_DEVICE_ID_NLM_FMN, 0, INTERNAL_DEV },
122 { PCI_DEVICE_ID_NLM_UART, PIC_UART_0_IRQ, MEM_RES_EMUL | DEV_MMIO32},
123 { PCI_DEVICE_ID_NLM_I2C, 0, MEM_RES_EMUL | DEV_MMIO32 },
124 { PCI_DEVICE_ID_NLM_NOR, 0, MEM_RES_EMUL },
125 { PCI_DEVICE_ID_NLM_MMC, PIC_MMC_IRQ, MEM_RES_EMUL },
126 { PCI_DEVICE_ID_NLM_EHCI, PIC_EHCI_0_IRQ, 0 }
130 struct pci_devinfo pcidev;
133 u_long mem_res_start;
136 static __inline struct soc_dev_desc *
137 xlp_find_soc_desc(int devid)
139 struct soc_dev_desc *p;
142 n = sizeof(xlp_dev_desc) / sizeof(xlp_dev_desc[0]);
143 for (i = 0, p = xlp_dev_desc; i < n; i++, p++)
144 if (p->devid == devid)
149 static struct resource *
150 xlp_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
151 u_long start, u_long end, u_long count, u_int flags)
154 struct xlp_devinfo *xlp_devinfo;
158 * Do custom allocation for MEMORY resource for SoC device if
159 * MEM_RES_EMUL flag is set
161 busno = pci_get_bus(child);
162 if ((type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) && busno == 0) {
163 xlp_devinfo = (struct xlp_devinfo *)device_get_ivars(child);
164 if ((xlp_devinfo->flags & MEM_RES_EMUL) != 0) {
165 /* no emulation for IO ports */
166 if (type == SYS_RES_IOPORT)
169 start = xlp_devinfo->mem_res_start;
170 count = XLP_PCIE_CFG_SIZE - XLP_IO_PCI_HDRSZ;
172 /* MMC needs to 2 slots with rids 16 and 20 and a
174 if (pci_get_device(child) == PCI_DEVICE_ID_NLM_MMC) {
177 ; /* first slot already setup */
179 start += 0x100; /* second slot */
184 end = start + count - 1;
185 r = BUS_ALLOC_RESOURCE(device_get_parent(bus), child,
186 type, rid, start, end, count, flags);
189 if ((xlp_devinfo->flags & DEV_MMIO32) != 0)
190 rman_set_bustag(r, rmi_uart_bus_space);
195 /* Not custom alloc, use PCI code */
196 return (pci_alloc_resource(bus, child, type, rid, start, end, count,
201 xlp_pci_release_resource(device_t bus, device_t child, int type, int rid,
206 /* If custom alloc, handle that */
207 start = rman_get_start(r);
208 if (type == SYS_RES_MEMORY && pci_get_bus(child) == 0 &&
209 start >= EMUL_MEM_START && start <= EMUL_MEM_END)
210 return (BUS_RELEASE_RESOURCE(device_get_parent(bus), child,
213 /* use default PCI function */
214 return (bus_generic_rl_release_resource(bus, child, type, rid, r));
218 xlp_add_soc_child(device_t pcib, device_t dev, int b, int s, int f)
220 struct pci_devinfo *dinfo;
221 struct xlp_devinfo *xlp_dinfo;
222 struct soc_dev_desc *si;
224 int domain, node, irt, irq, flags, devoffset, num;
227 domain = pcib_get_domain(dev);
229 devoffset = XLP_HDR_OFFSET(node, 0, s % 8, f);
230 if (!nlm_dev_exists(devoffset))
233 /* Find if there is a desc for the SoC device */
234 devid = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_DEVICE, 2);
235 si = xlp_find_soc_desc(devid);
237 /* update flags and irq from desc if available */
241 if (si->irqbase != 0)
242 irq = si->irqbase + si->ndevs;
247 /* skip internal devices */
248 if ((flags & INTERNAL_DEV) != 0)
251 /* PCIe interfaces are special, bug in Ax */
252 if (devid == PCI_DEVICE_ID_NLM_PCIE) {
253 xlp_add_irq(node, xlp_pcie_link_irt(f), PIC_PCIE_0_IRQ + f);
255 /* Stash intline and pin in shadow reg for devices */
256 pcibase = nlm_pcicfg_base(devoffset);
257 irt = nlm_irtstart(pcibase);
258 num = nlm_irtnum(pcibase);
259 if (irq != 0 && num > 0) {
260 xlp_add_irq(node, irt, irq);
261 nlm_write_reg(pcibase, XLP_PCI_DEVSCRATCH_REG0,
265 dinfo = pci_read_device(pcib, domain, b, s, f, sizeof(*xlp_dinfo));
268 xlp_dinfo = (struct xlp_devinfo *)dinfo;
269 xlp_dinfo->irq = irq;
270 xlp_dinfo->flags = flags;
272 /* memory resource from ecfg space, if MEM_RES_EMUL is set */
273 if ((flags & MEM_RES_EMUL) != 0)
274 xlp_dinfo->mem_res_start = XLP_DEFAULT_IO_BASE + devoffset +
276 pci_add_child(dev, dinfo);
280 xlp_pci_attach(device_t dev)
282 device_t pcib = device_get_parent(dev);
283 int maxslots, s, f, pcifunchigh;
288 * The on-chip devices are on a bus that is almost, but not
289 * quite, completely like PCI. Add those things by hand.
291 busno = pcib_get_bus(dev);
292 maxslots = PCIB_MAXSLOTS(pcib);
293 for (s = 0; s <= maxslots; s++) {
296 hdrtype = PCIB_READ_CONFIG(pcib, busno, s, f, PCIR_HDRTYPE, 1);
297 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
299 if (hdrtype & PCIM_MFDEV)
300 pcifunchigh = PCI_FUNCMAX;
301 for (f = 0; f <= pcifunchigh; f++)
302 xlp_add_soc_child(pcib, dev, busno, s, f);
304 return (bus_generic_attach(dev));
308 xlp_pci_probe(device_t dev)
312 pcib = device_get_parent(dev);
314 * Only the top level bus has SoC devices, leave the rest to
317 if (strcmp(device_get_nameunit(pcib), "pcib0") != 0)
319 device_set_desc(dev, "XLP SoCbus");
320 return (BUS_PROBE_DEFAULT);
323 static devclass_t pci_devclass;
324 static device_method_t xlp_pci_methods[] = {
325 /* Device interface */
326 DEVMETHOD(device_probe, xlp_pci_probe),
327 DEVMETHOD(device_attach, xlp_pci_attach),
328 DEVMETHOD(bus_alloc_resource, xlp_pci_alloc_resource),
329 DEVMETHOD(bus_release_resource, xlp_pci_release_resource),
334 DEFINE_CLASS_1(pci, xlp_pci_driver, xlp_pci_methods, sizeof(struct pci_softc),
336 DRIVER_MODULE(xlp_pci, pcib, xlp_pci_driver, pci_devclass, 0, 0);
338 static devclass_t pcib_devclass;
339 static struct rman irq_rman, port_rman, mem_rman, emul_rman;
342 xlp_pcib_init_resources(void)
344 irq_rman.rm_start = 0;
345 irq_rman.rm_end = 255;
346 irq_rman.rm_type = RMAN_ARRAY;
347 irq_rman.rm_descr = "PCI Mapped Interrupts";
348 if (rman_init(&irq_rman)
349 || rman_manage_region(&irq_rman, 0, 255))
350 panic("pci_init_resources irq_rman");
352 port_rman.rm_start = 0;
353 port_rman.rm_end = ~0ul;
354 port_rman.rm_type = RMAN_ARRAY;
355 port_rman.rm_descr = "I/O ports";
356 if (rman_init(&port_rman)
357 || rman_manage_region(&port_rman, PCIE_IO_BASE, PCIE_IO_LIMIT))
358 panic("pci_init_resources port_rman");
360 mem_rman.rm_start = 0;
361 mem_rman.rm_end = ~0ul;
362 mem_rman.rm_type = RMAN_ARRAY;
363 mem_rman.rm_descr = "I/O memory";
364 if (rman_init(&mem_rman)
365 || rman_manage_region(&mem_rman, PCIE_MEM_BASE, PCIE_MEM_LIMIT))
366 panic("pci_init_resources mem_rman");
369 * This includes the GBU (nor flash) memory range and the PCIe
372 emul_rman.rm_start = 0;
373 emul_rman.rm_end = ~0ul;
374 emul_rman.rm_type = RMAN_ARRAY;
375 emul_rman.rm_descr = "Emulated MEMIO";
376 if (rman_init(&emul_rman)
377 || rman_manage_region(&emul_rman, EMUL_MEM_START, EMUL_MEM_END))
378 panic("pci_init_resources emul_rman");
382 xlp_pcib_probe(device_t dev)
385 device_set_desc(dev, "XLP PCI bus");
386 xlp_pcib_init_resources();
391 xlp_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
395 case PCIB_IVAR_DOMAIN:
406 xlp_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
409 case PCIB_IVAR_DOMAIN:
418 xlp_pcib_maxslots(device_t dev)
421 return (PCI_SLOTMAX);
425 xlp_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
426 u_int reg, int width)
430 int regindex = reg/sizeof(uint32_t);
432 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
433 if ((width == 2) && (reg & 1))
435 else if ((width == 4) && (reg & 3))
439 * The intline and int pin of SoC devices are DOA, except
440 * for bridges (slot %8 == 1).
441 * use the values we stashed in a writable PCI scratch reg.
443 if (b == 0 && regindex == 0xf && s % 8 > 1)
444 regindex = XLP_PCI_DEVSCRATCH_REG0;
446 data = nlm_read_pci_reg(cfgaddr, regindex);
448 return ((data >> ((reg & 3) << 3)) & 0xff);
450 return ((data >> ((reg & 3) << 3)) & 0xffff);
456 xlp_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
457 u_int reg, u_int32_t val, int width)
461 int regindex = reg / sizeof(uint32_t);
463 cfgaddr = nlm_pcicfg_base(XLP_HDR_OFFSET(0, b, s, f));
464 if ((width == 2) && (reg & 1))
466 else if ((width == 4) && (reg & 3))
470 data = nlm_read_pci_reg(cfgaddr, regindex);
471 data = (data & ~(0xff << ((reg & 3) << 3))) |
472 (val << ((reg & 3) << 3));
473 } else if (width == 2) {
474 data = nlm_read_pci_reg(cfgaddr, regindex);
475 data = (data & ~(0xffff << ((reg & 3) << 3))) |
476 (val << ((reg & 3) << 3));
482 * use shadow reg for intpin/intline which are dead
484 if (b == 0 && regindex == 0xf && s % 8 > 1)
485 regindex = XLP_PCI_DEVSCRATCH_REG0;
486 nlm_write_pci_reg(cfgaddr, regindex, data);
490 * Enable byte swap in hardware when compiled big-endian.
491 * Programs a link's PCIe SWAP regions from the link's IO and MEM address
495 xlp_pcib_hardware_swap_enable(int node, int link)
497 #if BYTE_ORDER == BIG_ENDIAN
498 uint64_t bbase, linkpcibase;
502 pcieoffset = XLP_IO_PCIE_OFFSET(node, link);
503 if (!nlm_dev_exists(pcieoffset))
506 bbase = nlm_get_bridge_regbase(node);
507 linkpcibase = nlm_pcicfg_base(pcieoffset);
508 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_BASE0 + link);
509 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar);
511 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link);
512 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF);
514 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link);
515 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar);
517 bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link);
518 nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF);
523 xlp_pcib_attach(device_t dev)
527 /* enable hardware swap on all nodes/links */
528 for (node = 0; node < XLP_MAX_NODES; node++)
529 for (link = 0; link < 4; link++)
530 xlp_pcib_hardware_swap_enable(node, link);
532 device_add_child(dev, "pci", 0);
533 bus_generic_attach(dev);
538 xlp_pcib_identify(driver_t * driver, device_t parent)
541 BUS_ADD_CHILD(parent, 0, "pcib", 0);
545 * XLS PCIe can have upto 4 links, and each link has its on IRQ
546 * Find the link on which the device is on
549 xlp_pcie_link(device_t pcib, device_t dev)
551 device_t parent, tmp;
553 /* find the lane on which the slot is connected to */
556 parent = device_get_parent(tmp);
557 if (parent == NULL || parent == pcib) {
558 device_printf(dev, "Cannot find parent bus\n");
561 if (strcmp(device_get_nameunit(parent), "pci0") == 0)
565 return (pci_get_function(tmp));
569 xlp_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
574 * Each link has 32 MSIs that can be allocated, but for now
575 * we only support one device per link.
576 * msi_alloc() equivalent is needed when we start supporting
577 * bridges on the PCIe link.
579 link = xlp_pcie_link(pcib, dev);
584 * encode the irq so that we know it is a MSI interrupt when we
587 for (i = 0; i < count; i++)
588 irqs[i] = 64 + link * 32 + i;
594 xlp_release_msi(device_t pcib, device_t dev, int count, int *irqs)
600 xlp_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
607 *addr = MIPS_MSI_ADDR(0);
609 irt = xlp_pcie_link_irt(msi/32);
611 *data = MIPS_MSI_DATA(xlp_irt_to_irq(irt));
614 device_printf(dev, "%s: map_msi for irq %d - ignored",
615 device_get_nameunit(pcib), irq);
621 bridge_pcie_ack(int irq)
627 reg = PCIE_MSI_STATUS;
631 base = nlm_pcicfg_base(XLP_IO_PCIE0_OFFSET(node));
634 base = nlm_pcicfg_base(XLP_IO_PCIE1_OFFSET(node));
637 base = nlm_pcicfg_base(XLP_IO_PCIE2_OFFSET(node));
640 base = nlm_pcicfg_base(XLP_IO_PCIE3_OFFSET(node));
646 nlm_write_pci_reg(base, reg, 0xFFFFFFFF);
651 mips_platform_pcib_setup_intr(device_t dev, device_t child,
652 struct resource *irq, int flags, driver_filter_t *filt,
653 driver_intr_t *intr, void *arg, void **cookiep)
659 error = rman_activate_resource(irq);
662 if (rman_get_start(irq) != rman_get_end(irq)) {
663 device_printf(dev, "Interrupt allocation %lu != %lu\n",
664 rman_get_start(irq), rman_get_end(irq));
667 xlpirq = rman_get_start(irq);
671 if (strcmp(device_get_name(dev), "pcib") != 0)
675 * temporary hack for MSI, we support just one device per
676 * link, and assign the link interrupt to the device interrupt
683 if (xlpirq % 32 != 0)
688 base = nlm_pcicfg_base(XLP_IO_PCIE_OFFSET(node,link));
690 /* MSI Interrupt Vector enable at bridge's configuration */
691 nlm_write_pci_reg(base, PCIE_MSI_EN, PCIE_MSI_VECTOR_INT_EN);
693 val = nlm_read_pci_reg(base, PCIE_INT_EN0);
694 /* MSI Interrupt enable at bridge's configuration */
695 nlm_write_pci_reg(base, PCIE_INT_EN0,
696 (val | PCIE_MSI_INT_EN));
698 /* legacy interrupt disable at bridge */
699 val = nlm_read_pci_reg(base, PCIE_BRIDGE_CMD);
700 nlm_write_pci_reg(base, PCIE_BRIDGE_CMD,
701 (val | PCIM_CMD_INTxDIS));
703 /* MSI address update at bridge */
704 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRL,
706 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_ADDRH, 0);
708 val = nlm_read_pci_reg(base, PCIE_BRIDGE_MSI_CAP);
709 /* MSI capability enable at bridge */
710 nlm_write_pci_reg(base, PCIE_BRIDGE_MSI_CAP,
711 (val | (PCIM_MSICTRL_MSI_ENABLE << 16) |
712 (PCIM_MSICTRL_MMC_32 << 16)));
714 xlpirq = xlp_pcie_link_irt(xlpirq / 32);
717 xlpirq = xlp_irt_to_irq(xlpirq);
719 /* Set all irqs to CPU 0 for now */
720 nlm_pic_write_irt_direct(xlp_pic_base, xlp_irq_to_irt(xlpirq), 1, 0,
721 PIC_LOCAL_SCHEDULING, xlpirq, 0);
723 if (xlpirq >= PIC_PCIE_0_IRQ && xlpirq <= PIC_PCIE_3_IRQ)
724 extra_ack = bridge_pcie_ack;
725 xlp_establish_intr(device_get_name(child), filt,
726 intr, arg, xlpirq, flags, cookiep, extra_ack);
732 mips_platform_pcib_teardown_intr(device_t dev, device_t child,
733 struct resource *irq, void *cookie)
735 if (strcmp(device_get_name(child), "pci") == 0) {
736 /* if needed reprogram the pic to clear pcix related entry */
737 device_printf(dev, "teardown intr\n");
739 return (bus_generic_teardown_intr(dev, child, irq, cookie));
742 static struct resource *
743 xlp_pcib_alloc_resource(device_t bus, device_t child, int type, int *rid,
744 u_long start, u_long end, u_long count, u_int flags)
746 struct rman *rm = NULL;
749 int needactivate = flags & RF_ACTIVE;
761 if (start >= EMUL_MEM_START && start <= EMUL_MEM_END)
771 rv = rman_reserve_resource(rm, start, end, count, flags, child);
775 rman_set_rid(rv, *rid);
777 if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
778 va = pmap_mapdev(start, count);
779 rman_set_bushandle(rv, (bus_space_handle_t)va);
780 rman_set_bustag(rv, rmi_bus_space);
783 if (bus_activate_resource(child, type, *rid, rv)) {
784 rman_release_resource(rv);
792 xlp_pcib_release_resource(device_t bus, device_t child, int type, int rid,
796 return (rman_release_resource(r));
800 xlp_pcib_activate_resource(device_t bus, device_t child, int type, int rid,
804 return (rman_activate_resource(r));
808 xlp_pcib_deactivate_resource(device_t bus, device_t child, int type, int rid,
812 return (rman_deactivate_resource(r));
816 mips_pcib_route_interrupt(device_t bus, device_t dev, int pin)
821 * Validate requested pin number.
823 if ((pin < 1) || (pin > 4))
826 if (pci_get_bus(dev) == 0 &&
827 pci_get_vendor(dev) == PCI_VENDOR_NETLOGIC) {
832 f = pci_get_function(dev);
833 n = pci_get_slot(dev) / 8;
834 d = pci_get_slot(dev) % 8;
837 * For PCIe links, return link IRT, for other SoC devices
838 * get the IRT from its PCIe header
841 irt = xlp_pcie_link_irt(f);
843 pcibase = nlm_pcicfg_base(XLP_HDR_OFFSET(n, 0, d, f));
844 irt = nlm_irtstart(pcibase);
845 num = nlm_irtnum(pcibase);
847 device_printf(bus, "[%d:%d:%d] Error %d IRQs\n",
851 /* Regular PCI devices */
852 link = xlp_pcie_link(bus, dev);
853 irt = xlp_pcie_link_irt(link);
857 return (xlp_irt_to_irq(irt));
862 static device_method_t xlp_pcib_methods[] = {
863 /* Device interface */
864 DEVMETHOD(device_identify, xlp_pcib_identify),
865 DEVMETHOD(device_probe, xlp_pcib_probe),
866 DEVMETHOD(device_attach, xlp_pcib_attach),
869 DEVMETHOD(bus_read_ivar, xlp_pcib_read_ivar),
870 DEVMETHOD(bus_write_ivar, xlp_pcib_write_ivar),
871 DEVMETHOD(bus_alloc_resource, xlp_pcib_alloc_resource),
872 DEVMETHOD(bus_release_resource, xlp_pcib_release_resource),
873 DEVMETHOD(bus_activate_resource, xlp_pcib_activate_resource),
874 DEVMETHOD(bus_deactivate_resource, xlp_pcib_deactivate_resource),
875 DEVMETHOD(bus_setup_intr, mips_platform_pcib_setup_intr),
876 DEVMETHOD(bus_teardown_intr, mips_platform_pcib_teardown_intr),
879 DEVMETHOD(pcib_maxslots, xlp_pcib_maxslots),
880 DEVMETHOD(pcib_read_config, xlp_pcib_read_config),
881 DEVMETHOD(pcib_write_config, xlp_pcib_write_config),
882 DEVMETHOD(pcib_route_interrupt, mips_pcib_route_interrupt),
884 DEVMETHOD(pcib_alloc_msi, xlp_alloc_msi),
885 DEVMETHOD(pcib_release_msi, xlp_release_msi),
886 DEVMETHOD(pcib_map_msi, xlp_map_msi),
891 static driver_t xlp_pcib_driver = {
897 DRIVER_MODULE(pcib, nexus, xlp_pcib_driver, pcib_devclass, 0, 0);