sys/mips/rmi/board.c

   1 /*********************************************************************
   2  *
   3  * Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
   4  * reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  *
  10  * 1. Redistributions of source code must retain the above copyright
  11  * notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  * notice, this list of conditions and the following disclaimer in
  14  * the documentation and/or other materials provided with the
  15  * distribution.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  20  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  23  * SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
  24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  27  * THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * *****************************RMI_2**********************************/
  30 #include <sys/cdefs.h>          /* RCS ID & Copyright macro defns */
  31 __FBSDID("$FreeBSD$");
  32 #include <sys/param.h>
  33 #include <sys/systm.h>
  34 #include <sys/bus.h>
  35 #include <sys/kernel.h>
  36 #include <sys/lock.h>
  37 #include <sys/mutex.h>
  38
  39 #include <machine/cpufunc.h>
  40 #include <mips/rmi/msgring.h>
  41 #include <mips/rmi/rmi_boot_info.h>
  42 #include <mips/rmi/board.h>
  43 #include <mips/rmi/pic.h>
  44
  45 struct stn_cc *xlr_core_cc_configs[] = { &cc_table_cpu_0, &cc_table_cpu_1,
  46     &cc_table_cpu_2, &cc_table_cpu_3, &cc_table_cpu_4, &cc_table_cpu_5,
  47     &cc_table_cpu_6, &cc_table_cpu_7};
  48
  49 struct stn_cc *xls_core_cc_configs[] = { &xls_cc_table_cpu_0, &xls_cc_table_cpu_1,
  50    &xls_cc_table_cpu_2, &xls_cc_table_cpu_3 };
  51
  52 struct xlr_board_info xlr_board_info;
  53
  54 static int
  55 xlr_pcmcia_present(void)
  56 {
  57         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
  58         uint32_t resetconf;
  59
  60         resetconf = xlr_read_reg(mmio, 21);
  61         return ((resetconf & 0x4000) != 0);
  62 }
  63
  64 static void
  65 xlr_chip_specific_overrides(struct xlr_board_info* board)
  66 {
  67         struct xlr_gmac_block_t *blk0, *blk1, *blk2;
  68         uint32_t chipid;
  69         uint32_t revision;
  70
  71         blk0 = &board->gmac_block[0];
  72         blk1 = &board->gmac_block[1];
  73         blk2 = &board->gmac_block[2];
  74
  75         chipid = xlr_processor_id();
  76         revision = xlr_revision();
  77
  78         if (revision == 0x04) { /* B2 */
  79                 switch (chipid) {
  80                 case 0x07:  /* XLR 508 */
  81                 case 0x08:  /* XLR 516 */
  82                 case 0x09:  /* XLR 532 */
  83                         /* NA[12] not available */
  84                         memset(blk1, 0, sizeof(*blk1));
  85                         memset(blk2, 0, sizeof(*blk2));
  86                         break;
  87                 case 0x06:  /* XLR 308 */
  88                         /* NA0 has 3 ports */
  89                         blk0->gmac_port[3].valid = 0;
  90                         blk0->num_ports--;
  91                         /* NA[12] not available */
  92                         memset(blk1, 0, sizeof(*blk1));
  93                         memset(blk2, 0, sizeof(*blk2));
  94                         break;
  95                 default:
  96                         break;
  97                 }
  98         } else if (revision == 0x91) { /* C4 */
  99                 switch (chipid) {
 100                 case 0x0B:  /* XLR 508 */
 101                 case 0x0A:  /* XLR 516 */
 102                 case 0x08:  /* XLR 532 */
 103                         /* NA[12] not available */
 104                         memset(blk1, 0, sizeof(*blk1));
 105                         memset(blk2, 0, sizeof(*blk2));
 106                         break;
 107                 case 0x0F:  /* XLR 308 */
 108                         /* NA0 has 3 ports */
 109                         blk0->gmac_port[3].valid = 0;
 110                         blk0->num_ports--;
 111                         /* NA[12] not available */
 112                         memset(blk1, 0, sizeof(*blk1));
 113                         memset(blk2, 0, sizeof(*blk2));
 114                         break;
 115                 default:
 116                         break;
 117                 }
 118         } else { /* other pre-production silicon */
 119                 switch (chipid) {
 120                         /* XLR 5xx */
 121                 case 0x0B:
 122                 case 0x0A:
 123                 case 0x07:
 124                 case 0x08:
 125                 case 0x09:
 126                         /* NA[12] not available */
 127                         memset(blk1, 0, sizeof(*blk1));
 128                         memset(blk2, 0, sizeof(*blk2));
 129                         break;
 130                         /* XLR 3xx */
 131                 case 0x0F:
 132                 case 0x06:
 133                         /* NA0 has 3 ports */
 134                         blk0->gmac_port[3].valid = 0;
 135                         blk0->num_ports--;
 136                         /* NA[12] not available */
 137                         memset(blk1, 0, sizeof(*blk1));
 138                         memset(blk2, 0, sizeof(*blk2));
 139                         break;
 140                 default:
 141                         break;
 142                 }
 143         }
 144 }
 145
 146 static void
 147 xlr_board_specific_overrides(struct xlr_board_info* board)
 148 {
 149         struct xlr_gmac_block_t *blk1, *blk2;
 150
 151         blk1 = &board->gmac_block[1];
 152         blk2 = &board->gmac_block[2];
 153
 154         switch (xlr_boot1_info.board_major_version) {
 155         case RMI_XLR_BOARD_ARIZONA_I:
 156                 /* ATX-I has SPI-4, not XGMAC */
 157                 blk1->type = XLR_SPI4;
 158                 blk1->enabled = 0;     /* nlge does not
 159                                                          support SPI-4 */
 160                 blk2->type = XLR_SPI4;
 161                 blk2->enabled = 0;
 162                 break;
 163
 164         case RMI_XLR_BOARD_ARIZONA_II:
 165                 /* XGMII_A --> VSC7281, XGMII_B --> VSC7281 */
 166                 blk1->enabled = 1;
 167                 blk1->num_ports = 1;
 168                 blk1->gmac_port[0].valid = 1;
 169
 170                 blk2->enabled = 1;
 171                 blk2->num_ports = 1;
 172                 blk2->gmac_port[0].valid = 1;
 173         default:
 174                 break;
 175         }
 176 }
 177
 178 static int
 179 quad0_xaui(void)
 180 {
 181         xlr_reg_t *gpio_mmio =
 182             (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET);
 183         uint32_t bit24;
 184
 185         bit24 = (xlr_read_reg(gpio_mmio, 0x15) >> 24) & 0x1;
 186         return (bit24);
 187 }
 188
 189 static int
 190 quad1_xaui(void)
 191 {
 192         xlr_reg_t *gpio_mmio =
 193             (unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET);
 194         uint32_t bit25;
 195
 196         bit25 = (xlr_read_reg(gpio_mmio, 0x15) >> 25) & 0x1;
 197         return (bit25);
 198 }
 199
 200 static void
 201 xls_chip_specific_overrides(struct xlr_board_info* board)
 202 {
 203         struct xlr_gmac_block_t *blk0, *blk1;
 204         uint32_t chipid;
 205
 206         blk0 = &board->gmac_block[0];
 207         blk1 = &board->gmac_block[1];
 208         chipid = xlr_processor_id();
 209
 210         switch (chipid) {
 211         case 0x8E:      /* XLS208 */
 212         case 0x8F:      /* XLS204 */
 213                 /* NA1 is not available */
 214                 memset(blk1, 0, sizeof(*blk1));
 215                 break;
 216         case 0xCE:      /* XLS108 */
 217         case 0xCF:      /* XLS104 */
 218                 /* NA0 has 3 ports */
 219                 blk0->gmac_port[3].valid = 0;
 220                 blk0->num_ports--;
 221                 /* NA1 is not available */
 222                 memset(blk1, 0, sizeof(*blk1));
 223                 break;
 224         default:
 225                 break;
 226         }
 227 }
 228
 229 static void
 230 xls_board_specific_overrides(struct xlr_board_info* board)
 231 {
 232         struct xlr_gmac_block_t *blk0, *blk1;
 233         int i;
 234
 235         blk0 = &board->gmac_block[0];
 236         blk1 = &board->gmac_block[1];
 237
 238         switch (xlr_boot1_info.board_major_version) {
 239         case RMI_XLR_BOARD_ARIZONA_VI:
 240                 blk0->mode = XLR_PORT0_RGMII;
 241                 blk0->gmac_port[0].type = XLR_RGMII;
 242                 blk0->gmac_port[0].phy_addr = 0;
 243                 blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_4_OFFSET;
 244                 /* Because of the Octal PHY, SGMII Quad1 is MII is also bound
 245                  * to the PHY attached to SGMII0_MDC/MDIO/MDINT. */
 246                 for (i = 0; i < 4; i++) {
 247                         blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
 248                         blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
 249                 }
 250                 blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET;
 251                 blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET;
 252                 blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET;
 253
 254                 blk1->gmac_port[1].serdes_addr = XLR_IO_GMAC_0_OFFSET;
 255                 blk1->gmac_port[2].serdes_addr = XLR_IO_GMAC_0_OFFSET;
 256                 blk1->gmac_port[3].serdes_addr = XLR_IO_GMAC_0_OFFSET;
 257
 258                 /* RGMII MDIO interrupt is thru NA1 and SGMII MDIO
 259                  * interrupts for ports in blk1 are from NA0 */
 260                 blk0->gmac_port[0].mdint_id = 1;
 261
 262                 blk1->gmac_port[0].mdint_id = 0;
 263                 blk1->gmac_port[1].mdint_id = 0;
 264                 blk1->gmac_port[2].mdint_id = 0;
 265                 blk1->gmac_port[3].mdint_id = 0;
 266
 267                 /* If we have a 4xx lite chip, don't enable the
 268                  * GMACs which are disabled in hardware */
 269                 if (xlr_is_xls4xx_lite()) {
 270                         xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
 271                         uint32_t tmp;
 272
 273                         /* Port 6 & 7 are not enabled on the condor 4xx, figure
 274                          * this out from the GPIO fuse bank */
 275                         tmp = xlr_read_reg(mmio, 35);
 276                         if ((tmp & (3 << 28)) != 0) {
 277                                 blk1->enabled = 0x3;
 278                                 blk1->gmac_port[2].valid = 0;
 279                                 blk1->gmac_port[3].valid = 0;
 280                                 blk1->num_ports = 2;
 281                         }
 282                 }
 283                 break;
 284
 285         case RMI_XLR_BOARD_ARIZONA_VIII:
 286                 if (blk1->enabled) {
 287                         /* There is just one Octal PHY on the board and it is
 288                          * connected to the MII interface for NA Quad 0. */
 289                         for (i = 0; i < 4; i++) {
 290                                 blk1->gmac_port[i].mii_addr =
 291                                     XLR_IO_GMAC_0_OFFSET;
 292                                 blk1->gmac_port[i].mdint_id = 0;
 293                         }
 294                 }
 295                 break;
 296
 297         case RMI_XLR_BOARD_ARIZONA_XI:
 298         case RMI_XLR_BOARD_ARIZONA_XII:
 299                 if (quad0_xaui()) { /* GMAC ports 0-3 are set to XAUI */
 300                         /* only GMAC0 is active i.e, the 0-th port on this quad.
 301                          * Disable all the other 7 possible ports. */
 302                         for (i = 1; i < MAX_NA_PORTS; i++) {
 303                                 memset(&blk0->gmac_port[i], 0,
 304                                     sizeof(blk0->gmac_port[i]));
 305                         }
 306                         /* Setup for XAUI on N/w Acc0: gmac0 */
 307                         blk0->type              = XLR_XGMAC;
 308                         blk0->mode              = XLR_XAUI;
 309                         blk0->num_ports         = 1;
 310                         blk0->gmac_port[0].type = XLR_XAUI;
 311                         blk1->gmac_port[0].phy_addr = 16;
 312                         blk0->gmac_port[0].tx_bucket_id = blk0->station_txbase;
 313                         /* Other addresses etc need not be modified as XAUI_0
 314                          * shares its addresses with SGMII GMAC_0, which was
 315                          * set in the caller. */
 316                 }
 317                 else {
 318                         blk0->num_ports         = 1;  /* only 1 RGMII port */
 319                         blk0->mode = XLR_PORT0_RGMII;
 320                         blk0->gmac_port[0].type = XLR_RGMII;
 321                         blk0->gmac_port[0].phy_addr = 0;
 322                         blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET;
 323                 }
 324
 325                 if (quad1_xaui()) { /* GMAC ports 4-7 are used for XAUI */
 326                         /* only GMAC4 is active i.e, the 0-th port on this quad.
 327                          * Disable all the other 7 possible ports. */
 328                         for (i = 1; i < MAX_NA_PORTS; i++) {
 329                                 memset(&blk1->gmac_port[i], 0,
 330                                     sizeof(blk1->gmac_port[i]));
 331                         }
 332                         /* Setup for XAUI on N/w Acc1: gmac4 */
 333                         blk1->type              = XLR_XGMAC;
 334                         blk1->mode              = XLR_XAUI;
 335                         blk1->num_ports         = 1;
 336                         /* XAUI and SGMII ports share FMN buckets on N/w Acc 1;
 337                            so, station_txbase, station_rfr need not be
 338                            patched up. */
 339                         blk1->gmac_port[0].type = XLR_XAUI;
 340                         blk1->gmac_port[0].phy_addr = 16;
 341                         blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase;
 342                         /* Other addresses etc need not be modified as XAUI_1
 343                          * shares its addresses with SGMII GMAC_4, which was
 344                          * set in the caller. */
 345                 }
 346                 break;
 347
 348         default:
 349                 break;
 350         }
 351 }
 352
 353 /*
 354  * All our knowledge of chip and board that cannot be detected by probing
 355  * at run-time goes here
 356  */
 357 int
 358 xlr_board_info_setup()
 359 {
 360         struct xlr_gmac_block_t *blk0, *blk1, *blk2;
 361         int i;
 362
 363         /* This setup code is long'ish because the same base driver
 364          * (if_nlge.c) is used for different:
 365          *    - CPUs (XLR/XLS)
 366          *    - boards (for each CPU, multiple board configs are possible
 367          *              and available).
 368          *
 369          * At the time of writing, there are atleast 12 boards, 4 with XLR
 370          * and 8 with XLS. This means that the base driver needs to work with
 371          * 12 different configurations, with varying levels of differences.
 372          * To accomodate the different configs, the xlr_board_info struct
 373          * has various attributes for paramters that could be different.
 374          * These attributes are setup here and can be used directly in the
 375          * base driver.
 376          * It was seen that the setup code is not entirely trivial and
 377          * it is possible to organize it in different ways. In the following,
 378          * we choose an approach that sacrifices code-compactness/speed for
 379          * readability. This is because configuration code executes once
 380          * per reboot and hence has a minimal performance impact.
 381          * On the other hand, driver debugging/enhancements require
 382          * that different engineers can quickly comprehend the setup
 383          * sequence. Hence, readability is seen as the key requirement for
 384          * this code. It is for the reader to decide how much of this
 385          * requirement is met with the current code organization !!
 386          *
 387          * The initialization is organized thus:
 388          *
 389          * if (CPU is XLS) {
 390          *    // initialize per XLS architecture
 391          *       // default inits (per chip spec)
 392          *       // chip-specific overrides
 393          *       // board-specific overrides
 394          * } else if (CPU is XLR) {
 395          *    // initialize per XLR architecture
 396          *       // default inits (per chip spec)
 397          *       // chip-specific overrides
 398          *       // board-specific overrides
 399          * }
 400          *
 401          * For each CPU family, all the default initializations
 402          * are done for a fully-loaded device of that family.
 403          * This configuration is then adjusted for the actual
 404          * chip id. This is followed up with board specific
 405          * overrides.
 406          */
 407
 408         /* start with a clean slate */
 409         memset(&xlr_board_info, 0, sizeof(xlr_board_info));
 410         xlr_board_info.ata =  xlr_pcmcia_present();
 411
 412         blk0 = &xlr_board_info.gmac_block[0];
 413         blk1 = &xlr_board_info.gmac_block[1];
 414         blk2 = &xlr_board_info.gmac_block[2];
 415
 416         if (xlr_is_xls()) {
 417                 xlr_board_info.is_xls = 1;
 418                 xlr_board_info.nr_cpus = 8;
 419                 xlr_board_info.usb = 1;
 420                 /* Board version 8 has NAND flash */
 421                 xlr_board_info.cfi =
 422                     (xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII);
 423                 xlr_board_info.pci_irq = 0;
 424                 xlr_board_info.credit_configs = xls_core_cc_configs;
 425                 xlr_board_info.bucket_sizes   = &xls_bucket_sizes;
 426                 xlr_board_info.gmacports      = MAX_NA_PORTS;
 427
 428                 /* ---------------- Network Acc 0 ---------------- */
 429
 430                 blk0->type              = XLR_GMAC;
 431                 blk0->enabled           = 0xf;
 432                 blk0->credit_config     = &xls_cc_table_gmac0;
 433                 blk0->station_id        = MSGRNG_STNID_GMAC;
 434                 blk0->station_txbase    = MSGRNG_STNID_GMACTX0;
 435                 blk0->station_rfr       = MSGRNG_STNID_GMACRFR_0;
 436                 blk0->mode              = XLR_SGMII;
 437                 blk0->baseaddr          = XLR_IO_GMAC_0_OFFSET;
 438                 blk0->baseirq           = PIC_GMAC_0_IRQ;
 439                 blk0->baseinst          = 0;
 440
 441                 /* By default, assume SGMII is setup. But this can change based
 442                    on board-specific or setting-specific info. */
 443                 for (i = 0; i < 4; i++) {
 444                         blk0->gmac_port[i].valid = 1;
 445                         blk0->gmac_port[i].instance = i + blk0->baseinst;
 446                         blk0->gmac_port[i].type = XLR_SGMII;
 447                         blk0->gmac_port[i].phy_addr = i + 16;
 448                         blk0->gmac_port[i].tx_bucket_id =
 449                             blk0->station_txbase + i;
 450                         blk0->gmac_port[i].mdint_id = 0;
 451                         blk0->num_ports++;
 452                         blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000;
 453                         blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
 454                         blk0->gmac_port[i].pcs_addr = XLR_IO_GMAC_0_OFFSET;
 455                         blk0->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
 456                 }
 457
 458                 /* ---------------- Network Acc 1 ---------------- */
 459                 blk1->type              = XLR_GMAC;
 460                 blk1->enabled           = 0xf;
 461                 blk1->credit_config     = &xls_cc_table_gmac1;
 462                 blk1->station_id        = MSGRNG_STNID_GMAC1;
 463                 blk1->station_txbase    = MSGRNG_STNID_GMAC1_TX0;
 464                 blk1->station_rfr       = MSGRNG_STNID_GMAC1_FR_0;
 465                 blk1->mode              = XLR_SGMII;
 466                 blk1->baseaddr          = XLR_IO_GMAC_4_OFFSET;
 467                 blk1->baseirq           = PIC_XGS_0_IRQ;
 468                 blk1->baseinst          = 4;
 469
 470                 for (i = 0; i < 4; i++) {
 471                         blk1->gmac_port[i].valid = 1;
 472                         blk1->gmac_port[i].instance = i + blk1->baseinst;
 473                         blk1->gmac_port[i].type = XLR_SGMII;
 474                         blk1->gmac_port[i].phy_addr = i + 20;
 475                         blk1->gmac_port[i].tx_bucket_id =
 476                             blk1->station_txbase + i;
 477                         blk1->gmac_port[i].mdint_id = 1;
 478                         blk1->num_ports++;
 479                         blk1->gmac_port[i].base_addr = XLR_IO_GMAC_4_OFFSET +  i * 0x1000;
 480                         blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_4_OFFSET;
 481                         blk1->gmac_port[i].pcs_addr = XLR_IO_GMAC_4_OFFSET;
 482                         blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
 483                 }
 484
 485                 /* ---------------- Network Acc 2 ---------------- */
 486                 xlr_board_info.gmac_block[2].enabled = 0;  /* disabled on XLS */
 487
 488                 xls_chip_specific_overrides(&xlr_board_info);
 489                 xls_board_specific_overrides(&xlr_board_info);
 490
 491         } else {        /* XLR */
 492                 xlr_board_info.is_xls = 0;
 493                 xlr_board_info.nr_cpus = 32;
 494                 xlr_board_info.usb = 0;
 495                 xlr_board_info.cfi = 1;
 496                 xlr_board_info.pci_irq = 0;
 497                 xlr_board_info.credit_configs = xlr_core_cc_configs;
 498                 xlr_board_info.bucket_sizes   = &bucket_sizes;
 499                 xlr_board_info.gmacports         = 4;
 500
 501                 /* ---------------- GMAC0 ---------------- */
 502                 blk0->type              = XLR_GMAC;
 503                 blk0->enabled           = 0xf;
 504                 blk0->credit_config     = &cc_table_gmac;
 505                 blk0->station_id        = MSGRNG_STNID_GMAC;
 506                 blk0->station_txbase    = MSGRNG_STNID_GMACTX0;
 507                 blk0->station_rfr       = MSGRNG_STNID_GMACRFR_0;
 508                 blk0->mode              = XLR_RGMII;
 509                 blk0->baseaddr          = XLR_IO_GMAC_0_OFFSET;
 510                 blk0->baseirq           = PIC_GMAC_0_IRQ;
 511                 blk0->baseinst          = 0;
 512
 513                 /* first, do the common/easy stuff for all the ports */
 514                 for (i = 0; i < 4; i++) {
 515                         blk0->gmac_port[i].valid = 1;
 516                         blk0->gmac_port[i].instance = i + blk0->baseinst;
 517                         blk0->gmac_port[i].type = XLR_RGMII;
 518                         blk0->gmac_port[i].phy_addr = i;
 519                         blk0->gmac_port[i].tx_bucket_id =
 520                             blk0->station_txbase + i;
 521                         blk0->gmac_port[i].mdint_id = 0;
 522                         blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000;
 523                         blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
 524                         /* RGMII ports, no PCS/SERDES */
 525                         blk0->num_ports++;
 526                 }
 527
 528                 /* ---------------- XGMAC0 ---------------- */
 529                 blk1->type              = XLR_XGMAC;
 530                 blk1->mode              = XLR_XGMII;
 531                 blk1->enabled           = 0;
 532                 blk1->credit_config     = &cc_table_xgs_0;
 533                 blk1->station_txbase    = MSGRNG_STNID_XGS0_TX;
 534                 blk1->station_rfr       = MSGRNG_STNID_XMAC0RFR;
 535                 blk1->station_id        = MSGRNG_STNID_XGS0FR;
 536                 blk1->baseaddr          = XLR_IO_XGMAC_0_OFFSET;
 537                 blk1->baseirq           = PIC_XGS_0_IRQ;
 538                 blk1->baseinst          = 4;
 539
 540                 blk1->gmac_port[0].type         = XLR_XGMII;
 541                 blk1->gmac_port[0].instance     = 0;
 542                 blk1->gmac_port[0].phy_addr     = 0;
 543                 blk1->gmac_port[0].base_addr    = XLR_IO_XGMAC_0_OFFSET;
 544                 blk1->gmac_port[0].mii_addr     = XLR_IO_XGMAC_0_OFFSET;
 545                 blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase;
 546                 blk1->gmac_port[0].mdint_id     = 1;
 547
 548                 /* ---------------- XGMAC1 ---------------- */
 549                 blk2->type              = XLR_XGMAC;
 550                 blk2->mode              = XLR_XGMII;
 551                 blk2->enabled           = 0;
 552                 blk2->credit_config     = &cc_table_xgs_1;
 553                 blk2->station_txbase    = MSGRNG_STNID_XGS1_TX;
 554                 blk2->station_rfr       = MSGRNG_STNID_XMAC1RFR;
 555                 blk2->station_id        = MSGRNG_STNID_XGS1FR;
 556                 blk2->baseaddr          = XLR_IO_XGMAC_1_OFFSET;
 557                 blk2->baseirq           = PIC_XGS_1_IRQ;
 558                 blk2->baseinst          = 5;
 559
 560                 blk2->gmac_port[0].type         = XLR_XGMII;
 561                 blk2->gmac_port[0].instance     = 0;
 562                 blk2->gmac_port[0].phy_addr     = 0;
 563                 blk2->gmac_port[0].base_addr    = XLR_IO_XGMAC_1_OFFSET;
 564                 blk2->gmac_port[0].mii_addr     = XLR_IO_XGMAC_1_OFFSET;
 565                 blk2->gmac_port[0].tx_bucket_id = blk2->station_txbase;
 566                 blk2->gmac_port[0].mdint_id     = 2;
 567
 568                 /* Done with default setup. Now handle chip and board-specific
 569                    variations. */
 570                 xlr_chip_specific_overrides(&xlr_board_info);
 571                 xlr_board_specific_overrides(&xlr_board_info);
 572         }
 573         return 0;
 574 }