2 * Copyright (c) 2003-2009 RMI Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of RMI Corporation, nor the names of its contributors,
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 * Engineering boards have a major/minor number in their EEPROM to
37 * identify their configuration
39 #define RMI_XLR_BOARD_ARIZONA_I 1
40 #define RMI_XLR_BOARD_ARIZONA_II 2
41 #define RMI_XLR_BOARD_ARIZONA_III 3
42 #define RMI_XLR_BOARD_ARIZONA_IV 4
43 #define RMI_XLR_BOARD_ARIZONA_V 5
44 #define RMI_XLR_BOARD_ARIZONA_VI 6
45 #define RMI_XLR_BOARD_ARIZONA_VII 7
46 #define RMI_XLR_BOARD_ARIZONA_VIII 8
47 #define RMI_XLR_BOARD_ARIZONA_XI 11
48 #define RMI_XLR_BOARD_ARIZONA_XII 12
51 * RMI Chips - Values in Processor ID field
53 #define RMI_CHIP_XLR732 0x00
54 #define RMI_CHIP_XLR716 0x02
55 #define RMI_CHIP_XLR308 0x06
56 #define RMI_CHIP_XLR532 0x09
61 #define RMI_CHIP_XLR308_C 0x0F
62 #define RMI_CHIP_XLR508_C 0x0b
63 #define RMI_CHIP_XLR516_C 0x0a
64 #define RMI_CHIP_XLR532_C 0x08
69 #define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */
70 #define RMI_CHIP_XLS608 0x80 /* Internal */
71 #define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */
72 #define RMI_CHIP_XLS208 0x8e
73 #define RMI_CHIP_XLS204 0x8f
74 #define RMI_CHIP_XLS108 0xce
75 #define RMI_CHIP_XLS104 0xcf
78 * XLS B revision chips
80 #define RMI_CHIP_XLS616_B0 0x40
81 #define RMI_CHIP_XLS608_B0 0x4a
82 #define RMI_CHIP_XLS416_B0 0x44
83 #define RMI_CHIP_XLS412_B0 0x4c
84 #define RMI_CHIP_XLS408_B0 0x4e
85 #define RMI_CHIP_XLS404_B0 0x4f
88 * The XLS product line has chip versions 0x4x and 0x8x
90 static __inline unsigned int
93 uint32_t prid = mips_rd_prid();
95 return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
96 (prid & 0xf000) == 0xc000);
100 * The last byte of the processor id field is revision
102 static __inline unsigned int
106 return (mips_rd_prid() & 0xff);
110 * The 15:8 byte of the PR Id register is the Processor ID
112 static __inline unsigned int
113 xlr_processor_id(void)
116 return ((mips_rd_prid() & 0xff00) >> 8);
120 * The processor is XLR and C-Series
122 static __inline unsigned int
123 xlr_is_c_revision(void)
125 int processor_id = xlr_processor_id();
126 int revision_id = xlr_revision();
128 switch (processor_id) {
130 * These are the relevant PIDs for XLR
131 * steppings (hawk and above). For these,
132 * PIDs, Rev-Ids of [5-9] indicate 'C'.
134 case RMI_CHIP_XLR308_C:
135 case RMI_CHIP_XLR508_C:
136 case RMI_CHIP_XLR516_C:
137 case RMI_CHIP_XLR532_C:
138 case RMI_CHIP_XLR716:
139 case RMI_CHIP_XLR732:
140 if (revision_id >= 5 && revision_id <= 9)
149 * RMI Engineering boards which are PCI cards
150 * These should come up in PCI device mode (not yet)
153 xlr_board_pci(int board_major)
156 return ((board_major == RMI_XLR_BOARD_ARIZONA_III) ||
157 (board_major == RMI_XLR_BOARD_ARIZONA_V));
163 uint32_t chipid = xlr_processor_id();
165 return (chipid == 0xce || chipid == 0xcf);
171 uint32_t chipid = xlr_processor_id();
173 return (chipid == 0x8e || chipid == 0x8f);
177 xlr_is_xls4xx_lite(void)
179 uint32_t chipid = xlr_processor_id();
181 return (chipid == 0x88 || chipid == 0x8c);
184 static __inline unsigned int
187 uint32_t chipid = xlr_processor_id();
189 return (chipid >= 0x40 && chipid <= 0x4f);
192 /* SPI-4 --> 8 ports, 1G MAC --> 4 ports and 10G MAC --> 1 port */
193 #define MAX_NA_PORTS 8
195 /* all our knowledge of chip and board that cannot be detected run-time goes here */
196 enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4};
197 enum gmac_port_types { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII, XLR_XGMII, XLR_XAUI };
198 enum i2c_dev_types { I2C_RTC, I2C_THERMAL, I2C_EEPROM };
200 struct xlr_board_info {
203 int usb; /* usb enabled ? */
204 int cfi; /* compact flash driver for NOR? */
205 int ata; /* ata driver */
207 struct stn_cc **credit_configs; /* pointer to Core station credits */
208 struct bucket_size *bucket_sizes; /* pointer to Core station bucket */
209 int *msgmap; /* mapping of message station to devices */
210 int gmacports; /* number of gmac ports on the board */
211 struct xlr_i2c_dev_t {
213 unsigned int enabled; /* mask of devs enabled */
218 struct xlr_gmac_block_t { /* refers to the set of GMACs controlled by a
219 network accelarator */
220 int type; /* see enum gmac_block_types */
221 unsigned int enabled; /* mask of ports enabled */
222 struct stn_cc *credit_config; /* credit configuration */
223 int station_id; /* station id for sending msgs */
224 int station_txbase; /* station id for tx */
225 int station_rfr; /* free desc bucket */
226 int mode; /* see gmac_block_modes */
227 uint32_t baseaddr; /* IO base */
228 int baseirq; /* first irq for this block, the rest are in sequence */
229 int baseinst; /* the first rge unit for this block */
231 struct xlr_gmac_port {
233 int type; /* see enum gmac_port_types */
234 uint32_t instance; /* identifies the GMAC to which
235 this port is bound to. */
240 uint32_t serdes_addr;
241 uint32_t tx_bucket_id;
243 } gmac_port[MAX_NA_PORTS];
247 extern struct xlr_board_info xlr_board_info;
248 int xlr_board_info_setup(void);