sys/mips/rmi/dev/xlr/rge.h

   1 /*-
   2  * Copyright (c) 2003-2009 RMI Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  * 3. Neither the name of RMI Corporation, nor the names of its contributors,
  14  *    may be used to endorse or promote products derived from this software
  15  *    without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  27  * SUCH DAMAGE.
  28  *
  29  * RMI_BSD */
  30 #ifndef _RMI_RGE_H_
  31 #define _RMI_RGE_H_
  32
  33 /* #define MAC_SPLIT_MODE */
  34
  35 #define MAC_SPACING                 0x400
  36 #define XGMAC_SPACING               0x400
  37
  38 /* PE-MCXMAC register and bit field definitions */
  39 #define R_MAC_CONFIG_1                                              0x00
  40 #define   O_MAC_CONFIG_1__srst                                      31
  41 #define   O_MAC_CONFIG_1__simr                                      30
  42 #define   O_MAC_CONFIG_1__hrrmc                                     18
  43 #define   W_MAC_CONFIG_1__hrtmc                                      2
  44 #define   O_MAC_CONFIG_1__hrrfn                                     16
  45 #define   W_MAC_CONFIG_1__hrtfn                                      2
  46 #define   O_MAC_CONFIG_1__intlb                                      8
  47 #define   O_MAC_CONFIG_1__rxfc                                       5
  48 #define   O_MAC_CONFIG_1__txfc                                       4
  49 #define   O_MAC_CONFIG_1__srxen                                      3
  50 #define   O_MAC_CONFIG_1__rxen                                       2
  51 #define   O_MAC_CONFIG_1__stxen                                      1
  52 #define   O_MAC_CONFIG_1__txen                                       0
  53 #define R_MAC_CONFIG_2                                              0x01
  54 #define   O_MAC_CONFIG_2__prlen                                     12
  55 #define   W_MAC_CONFIG_2__prlen                                      4
  56 #define   O_MAC_CONFIG_2__speed                                      8
  57 #define   W_MAC_CONFIG_2__speed                                      2
  58 #define   O_MAC_CONFIG_2__hugen                                      5
  59 #define   O_MAC_CONFIG_2__flchk                                      4
  60 #define   O_MAC_CONFIG_2__crce                                       1
  61 #define   O_MAC_CONFIG_2__fulld                                      0
  62 #define R_IPG_IFG                                                   0x02
  63 #define   O_IPG_IFG__ipgr1                                          24
  64 #define   W_IPG_IFG__ipgr1                                           7
  65 #define   O_IPG_IFG__ipgr2                                          16
  66 #define   W_IPG_IFG__ipgr2                                           7
  67 #define   O_IPG_IFG__mifg                                            8
  68 #define   W_IPG_IFG__mifg                                            8
  69 #define   O_IPG_IFG__ipgt                                            0
  70 #define   W_IPG_IFG__ipgt                                            7
  71 #define R_HALF_DUPLEX                                               0x03
  72 #define   O_HALF_DUPLEX__abebt                                      24
  73 #define   W_HALF_DUPLEX__abebt                                       4
  74 #define   O_HALF_DUPLEX__abebe                                      19
  75 #define   O_HALF_DUPLEX__bpnb                                       18
  76 #define   O_HALF_DUPLEX__nobo                                       17
  77 #define   O_HALF_DUPLEX__edxsdfr                                    16
  78 #define   O_HALF_DUPLEX__retry                                      12
  79 #define   W_HALF_DUPLEX__retry                                       4
  80 #define   O_HALF_DUPLEX__lcol                                        0
  81 #define   W_HALF_DUPLEX__lcol                                       10
  82 #define R_MAXIMUM_FRAME_LENGTH                                      0x04
  83 #define   O_MAXIMUM_FRAME_LENGTH__maxf                               0
  84 #define   W_MAXIMUM_FRAME_LENGTH__maxf                              16
  85 #define R_TEST                                                      0x07
  86 #define   O_TEST__mbof                                               3
  87 #define   O_TEST__rthdf                                              2
  88 #define   O_TEST__tpause                                             1
  89 #define   O_TEST__sstct                                              0
  90 #define R_MII_MGMT_CONFIG                                           0x08
  91 #define   O_MII_MGMT_CONFIG__scinc                                   5
  92 #define   O_MII_MGMT_CONFIG__spre                                    4
  93 #define   O_MII_MGMT_CONFIG__clks                                    3
  94 #define   W_MII_MGMT_CONFIG__clks                                    3
  95 #define R_MII_MGMT_COMMAND                                          0x09
  96 #define   O_MII_MGMT_COMMAND__scan                                   1
  97 #define   O_MII_MGMT_COMMAND__rstat                                  0
  98 #define R_MII_MGMT_ADDRESS                                          0x0A
  99 #define   O_MII_MGMT_ADDRESS__fiad                                   8
 100 #define   W_MII_MGMT_ADDRESS__fiad                                   5
 101 #define   O_MII_MGMT_ADDRESS__fgad                                   5
 102 #define   W_MII_MGMT_ADDRESS__fgad                                   0
 103 #define R_MII_MGMT_WRITE_DATA                                       0x0B
 104 #define   O_MII_MGMT_WRITE_DATA__ctld                                0
 105 #define   W_MII_MGMT_WRITE_DATA__ctld                               16
 106 #define R_MII_MGMT_STATUS                                           0x0C
 107 #define R_MII_MGMT_INDICATORS                                       0x0D
 108 #define   O_MII_MGMT_INDICATORS__nvalid                              2
 109 #define   O_MII_MGMT_INDICATORS__scan                                1
 110 #define   O_MII_MGMT_INDICATORS__busy                                0
 111 #define R_INTERFACE_CONTROL                                         0x0E
 112 #define   O_INTERFACE_CONTROL__hrstint                              31
 113 #define   O_INTERFACE_CONTROL__tbimode                              27
 114 #define   O_INTERFACE_CONTROL__ghdmode                              26
 115 #define   O_INTERFACE_CONTROL__lhdmode                              25
 116 #define   O_INTERFACE_CONTROL__phymod                               24
 117 #define   O_INTERFACE_CONTROL__hrrmi                                23
 118 #define   O_INTERFACE_CONTROL__rspd                                 16
 119 #define   O_INTERFACE_CONTROL__hr100                                15
 120 #define   O_INTERFACE_CONTROL__frcq                                 10
 121 #define   O_INTERFACE_CONTROL__nocfr                                 9
 122 #define   O_INTERFACE_CONTROL__dlfct                                 8
 123 #define   O_INTERFACE_CONTROL__enjab                                 0
 124 #define R_INTERFACE_STATUS                                         0x0F
 125 #define   O_INTERFACE_STATUS__xsdfr                                  9
 126 #define   O_INTERFACE_STATUS__ssrr                                   8
 127 #define   W_INTERFACE_STATUS__ssrr                                   5
 128 #define   O_INTERFACE_STATUS__miilf                                  3
 129 #define   O_INTERFACE_STATUS__locar                                  2
 130 #define   O_INTERFACE_STATUS__sqerr                                  1
 131 #define   O_INTERFACE_STATUS__jabber                                 0
 132 #define R_STATION_ADDRESS_LS                                       0x10
 133 #define R_STATION_ADDRESS_MS                                       0x11
 134
 135 /* A-XGMAC register and bit field definitions */
 136 #define R_XGMAC_CONFIG_0    0x00
 137 #define   O_XGMAC_CONFIG_0__hstmacrst               31
 138 #define   O_XGMAC_CONFIG_0__hstrstrctl              23
 139 #define   O_XGMAC_CONFIG_0__hstrstrfn               22
 140 #define   O_XGMAC_CONFIG_0__hstrsttctl              18
 141 #define   O_XGMAC_CONFIG_0__hstrsttfn               17
 142 #define   O_XGMAC_CONFIG_0__hstrstmiim              16
 143 #define   O_XGMAC_CONFIG_0__hstloopback             8
 144 #define R_XGMAC_CONFIG_1    0x01
 145 #define   O_XGMAC_CONFIG_1__hsttctlen               31
 146 #define   O_XGMAC_CONFIG_1__hsttfen                 30
 147 #define   O_XGMAC_CONFIG_1__hstrctlen               29
 148 #define   O_XGMAC_CONFIG_1__hstrfen                 28
 149 #define   O_XGMAC_CONFIG_1__tfen                    26
 150 #define   O_XGMAC_CONFIG_1__rfen                    24
 151 #define   O_XGMAC_CONFIG_1__hstrctlshrtp            12
 152 #define   O_XGMAC_CONFIG_1__hstdlyfcstx             10
 153 #define   W_XGMAC_CONFIG_1__hstdlyfcstx              2
 154 #define   O_XGMAC_CONFIG_1__hstdlyfcsrx              8
 155 #define   W_XGMAC_CONFIG_1__hstdlyfcsrx              2
 156 #define   O_XGMAC_CONFIG_1__hstppen                  7
 157 #define   O_XGMAC_CONFIG_1__hstbytswp                6
 158 #define   O_XGMAC_CONFIG_1__hstdrplt64               5
 159 #define   O_XGMAC_CONFIG_1__hstprmscrx               4
 160 #define   O_XGMAC_CONFIG_1__hstlenchk                3
 161 #define   O_XGMAC_CONFIG_1__hstgenfcs                2
 162 #define   O_XGMAC_CONFIG_1__hstpadmode               0
 163 #define   W_XGMAC_CONFIG_1__hstpadmode               2
 164 #define R_XGMAC_CONFIG_2    0x02
 165 #define   O_XGMAC_CONFIG_2__hsttctlfrcp             31
 166 #define   O_XGMAC_CONFIG_2__hstmlnkflth             27
 167 #define   O_XGMAC_CONFIG_2__hstalnkflth             26
 168 #define   O_XGMAC_CONFIG_2__rflnkflt                24
 169 #define   W_XGMAC_CONFIG_2__rflnkflt                 2
 170 #define   O_XGMAC_CONFIG_2__hstipgextmod            16
 171 #define   W_XGMAC_CONFIG_2__hstipgextmod             5
 172 #define   O_XGMAC_CONFIG_2__hstrctlfrcp             15
 173 #define   O_XGMAC_CONFIG_2__hstipgexten              5
 174 #define   O_XGMAC_CONFIG_2__hstmipgext               0
 175 #define   W_XGMAC_CONFIG_2__hstmipgext               5
 176 #define R_XGMAC_CONFIG_3    0x03
 177 #define   O_XGMAC_CONFIG_3__hstfltrfrm              31
 178 #define   W_XGMAC_CONFIG_3__hstfltrfrm              16
 179 #define   O_XGMAC_CONFIG_3__hstfltrfrmdc            15
 180 #define   W_XGMAC_CONFIG_3__hstfltrfrmdc            16
 181 #define R_XGMAC_STATION_ADDRESS_LS      0x04
 182 #define   O_XGMAC_STATION_ADDRESS_LS__hstmacadr0    0
 183 #define   W_XGMAC_STATION_ADDRESS_LS__hstmacadr0    32
 184 #define R_XGMAC_STATION_ADDRESS_MS      0x05
 185 #define R_XGMAC_MAX_FRAME_LEN           0x08
 186 #define   O_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx       16
 187 #define   W_XGMAC_MAX_FRAME_LEN__hstmxfrmwctx       14
 188 #define   O_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx        0
 189 #define   W_XGMAC_MAX_FRAME_LEN__hstmxfrmbcrx       16
 190 #define R_XGMAC_REV_LEVEL               0x0B
 191 #define   O_XGMAC_REV_LEVEL__revlvl                  0
 192 #define   W_XGMAC_REV_LEVEL__revlvl                 15
 193 #define R_XGMAC_MIIM_COMMAND            0x10
 194 #define   O_XGMAC_MIIM_COMMAND__hstldcmd             3
 195 #define   O_XGMAC_MIIM_COMMAND__hstmiimcmd           0
 196 #define   W_XGMAC_MIIM_COMMAND__hstmiimcmd           3
 197 #define R_XGMAC_MIIM_FILED              0x11
 198 #define   O_XGMAC_MIIM_FILED__hststfield            30
 199 #define   W_XGMAC_MIIM_FILED__hststfield             2
 200 #define   O_XGMAC_MIIM_FILED__hstopfield            28
 201 #define   W_XGMAC_MIIM_FILED__hstopfield             2
 202 #define   O_XGMAC_MIIM_FILED__hstphyadx             23
 203 #define   W_XGMAC_MIIM_FILED__hstphyadx              5
 204 #define   O_XGMAC_MIIM_FILED__hstregadx             18
 205 #define   W_XGMAC_MIIM_FILED__hstregadx              5
 206 #define   O_XGMAC_MIIM_FILED__hsttafield            16
 207 #define   W_XGMAC_MIIM_FILED__hsttafield             2
 208 #define   O_XGMAC_MIIM_FILED__miimrddat              0
 209 #define   W_XGMAC_MIIM_FILED__miimrddat             16
 210 #define R_XGMAC_MIIM_CONFIG             0x12
 211 #define   O_XGMAC_MIIM_CONFIG__hstnopram             7
 212 #define   O_XGMAC_MIIM_CONFIG__hstclkdiv             0
 213 #define   W_XGMAC_MIIM_CONFIG__hstclkdiv             7
 214 #define R_XGMAC_MIIM_LINK_FAIL_VECTOR   0x13
 215 #define   O_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec   0
 216 #define   W_XGMAC_MIIM_LINK_FAIL_VECTOR__miimlfvec  32
 217 #define R_XGMAC_MIIM_INDICATOR          0x14
 218 #define   O_XGMAC_MIIM_INDICATOR__miimphylf          4
 219 #define   O_XGMAC_MIIM_INDICATOR__miimmoncplt        3
 220 #define   O_XGMAC_MIIM_INDICATOR__miimmonvld         2
 221 #define   O_XGMAC_MIIM_INDICATOR__miimmon            1
 222 #define   O_XGMAC_MIIM_INDICATOR__miimbusy           0
 223
 224 /* Glue logic register and bit field definitions */
 225 #define R_MAC_ADDR0                                                 0x50
 226 #define R_MAC_ADDR1                                                 0x52
 227 #define R_MAC_ADDR2                                                 0x54
 228 #define R_MAC_ADDR3                                                 0x56
 229 #define R_MAC_ADDR_MASK2                                            0x58
 230 #define R_MAC_ADDR_MASK3                                            0x5A
 231 #define R_MAC_FILTER_CONFIG                                         0x5C
 232 #define   O_MAC_FILTER_CONFIG__BROADCAST_EN                         10
 233 #define   O_MAC_FILTER_CONFIG__PAUSE_FRAME_EN                       9
 234 #define   O_MAC_FILTER_CONFIG__ALL_MCAST_EN                         8
 235 #define   O_MAC_FILTER_CONFIG__ALL_UCAST_EN                         7
 236 #define   O_MAC_FILTER_CONFIG__HASH_MCAST_EN                        6
 237 #define   O_MAC_FILTER_CONFIG__HASH_UCAST_EN                        5
 238 #define   O_MAC_FILTER_CONFIG__ADDR_MATCH_DISC                      4
 239 #define   O_MAC_FILTER_CONFIG__MAC_ADDR3_VALID                      3
 240 #define   O_MAC_FILTER_CONFIG__MAC_ADDR2_VALID                      2
 241 #define   O_MAC_FILTER_CONFIG__MAC_ADDR1_VALID                      1
 242 #define   O_MAC_FILTER_CONFIG__MAC_ADDR0_VALID                      0
 243 #define R_HASH_TABLE_VECTOR                                         0x30
 244 #define R_TX_CONTROL                                                 0x0A0
 245 #define   O_TX_CONTROL__Tx15Halt                                     31
 246 #define   O_TX_CONTROL__Tx14Halt                                     30
 247 #define   O_TX_CONTROL__Tx13Halt                                     29
 248 #define   O_TX_CONTROL__Tx12Halt                                     28
 249 #define   O_TX_CONTROL__Tx11Halt                                     27
 250 #define   O_TX_CONTROL__Tx10Halt                                     26
 251 #define   O_TX_CONTROL__Tx9Halt                                      25
 252 #define   O_TX_CONTROL__Tx8Halt                                      24
 253 #define   O_TX_CONTROL__Tx7Halt                                      23
 254 #define   O_TX_CONTROL__Tx6Halt                                      22
 255 #define   O_TX_CONTROL__Tx5Halt                                      21
 256 #define   O_TX_CONTROL__Tx4Halt                                      20
 257 #define   O_TX_CONTROL__Tx3Halt                                      19
 258 #define   O_TX_CONTROL__Tx2Halt                                      18
 259 #define   O_TX_CONTROL__Tx1Halt                                      17
 260 #define   O_TX_CONTROL__Tx0Halt                                      16
 261 #define   O_TX_CONTROL__TxIdle                                       15
 262 #define   O_TX_CONTROL__TxEnable                                     14
 263 #define   O_TX_CONTROL__TxThreshold                                  0
 264 #define   W_TX_CONTROL__TxThreshold                                  14
 265 #define R_RX_CONTROL                                                 0x0A1
 266 #define   O_RX_CONTROL__RGMII                                        10
 267 #define   O_RX_CONTROL__RxHalt                                       1
 268 #define   O_RX_CONTROL__RxEnable                                     0
 269 #define R_DESC_PACK_CTRL                                            0x0A2
 270 #define   O_DESC_PACK_CTRL__ByteOffset                              17
 271 #define   W_DESC_PACK_CTRL__ByteOffset                              3
 272 #define   O_DESC_PACK_CTRL__PrePadEnable                            16
 273 #define   O_DESC_PACK_CTRL__MaxEntry                                14
 274 #define   W_DESC_PACK_CTRL__MaxEntry                                2
 275 #define   O_DESC_PACK_CTRL__RegularSize                             0
 276 #define   W_DESC_PACK_CTRL__RegularSize                             14
 277 #define R_STATCTRL                                                  0x0A3
 278 #define   O_STATCTRL__OverFlowEn                                    4
 279 #define   O_STATCTRL__GIG                                           3
 280 #define   O_STATCTRL__Sten                                          2
 281 #define   O_STATCTRL__ClrCnt                                        1
 282 #define   O_STATCTRL__AutoZ                                         0
 283 #define R_L2ALLOCCTRL                                               0x0A4
 284 #define   O_L2ALLOCCTRL__TxL2Allocate                               9
 285 #define   W_L2ALLOCCTRL__TxL2Allocate                               9
 286 #define   O_L2ALLOCCTRL__RxL2Allocate                               0
 287 #define   W_L2ALLOCCTRL__RxL2Allocate                               9
 288 #define R_INTMASK                                                   0x0A5
 289 #define   O_INTMASK__Spi4TxError                                     28
 290 #define   O_INTMASK__Spi4RxError                                     27
 291 #define   O_INTMASK__RGMIIHalfDupCollision                           27
 292 #define   O_INTMASK__Abort                                           26
 293 #define   O_INTMASK__Underrun                                        25
 294 #define   O_INTMASK__DiscardPacket                                   24
 295 #define   O_INTMASK__AsyncFifoFull                                   23
 296 #define   O_INTMASK__TagFull                                         22
 297 #define   O_INTMASK__Class3Full                                      21
 298 #define   O_INTMASK__C3EarlyFull                                     20
 299 #define   O_INTMASK__Class2Full                                      19
 300 #define   O_INTMASK__C2EarlyFull                                     18
 301 #define   O_INTMASK__Class1Full                                      17
 302 #define   O_INTMASK__C1EarlyFull                                     16
 303 #define   O_INTMASK__Class0Full                                      15
 304 #define   O_INTMASK__C0EarlyFull                                     14
 305 #define   O_INTMASK__RxDataFull                                      13
 306 #define   O_INTMASK__RxEarlyFull                                     12
 307 #define   O_INTMASK__RFreeEmpty                                      9
 308 #define   O_INTMASK__RFEarlyEmpty                                    8
 309 #define   O_INTMASK__P2PSpillEcc                                     7
 310 #define   O_INTMASK__FreeDescFull                                    5
 311 #define   O_INTMASK__FreeEarlyFull                                   4
 312 #define   O_INTMASK__TxFetchError                                    3
 313 #define   O_INTMASK__StatCarry                                       2
 314 #define   O_INTMASK__MDInt                                           1
 315 #define   O_INTMASK__TxIllegal                                       0
 316 #define R_INTREG                                                    0x0A6
 317 #define   O_INTREG__Spi4TxError                                     28
 318 #define   O_INTREG__Spi4RxError                                     27
 319 #define   O_INTREG__RGMIIHalfDupCollision                           27
 320 #define   O_INTREG__Abort                                           26
 321 #define   O_INTREG__Underrun                                        25
 322 #define   O_INTREG__DiscardPacket                                   24
 323 #define   O_INTREG__AsyncFifoFull                                   23
 324 #define   O_INTREG__TagFull                                         22
 325 #define   O_INTREG__Class3Full                                      21
 326 #define   O_INTREG__C3EarlyFull                                     20
 327 #define   O_INTREG__Class2Full                                      19
 328 #define   O_INTREG__C2EarlyFull                                     18
 329 #define   O_INTREG__Class1Full                                      17
 330 #define   O_INTREG__C1EarlyFull                                     16
 331 #define   O_INTREG__Class0Full                                      15
 332 #define   O_INTREG__C0EarlyFull                                     14
 333 #define   O_INTREG__RxDataFull                                      13
 334 #define   O_INTREG__RxEarlyFull                                     12
 335 #define   O_INTREG__RFreeEmpty                                      9
 336 #define   O_INTREG__RFEarlyEmpty                                    8
 337 #define   O_INTREG__P2PSpillEcc                                     7
 338 #define   O_INTREG__FreeDescFull                                    5
 339 #define   O_INTREG__FreeEarlyFull                                   4
 340 #define   O_INTREG__TxFetchError                                    3
 341 #define   O_INTREG__StatCarry                                       2
 342 #define   O_INTREG__MDInt                                           1
 343 #define   O_INTREG__TxIllegal                                       0
 344 #define R_TXRETRY                                                   0x0A7
 345 #define   O_TXRETRY__CollisionRetry                                 6
 346 #define   O_TXRETRY__BusErrorRetry                                  5
 347 #define   O_TXRETRY__UnderRunRetry                                  4
 348 #define   O_TXRETRY__Retries                                        0
 349 #define   W_TXRETRY__Retries                                        4
 350 #define R_CORECONTROL                                               0x0A8
 351 #define   O_CORECONTROL__ErrorThread                                4
 352 #define   W_CORECONTROL__ErrorThread                                7
 353 #define   O_CORECONTROL__Shutdown                                   2
 354 #define   O_CORECONTROL__Speed                                      0
 355 #define   W_CORECONTROL__Speed                                      2
 356 #define R_BYTEOFFSET0                                               0x0A9
 357 #define R_BYTEOFFSET1                                               0x0AA
 358 #define R_L2TYPE_0                                                  0x0F0
 359 #define   O_L2TYPE__ExtraHdrProtoSize                               26
 360 #define   W_L2TYPE__ExtraHdrProtoSize                               5
 361 #define   O_L2TYPE__ExtraHdrProtoOffset                             20
 362 #define   W_L2TYPE__ExtraHdrProtoOffset                             6
 363 #define   O_L2TYPE__ExtraHeaderSize                                 14
 364 #define   W_L2TYPE__ExtraHeaderSize                                 6
 365 #define   O_L2TYPE__ProtoOffset                                     8
 366 #define   W_L2TYPE__ProtoOffset                                     6
 367 #define   O_L2TYPE__L2HdrOffset                                     2
 368 #define   W_L2TYPE__L2HdrOffset                                     6
 369 #define   O_L2TYPE__L2Proto                                         0
 370 #define   W_L2TYPE__L2Proto                                         2
 371 #define R_L2TYPE_1                                                  0xF0
 372 #define R_L2TYPE_2                                                  0xF0
 373 #define R_L2TYPE_3                                                  0xF0
 374 #define R_PARSERCONFIGREG                                           0x100
 375 #define   O_PARSERCONFIGREG__CRCHashPoly                            8
 376 #define   W_PARSERCONFIGREG__CRCHashPoly                            7
 377 #define   O_PARSERCONFIGREG__PrePadOffset                           4
 378 #define   W_PARSERCONFIGREG__PrePadOffset                           4
 379 #define   O_PARSERCONFIGREG__UseCAM                                 2
 380 #define   O_PARSERCONFIGREG__UseHASH                                1
 381 #define   O_PARSERCONFIGREG__UseProto                               0
 382 #define R_L3CTABLE                                                  0x140
 383 #define   O_L3CTABLE__Offset0                                       25
 384 #define   W_L3CTABLE__Offset0                                       7
 385 #define   O_L3CTABLE__Len0                                          21
 386 #define   W_L3CTABLE__Len0                                          4
 387 #define   O_L3CTABLE__Offset1                                       14
 388 #define   W_L3CTABLE__Offset1                                       7
 389 #define   O_L3CTABLE__Len1                                          10
 390 #define   W_L3CTABLE__Len1                                          4
 391 #define   O_L3CTABLE__Offset2                                       4
 392 #define   W_L3CTABLE__Offset2                                       6
 393 #define   O_L3CTABLE__Len2                                          0
 394 #define   W_L3CTABLE__Len2                                          4
 395 #define   O_L3CTABLE__L3HdrOffset                                   26
 396 #define   W_L3CTABLE__L3HdrOffset                                   6
 397 #define   O_L3CTABLE__L4ProtoOffset                                 20
 398 #define   W_L3CTABLE__L4ProtoOffset                                 6
 399 #define   O_L3CTABLE__IPChksumCompute                               19
 400 #define   O_L3CTABLE__L4Classify                                    18
 401 #define   O_L3CTABLE__L2Proto                                       16
 402 #define   W_L3CTABLE__L2Proto                                       2
 403 #define   O_L3CTABLE__L3ProtoKey                                    0
 404 #define   W_L3CTABLE__L3ProtoKey                                    16
 405 #define R_L4CTABLE                                                  0x160
 406 #define   O_L4CTABLE__Offset0                                       21
 407 #define   W_L4CTABLE__Offset0                                       6
 408 #define   O_L4CTABLE__Len0                                          17
 409 #define   W_L4CTABLE__Len0                                          4
 410 #define   O_L4CTABLE__Offset1                                       11
 411 #define   W_L4CTABLE__Offset1                                       6
 412 #define   O_L4CTABLE__Len1                                          7
 413 #define   W_L4CTABLE__Len1                                          4
 414 #define   O_L4CTABLE__TCPChksumEnable                               0
 415 #define R_CAM4X128TABLE                                             0x172
 416 #define   O_CAM4X128TABLE__ClassId                                  7
 417 #define   W_CAM4X128TABLE__ClassId                                  2
 418 #define   O_CAM4X128TABLE__BucketId                                 1
 419 #define   W_CAM4X128TABLE__BucketId                                 6
 420 #define   O_CAM4X128TABLE__UseBucket                                0
 421 #define R_CAM4X128KEY                                               0x180
 422 #define R_TRANSLATETABLE                                            0x1A0
 423 #define R_DMACR0                                                    0x200
 424 #define   O_DMACR0__Data0WrMaxCr                                    27
 425 #define   W_DMACR0__Data0WrMaxCr                                    3
 426 #define   O_DMACR0__Data0RdMaxCr                                    24
 427 #define   W_DMACR0__Data0RdMaxCr                                    3
 428 #define   O_DMACR0__Data1WrMaxCr                                    21
 429 #define   W_DMACR0__Data1WrMaxCr                                    3
 430 #define   O_DMACR0__Data1RdMaxCr                                    18
 431 #define   W_DMACR0__Data1RdMaxCr                                    3
 432 #define   O_DMACR0__Data2WrMaxCr                                    15
 433 #define   W_DMACR0__Data2WrMaxCr                                    3
 434 #define   O_DMACR0__Data2RdMaxCr                                    12
 435 #define   W_DMACR0__Data2RdMaxCr                                    3
 436 #define   O_DMACR0__Data3WrMaxCr                                    9
 437 #define   W_DMACR0__Data3WrMaxCr                                    3
 438 #define   O_DMACR0__Data3RdMaxCr                                    6
 439 #define   W_DMACR0__Data3RdMaxCr                                    3
 440 #define   O_DMACR0__Data4WrMaxCr                                    3
 441 #define   W_DMACR0__Data4WrMaxCr                                    3
 442 #define   O_DMACR0__Data4RdMaxCr                                    0
 443 #define   W_DMACR0__Data4RdMaxCr                                    3
 444 #define R_DMACR1                                                    0x201
 445 #define   O_DMACR1__Data5WrMaxCr                                    27
 446 #define   W_DMACR1__Data5WrMaxCr                                    3
 447 #define   O_DMACR1__Data5RdMaxCr                                    24
 448 #define   W_DMACR1__Data5RdMaxCr                                    3
 449 #define   O_DMACR1__Data6WrMaxCr                                    21
 450 #define   W_DMACR1__Data6WrMaxCr                                    3
 451 #define   O_DMACR1__Data6RdMaxCr                                    18
 452 #define   W_DMACR1__Data6RdMaxCr                                    3
 453 #define   O_DMACR1__Data7WrMaxCr                                    15
 454 #define   W_DMACR1__Data7WrMaxCr                                    3
 455 #define   O_DMACR1__Data7RdMaxCr                                    12
 456 #define   W_DMACR1__Data7RdMaxCr                                    3
 457 #define   O_DMACR1__Data8WrMaxCr                                    9
 458 #define   W_DMACR1__Data8WrMaxCr                                    3
 459 #define   O_DMACR1__Data8RdMaxCr                                    6
 460 #define   W_DMACR1__Data8RdMaxCr                                    3
 461 #define   O_DMACR1__Data9WrMaxCr                                    3
 462 #define   W_DMACR1__Data9WrMaxCr                                    3
 463 #define   O_DMACR1__Data9RdMaxCr                                    0
 464 #define   W_DMACR1__Data9RdMaxCr                                    3
 465 #define R_DMACR2                                                    0x202
 466 #define   O_DMACR2__Data10WrMaxCr                                   27
 467 #define   W_DMACR2__Data10WrMaxCr                                   3
 468 #define   O_DMACR2__Data10RdMaxCr                                   24
 469 #define   W_DMACR2__Data10RdMaxCr                                   3
 470 #define   O_DMACR2__Data11WrMaxCr                                   21
 471 #define   W_DMACR2__Data11WrMaxCr                                   3
 472 #define   O_DMACR2__Data11RdMaxCr                                   18
 473 #define   W_DMACR2__Data11RdMaxCr                                   3
 474 #define   O_DMACR2__Data12WrMaxCr                                   15
 475 #define   W_DMACR2__Data12WrMaxCr                                   3
 476 #define   O_DMACR2__Data12RdMaxCr                                   12
 477 #define   W_DMACR2__Data12RdMaxCr                                   3
 478 #define   O_DMACR2__Data13WrMaxCr                                   9
 479 #define   W_DMACR2__Data13WrMaxCr                                   3
 480 #define   O_DMACR2__Data13RdMaxCr                                   6
 481 #define   W_DMACR2__Data13RdMaxCr                                   3
 482 #define   O_DMACR2__Data14WrMaxCr                                   3
 483 #define   W_DMACR2__Data14WrMaxCr                                   3
 484 #define   O_DMACR2__Data14RdMaxCr                                   0
 485 #define   W_DMACR2__Data14RdMaxCr                                   3
 486 #define R_DMACR3                                                    0x203
 487 #define   O_DMACR3__Data15WrMaxCr                                   27
 488 #define   W_DMACR3__Data15WrMaxCr                                   3
 489 #define   O_DMACR3__Data15RdMaxCr                                   24
 490 #define   W_DMACR3__Data15RdMaxCr                                   3
 491 #define   O_DMACR3__SpClassWrMaxCr                                  21
 492 #define   W_DMACR3__SpClassWrMaxCr                                  3
 493 #define   O_DMACR3__SpClassRdMaxCr                                  18
 494 #define   W_DMACR3__SpClassRdMaxCr                                  3
 495 #define   O_DMACR3__JumFrInWrMaxCr                                  15
 496 #define   W_DMACR3__JumFrInWrMaxCr                                  3
 497 #define   O_DMACR3__JumFrInRdMaxCr                                  12
 498 #define   W_DMACR3__JumFrInRdMaxCr                                  3
 499 #define   O_DMACR3__RegFrInWrMaxCr                                  9
 500 #define   W_DMACR3__RegFrInWrMaxCr                                  3
 501 #define   O_DMACR3__RegFrInRdMaxCr                                  6
 502 #define   W_DMACR3__RegFrInRdMaxCr                                  3
 503 #define   O_DMACR3__FrOutWrMaxCr                                    3
 504 #define   W_DMACR3__FrOutWrMaxCr                                    3
 505 #define   O_DMACR3__FrOutRdMaxCr                                    0
 506 #define   W_DMACR3__FrOutRdMaxCr                                    3
 507 #define R_REG_FRIN_SPILL_MEM_START_0                                0x204
 508 #define   O_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0        0
 509 #define   W_REG_FRIN_SPILL_MEM_START_0__RegFrInSpillMemStart0       32
 510 #define R_REG_FRIN_SPILL_MEM_START_1                                0x205
 511 #define   O_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1        0
 512 #define   W_REG_FRIN_SPILL_MEM_START_1__RegFrInSpillMemStart1        3
 513 #define R_REG_FRIN_SPILL_MEM_SIZE                                   0x206
 514 #define   O_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize             0
 515 #define   W_REG_FRIN_SPILL_MEM_SIZE__RegFrInSpillMemSize            32
 516 #define R_FROUT_SPILL_MEM_START_0                                   0x207
 517 #define   O_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0             0
 518 #define   W_FROUT_SPILL_MEM_START_0__FrOutSpillMemStart0            32
 519 #define R_FROUT_SPILL_MEM_START_1                                   0x208
 520 #define   O_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1             0
 521 #define   W_FROUT_SPILL_MEM_START_1__FrOutSpillMemStart1             3
 522 #define R_FROUT_SPILL_MEM_SIZE                                      0x209
 523 #define   O_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize                  0
 524 #define   W_FROUT_SPILL_MEM_SIZE__FrOutSpillMemSize                 32
 525 #define R_CLASS0_SPILL_MEM_START_0                                  0x20A
 526 #define   O_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0           0
 527 #define   W_CLASS0_SPILL_MEM_START_0__Class0SpillMemStart0          32
 528 #define R_CLASS0_SPILL_MEM_START_1                                  0x20B
 529 #define   O_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1           0
 530 #define   W_CLASS0_SPILL_MEM_START_1__Class0SpillMemStart1           3
 531 #define R_CLASS0_SPILL_MEM_SIZE                                     0x20C
 532 #define   O_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize                0
 533 #define   W_CLASS0_SPILL_MEM_SIZE__Class0SpillMemSize               32
 534 #define R_JUMFRIN_SPILL_MEM_START_0                                 0x20D
 535 #define   O_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0          0
 536 #define   W_JUMFRIN_SPILL_MEM_START_0__JumFrInSpillMemStar0         32
 537 #define R_JUMFRIN_SPILL_MEM_START_1                                 0x20E
 538 #define   O_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1         0
 539 #define   W_JUMFRIN_SPILL_MEM_START_1__JumFrInSpillMemStart1         3
 540 #define R_JUMFRIN_SPILL_MEM_SIZE                                    0x20F
 541 #define   O_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize              0
 542 #define   W_JUMFRIN_SPILL_MEM_SIZE__JumFrInSpillMemSize             32
 543 #define R_CLASS1_SPILL_MEM_START_0                                  0x210
 544 #define   O_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0           0
 545 #define   W_CLASS1_SPILL_MEM_START_0__Class1SpillMemStart0          32
 546 #define R_CLASS1_SPILL_MEM_START_1                                  0x211
 547 #define   O_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1           0
 548 #define   W_CLASS1_SPILL_MEM_START_1__Class1SpillMemStart1           3
 549 #define R_CLASS1_SPILL_MEM_SIZE                                     0x212
 550 #define   O_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize                0
 551 #define   W_CLASS1_SPILL_MEM_SIZE__Class1SpillMemSize               32
 552 #define R_CLASS2_SPILL_MEM_START_0                                  0x213
 553 #define   O_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0           0
 554 #define   W_CLASS2_SPILL_MEM_START_0__Class2SpillMemStart0          32
 555 #define R_CLASS2_SPILL_MEM_START_1                                  0x214
 556 #define   O_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1           0
 557 #define   W_CLASS2_SPILL_MEM_START_1__Class2SpillMemStart1           3
 558 #define R_CLASS2_SPILL_MEM_SIZE                                     0x215
 559 #define   O_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize                0
 560 #define   W_CLASS2_SPILL_MEM_SIZE__Class2SpillMemSize               32
 561 #define R_CLASS3_SPILL_MEM_START_0                                  0x216
 562 #define   O_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0           0
 563 #define   W_CLASS3_SPILL_MEM_START_0__Class3SpillMemStart0          32
 564 #define R_CLASS3_SPILL_MEM_START_1                                  0x217
 565 #define   O_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1           0
 566 #define   W_CLASS3_SPILL_MEM_START_1__Class3SpillMemStart1           3
 567 #define R_CLASS3_SPILL_MEM_SIZE                                     0x218
 568 #define   O_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize                0
 569 #define   W_CLASS3_SPILL_MEM_SIZE__Class3SpillMemSize               32
 570 #define R_REG_FRIN1_SPILL_MEM_START_0                               0x219
 571 #define R_REG_FRIN1_SPILL_MEM_START_1                               0x21a
 572 #define R_REG_FRIN1_SPILL_MEM_SIZE                                  0x21b
 573 #define R_SPIHNGY0                                                  0x219
 574 #define   O_SPIHNGY0__EG_HNGY_THRESH_0                              24
 575 #define   W_SPIHNGY0__EG_HNGY_THRESH_0                              7
 576 #define   O_SPIHNGY0__EG_HNGY_THRESH_1                              16
 577 #define   W_SPIHNGY0__EG_HNGY_THRESH_1                              7
 578 #define   O_SPIHNGY0__EG_HNGY_THRESH_2                              8
 579 #define   W_SPIHNGY0__EG_HNGY_THRESH_2                              7
 580 #define   O_SPIHNGY0__EG_HNGY_THRESH_3                              0
 581 #define   W_SPIHNGY0__EG_HNGY_THRESH_3                              7
 582 #define R_SPIHNGY1                                                  0x21A
 583 #define   O_SPIHNGY1__EG_HNGY_THRESH_4                              24
 584 #define   W_SPIHNGY1__EG_HNGY_THRESH_4                              7
 585 #define   O_SPIHNGY1__EG_HNGY_THRESH_5                              16
 586 #define   W_SPIHNGY1__EG_HNGY_THRESH_5                              7
 587 #define   O_SPIHNGY1__EG_HNGY_THRESH_6                              8
 588 #define   W_SPIHNGY1__EG_HNGY_THRESH_6                              7
 589 #define   O_SPIHNGY1__EG_HNGY_THRESH_7                              0
 590 #define   W_SPIHNGY1__EG_HNGY_THRESH_7                              7
 591 #define R_SPIHNGY2                                                  0x21B
 592 #define   O_SPIHNGY2__EG_HNGY_THRESH_8                              24
 593 #define   W_SPIHNGY2__EG_HNGY_THRESH_8                              7
 594 #define   O_SPIHNGY2__EG_HNGY_THRESH_9                              16
 595 #define   W_SPIHNGY2__EG_HNGY_THRESH_9                              7
 596 #define   O_SPIHNGY2__EG_HNGY_THRESH_10                             8
 597 #define   W_SPIHNGY2__EG_HNGY_THRESH_10                             7
 598 #define   O_SPIHNGY2__EG_HNGY_THRESH_11                             0
 599 #define   W_SPIHNGY2__EG_HNGY_THRESH_11                             7
 600 #define R_SPIHNGY3                                                  0x21C
 601 #define   O_SPIHNGY3__EG_HNGY_THRESH_12                             24
 602 #define   W_SPIHNGY3__EG_HNGY_THRESH_12                             7
 603 #define   O_SPIHNGY3__EG_HNGY_THRESH_13                             16
 604 #define   W_SPIHNGY3__EG_HNGY_THRESH_13                             7
 605 #define   O_SPIHNGY3__EG_HNGY_THRESH_14                             8
 606 #define   W_SPIHNGY3__EG_HNGY_THRESH_14                             7
 607 #define   O_SPIHNGY3__EG_HNGY_THRESH_15                             0
 608 #define   W_SPIHNGY3__EG_HNGY_THRESH_15                             7
 609 #define R_SPISTRV0                                                  0x21D
 610 #define   O_SPISTRV0__EG_STRV_THRESH_0                              24
 611 #define   W_SPISTRV0__EG_STRV_THRESH_0                              7
 612 #define   O_SPISTRV0__EG_STRV_THRESH_1                              16
 613 #define   W_SPISTRV0__EG_STRV_THRESH_1                              7
 614 #define   O_SPISTRV0__EG_STRV_THRESH_2                              8
 615 #define   W_SPISTRV0__EG_STRV_THRESH_2                              7
 616 #define   O_SPISTRV0__EG_STRV_THRESH_3                              0
 617 #define   W_SPISTRV0__EG_STRV_THRESH_3                              7
 618 #define R_SPISTRV1                                                  0x21E
 619 #define   O_SPISTRV1__EG_STRV_THRESH_4                              24
 620 #define   W_SPISTRV1__EG_STRV_THRESH_4                              7
 621 #define   O_SPISTRV1__EG_STRV_THRESH_5                              16
 622 #define   W_SPISTRV1__EG_STRV_THRESH_5                              7
 623 #define   O_SPISTRV1__EG_STRV_THRESH_6                              8
 624 #define   W_SPISTRV1__EG_STRV_THRESH_6                              7
 625 #define   O_SPISTRV1__EG_STRV_THRESH_7                              0
 626 #define   W_SPISTRV1__EG_STRV_THRESH_7                              7
 627 #define R_SPISTRV2                                                  0x21F
 628 #define   O_SPISTRV2__EG_STRV_THRESH_8                              24
 629 #define   W_SPISTRV2__EG_STRV_THRESH_8                              7
 630 #define   O_SPISTRV2__EG_STRV_THRESH_9                              16
 631 #define   W_SPISTRV2__EG_STRV_THRESH_9                              7
 632 #define   O_SPISTRV2__EG_STRV_THRESH_10                             8
 633 #define   W_SPISTRV2__EG_STRV_THRESH_10                             7
 634 #define   O_SPISTRV2__EG_STRV_THRESH_11                             0
 635 #define   W_SPISTRV2__EG_STRV_THRESH_11                             7
 636 #define R_SPISTRV3                                                  0x220
 637 #define   O_SPISTRV3__EG_STRV_THRESH_12                             24
 638 #define   W_SPISTRV3__EG_STRV_THRESH_12                             7
 639 #define   O_SPISTRV3__EG_STRV_THRESH_13                             16
 640 #define   W_SPISTRV3__EG_STRV_THRESH_13                             7
 641 #define   O_SPISTRV3__EG_STRV_THRESH_14                             8
 642 #define   W_SPISTRV3__EG_STRV_THRESH_14                             7
 643 #define   O_SPISTRV3__EG_STRV_THRESH_15                             0
 644 #define   W_SPISTRV3__EG_STRV_THRESH_15                             7
 645 #define R_TXDATAFIFO0                                               0x221
 646 #define   O_TXDATAFIFO0__Tx0DataFifoStart                           24
 647 #define   W_TXDATAFIFO0__Tx0DataFifoStart                           7
 648 #define   O_TXDATAFIFO0__Tx0DataFifoSize                            16
 649 #define   W_TXDATAFIFO0__Tx0DataFifoSize                            7
 650 #define   O_TXDATAFIFO0__Tx1DataFifoStart                           8
 651 #define   W_TXDATAFIFO0__Tx1DataFifoStart                           7
 652 #define   O_TXDATAFIFO0__Tx1DataFifoSize                            0
 653 #define   W_TXDATAFIFO0__Tx1DataFifoSize                            7
 654 #define R_TXDATAFIFO1                                               0x222
 655 #define   O_TXDATAFIFO1__Tx2DataFifoStart                           24
 656 #define   W_TXDATAFIFO1__Tx2DataFifoStart                           7
 657 #define   O_TXDATAFIFO1__Tx2DataFifoSize                            16
 658 #define   W_TXDATAFIFO1__Tx2DataFifoSize                            7
 659 #define   O_TXDATAFIFO1__Tx3DataFifoStart                           8
 660 #define   W_TXDATAFIFO1__Tx3DataFifoStart                           7
 661 #define   O_TXDATAFIFO1__Tx3DataFifoSize                            0
 662 #define   W_TXDATAFIFO1__Tx3DataFifoSize                            7
 663 #define R_TXDATAFIFO2                                               0x223
 664 #define   O_TXDATAFIFO2__Tx4DataFifoStart                           24
 665 #define   W_TXDATAFIFO2__Tx4DataFifoStart                           7
 666 #define   O_TXDATAFIFO2__Tx4DataFifoSize                            16
 667 #define   W_TXDATAFIFO2__Tx4DataFifoSize                            7
 668 #define   O_TXDATAFIFO2__Tx5DataFifoStart                           8
 669 #define   W_TXDATAFIFO2__Tx5DataFifoStart                           7
 670 #define   O_TXDATAFIFO2__Tx5DataFifoSize                            0
 671 #define   W_TXDATAFIFO2__Tx5DataFifoSize                            7
 672 #define R_TXDATAFIFO3                                               0x224
 673 #define   O_TXDATAFIFO3__Tx6DataFifoStart                           24
 674 #define   W_TXDATAFIFO3__Tx6DataFifoStart                           7
 675 #define   O_TXDATAFIFO3__Tx6DataFifoSize                            16
 676 #define   W_TXDATAFIFO3__Tx6DataFifoSize                            7
 677 #define   O_TXDATAFIFO3__Tx7DataFifoStart                           8
 678 #define   W_TXDATAFIFO3__Tx7DataFifoStart                           7
 679 #define   O_TXDATAFIFO3__Tx7DataFifoSize                            0
 680 #define   W_TXDATAFIFO3__Tx7DataFifoSize                            7
 681 #define R_TXDATAFIFO4                                               0x225
 682 #define   O_TXDATAFIFO4__Tx8DataFifoStart                           24
 683 #define   W_TXDATAFIFO4__Tx8DataFifoStart                           7
 684 #define   O_TXDATAFIFO4__Tx8DataFifoSize                            16
 685 #define   W_TXDATAFIFO4__Tx8DataFifoSize                            7
 686 #define   O_TXDATAFIFO4__Tx9DataFifoStart                           8
 687 #define   W_TXDATAFIFO4__Tx9DataFifoStart                           7
 688 #define   O_TXDATAFIFO4__Tx9DataFifoSize                            0
 689 #define   W_TXDATAFIFO4__Tx9DataFifoSize                            7
 690 #define R_TXDATAFIFO5                                               0x226
 691 #define   O_TXDATAFIFO5__Tx10DataFifoStart                          24
 692 #define   W_TXDATAFIFO5__Tx10DataFifoStart                          7
 693 #define   O_TXDATAFIFO5__Tx10DataFifoSize                           16
 694 #define   W_TXDATAFIFO5__Tx10DataFifoSize                           7
 695 #define   O_TXDATAFIFO5__Tx11DataFifoStart                          8
 696 #define   W_TXDATAFIFO5__Tx11DataFifoStart                          7
 697 #define   O_TXDATAFIFO5__Tx11DataFifoSize                           0
 698 #define   W_TXDATAFIFO5__Tx11DataFifoSize                           7
 699 #define R_TXDATAFIFO6                                               0x227
 700 #define   O_TXDATAFIFO6__Tx12DataFifoStart                          24
 701 #define   W_TXDATAFIFO6__Tx12DataFifoStart                          7
 702 #define   O_TXDATAFIFO6__Tx12DataFifoSize                           16
 703 #define   W_TXDATAFIFO6__Tx12DataFifoSize                           7
 704 #define   O_TXDATAFIFO6__Tx13DataFifoStart                          8
 705 #define   W_TXDATAFIFO6__Tx13DataFifoStart                          7
 706 #define   O_TXDATAFIFO6__Tx13DataFifoSize                           0
 707 #define   W_TXDATAFIFO6__Tx13DataFifoSize                           7
 708 #define R_TXDATAFIFO7                                               0x228
 709 #define   O_TXDATAFIFO7__Tx14DataFifoStart                          24
 710 #define   W_TXDATAFIFO7__Tx14DataFifoStart                          7
 711 #define   O_TXDATAFIFO7__Tx14DataFifoSize                           16
 712 #define   W_TXDATAFIFO7__Tx14DataFifoSize                           7
 713 #define   O_TXDATAFIFO7__Tx15DataFifoStart                          8
 714 #define   W_TXDATAFIFO7__Tx15DataFifoStart                          7
 715 #define   O_TXDATAFIFO7__Tx15DataFifoSize                           0
 716 #define   W_TXDATAFIFO7__Tx15DataFifoSize                           7
 717 #define R_RXDATAFIFO0                                               0x229
 718 #define   O_RXDATAFIFO0__Rx0DataFifoStart                           24
 719 #define   W_RXDATAFIFO0__Rx0DataFifoStart                           7
 720 #define   O_RXDATAFIFO0__Rx0DataFifoSize                            16
 721 #define   W_RXDATAFIFO0__Rx0DataFifoSize                            7
 722 #define   O_RXDATAFIFO0__Rx1DataFifoStart                           8
 723 #define   W_RXDATAFIFO0__Rx1DataFifoStart                           7
 724 #define   O_RXDATAFIFO0__Rx1DataFifoSize                            0
 725 #define   W_RXDATAFIFO0__Rx1DataFifoSize                            7
 726 #define R_RXDATAFIFO1                                               0x22A
 727 #define   O_RXDATAFIFO1__Rx2DataFifoStart                           24
 728 #define   W_RXDATAFIFO1__Rx2DataFifoStart                           7
 729 #define   O_RXDATAFIFO1__Rx2DataFifoSize                            16
 730 #define   W_RXDATAFIFO1__Rx2DataFifoSize                            7
 731 #define   O_RXDATAFIFO1__Rx3DataFifoStart                           8
 732 #define   W_RXDATAFIFO1__Rx3DataFifoStart                           7
 733 #define   O_RXDATAFIFO1__Rx3DataFifoSize                            0
 734 #define   W_RXDATAFIFO1__Rx3DataFifoSize                            7
 735 #define R_RXDATAFIFO2                                               0x22B
 736 #define   O_RXDATAFIFO2__Rx4DataFifoStart                           24
 737 #define   W_RXDATAFIFO2__Rx4DataFifoStart                           7
 738 #define   O_RXDATAFIFO2__Rx4DataFifoSize                            16
 739 #define   W_RXDATAFIFO2__Rx4DataFifoSize                            7
 740 #define   O_RXDATAFIFO2__Rx5DataFifoStart                           8
 741 #define   W_RXDATAFIFO2__Rx5DataFifoStart                           7
 742 #define   O_RXDATAFIFO2__Rx5DataFifoSize                            0
 743 #define   W_RXDATAFIFO2__Rx5DataFifoSize                            7
 744 #define R_RXDATAFIFO3                                               0x22C
 745 #define   O_RXDATAFIFO3__Rx6DataFifoStart                           24
 746 #define   W_RXDATAFIFO3__Rx6DataFifoStart                           7
 747 #define   O_RXDATAFIFO3__Rx6DataFifoSize                            16
 748 #define   W_RXDATAFIFO3__Rx6DataFifoSize                            7
 749 #define   O_RXDATAFIFO3__Rx7DataFifoStart                           8
 750 #define   W_RXDATAFIFO3__Rx7DataFifoStart                           7
 751 #define   O_RXDATAFIFO3__Rx7DataFifoSize                            0
 752 #define   W_RXDATAFIFO3__Rx7DataFifoSize                            7
 753 #define R_RXDATAFIFO4                                               0x22D
 754 #define   O_RXDATAFIFO4__Rx8DataFifoStart                           24
 755 #define   W_RXDATAFIFO4__Rx8DataFifoStart                           7
 756 #define   O_RXDATAFIFO4__Rx8DataFifoSize                            16
 757 #define   W_RXDATAFIFO4__Rx8DataFifoSize                            7
 758 #define   O_RXDATAFIFO4__Rx9DataFifoStart                           8
 759 #define   W_RXDATAFIFO4__Rx9DataFifoStart                           7
 760 #define   O_RXDATAFIFO4__Rx9DataFifoSize                            0
 761 #define   W_RXDATAFIFO4__Rx9DataFifoSize                            7
 762 #define R_RXDATAFIFO5                                               0x22E
 763 #define   O_RXDATAFIFO5__Rx10DataFifoStart                          24
 764 #define   W_RXDATAFIFO5__Rx10DataFifoStart                          7
 765 #define   O_RXDATAFIFO5__Rx10DataFifoSize                           16
 766 #define   W_RXDATAFIFO5__Rx10DataFifoSize                           7
 767 #define   O_RXDATAFIFO5__Rx11DataFifoStart                          8
 768 #define   W_RXDATAFIFO5__Rx11DataFifoStart                          7
 769 #define   O_RXDATAFIFO5__Rx11DataFifoSize                           0
 770 #define   W_RXDATAFIFO5__Rx11DataFifoSize                           7
 771 #define R_RXDATAFIFO6                                               0x22F
 772 #define   O_RXDATAFIFO6__Rx12DataFifoStart                          24
 773 #define   W_RXDATAFIFO6__Rx12DataFifoStart                          7
 774 #define   O_RXDATAFIFO6__Rx12DataFifoSize                           16
 775 #define   W_RXDATAFIFO6__Rx12DataFifoSize                           7
 776 #define   O_RXDATAFIFO6__Rx13DataFifoStart                          8
 777 #define   W_RXDATAFIFO6__Rx13DataFifoStart                          7
 778 #define   O_RXDATAFIFO6__Rx13DataFifoSize                           0
 779 #define   W_RXDATAFIFO6__Rx13DataFifoSize                           7
 780 #define R_RXDATAFIFO7                                               0x230
 781 #define   O_RXDATAFIFO7__Rx14DataFifoStart                          24
 782 #define   W_RXDATAFIFO7__Rx14DataFifoStart                          7
 783 #define   O_RXDATAFIFO7__Rx14DataFifoSize                           16
 784 #define   W_RXDATAFIFO7__Rx14DataFifoSize                           7
 785 #define   O_RXDATAFIFO7__Rx15DataFifoStart                          8
 786 #define   W_RXDATAFIFO7__Rx15DataFifoStart                          7
 787 #define   O_RXDATAFIFO7__Rx15DataFifoSize                           0
 788 #define   W_RXDATAFIFO7__Rx15DataFifoSize                           7
 789 #define R_XGMACPADCALIBRATION                                       0x231
 790 #define R_FREEQCARVE                                                0x233
 791 #define R_SPI4STATICDELAY0                                          0x240
 792 #define   O_SPI4STATICDELAY0__DataLine7                             28
 793 #define   W_SPI4STATICDELAY0__DataLine7                             4
 794 #define   O_SPI4STATICDELAY0__DataLine6                             24
 795 #define   W_SPI4STATICDELAY0__DataLine6                             4
 796 #define   O_SPI4STATICDELAY0__DataLine5                             20
 797 #define   W_SPI4STATICDELAY0__DataLine5                             4
 798 #define   O_SPI4STATICDELAY0__DataLine4                             16
 799 #define   W_SPI4STATICDELAY0__DataLine4                             4
 800 #define   O_SPI4STATICDELAY0__DataLine3                             12
 801 #define   W_SPI4STATICDELAY0__DataLine3                             4
 802 #define   O_SPI4STATICDELAY0__DataLine2                             8
 803 #define   W_SPI4STATICDELAY0__DataLine2                             4
 804 #define   O_SPI4STATICDELAY0__DataLine1                             4
 805 #define   W_SPI4STATICDELAY0__DataLine1                             4
 806 #define   O_SPI4STATICDELAY0__DataLine0                             0
 807 #define   W_SPI4STATICDELAY0__DataLine0                             4
 808 #define R_SPI4STATICDELAY1                                          0x241
 809 #define   O_SPI4STATICDELAY1__DataLine15                            28
 810 #define   W_SPI4STATICDELAY1__DataLine15                            4
 811 #define   O_SPI4STATICDELAY1__DataLine14                            24
 812 #define   W_SPI4STATICDELAY1__DataLine14                            4
 813 #define   O_SPI4STATICDELAY1__DataLine13                            20
 814 #define   W_SPI4STATICDELAY1__DataLine13                            4
 815 #define   O_SPI4STATICDELAY1__DataLine12                            16
 816 #define   W_SPI4STATICDELAY1__DataLine12                            4
 817 #define   O_SPI4STATICDELAY1__DataLine11                            12
 818 #define   W_SPI4STATICDELAY1__DataLine11                            4
 819 #define   O_SPI4STATICDELAY1__DataLine10                            8
 820 #define   W_SPI4STATICDELAY1__DataLine10                            4
 821 #define   O_SPI4STATICDELAY1__DataLine9                             4
 822 #define   W_SPI4STATICDELAY1__DataLine9                             4
 823 #define   O_SPI4STATICDELAY1__DataLine8                             0
 824 #define   W_SPI4STATICDELAY1__DataLine8                             4
 825 #define R_SPI4STATICDELAY2                                          0x242
 826 #define   O_SPI4STATICDELAY0__TxStat1                               8
 827 #define   W_SPI4STATICDELAY0__TxStat1                               4
 828 #define   O_SPI4STATICDELAY0__TxStat0                               4
 829 #define   W_SPI4STATICDELAY0__TxStat0                               4
 830 #define   O_SPI4STATICDELAY0__RxControl                             0
 831 #define   W_SPI4STATICDELAY0__RxControl                             4
 832 #define R_SPI4CONTROL                                               0x243
 833 #define   O_SPI4CONTROL__StaticDelay                                2
 834 #define   O_SPI4CONTROL__LVDS_LVTTL                                 1
 835 #define   O_SPI4CONTROL__SPI4Enable                                 0
 836 #define R_CLASSWATERMARKS                                           0x244
 837 #define   O_CLASSWATERMARKS__Class0Watermark                        24
 838 #define   W_CLASSWATERMARKS__Class0Watermark                        5
 839 #define   O_CLASSWATERMARKS__Class1Watermark                        16
 840 #define   W_CLASSWATERMARKS__Class1Watermark                        5
 841 #define   O_CLASSWATERMARKS__Class3Watermark                        0
 842 #define   W_CLASSWATERMARKS__Class3Watermark                        5
 843 #define R_RXWATERMARKS1                                              0x245
 844 #define   O_RXWATERMARKS__Rx0DataWatermark                          24
 845 #define   W_RXWATERMARKS__Rx0DataWatermark                          7
 846 #define   O_RXWATERMARKS__Rx1DataWatermark                          16
 847 #define   W_RXWATERMARKS__Rx1DataWatermark                          7
 848 #define   O_RXWATERMARKS__Rx3DataWatermark                          0
 849 #define   W_RXWATERMARKS__Rx3DataWatermark                          7
 850 #define R_RXWATERMARKS2                                              0x246
 851 #define   O_RXWATERMARKS__Rx4DataWatermark                          24
 852 #define   W_RXWATERMARKS__Rx4DataWatermark                          7
 853 #define   O_RXWATERMARKS__Rx5DataWatermark                          16
 854 #define   W_RXWATERMARKS__Rx5DataWatermark                          7
 855 #define   O_RXWATERMARKS__Rx6DataWatermark                          8
 856 #define   W_RXWATERMARKS__Rx6DataWatermark                          7
 857 #define   O_RXWATERMARKS__Rx7DataWatermark                          0
 858 #define   W_RXWATERMARKS__Rx7DataWatermark                          7
 859 #define R_RXWATERMARKS3                                              0x247
 860 #define   O_RXWATERMARKS__Rx8DataWatermark                          24
 861 #define   W_RXWATERMARKS__Rx8DataWatermark                          7
 862 #define   O_RXWATERMARKS__Rx9DataWatermark                          16
 863 #define   W_RXWATERMARKS__Rx9DataWatermark                          7
 864 #define   O_RXWATERMARKS__Rx10DataWatermark                         8
 865 #define   W_RXWATERMARKS__Rx10DataWatermark                         7
 866 #define   O_RXWATERMARKS__Rx11DataWatermark                         0
 867 #define   W_RXWATERMARKS__Rx11DataWatermark                         7
 868 #define R_RXWATERMARKS4                                              0x248
 869 #define   O_RXWATERMARKS__Rx12DataWatermark                         24
 870 #define   W_RXWATERMARKS__Rx12DataWatermark                         7
 871 #define   O_RXWATERMARKS__Rx13DataWatermark                         16
 872 #define   W_RXWATERMARKS__Rx13DataWatermark                         7
 873 #define   O_RXWATERMARKS__Rx14DataWatermark                         8
 874 #define   W_RXWATERMARKS__Rx14DataWatermark                         7
 875 #define   O_RXWATERMARKS__Rx15DataWatermark                         0
 876 #define   W_RXWATERMARKS__Rx15DataWatermark                         7
 877 #define R_FREEWATERMARKS                                            0x249
 878 #define   O_FREEWATERMARKS__FreeOutWatermark                        16
 879 #define   W_FREEWATERMARKS__FreeOutWatermark                        16
 880 #define   O_FREEWATERMARKS__JumFrWatermark                          8
 881 #define   W_FREEWATERMARKS__JumFrWatermark                          7
 882 #define   O_FREEWATERMARKS__RegFrWatermark                          0
 883 #define   W_FREEWATERMARKS__RegFrWatermark                          7
 884 #define R_EGRESSFIFOCARVINGSLOTS                                    0x24a
 885
 886 #define CTRL_RES0           0
 887 #define CTRL_RES1           1
 888 #define CTRL_REG_FREE       2
 889 #define CTRL_JUMBO_FREE     3
 890 #define CTRL_CONT           4
 891 #define CTRL_EOP            5
 892 #define CTRL_START          6
 893 #define CTRL_SNGL           7
 894
 895 #define CTRL_B0_NOT_EOP     0
 896 #define CTRL_B0_EOP         1
 897
 898 #define R_ROUND_ROBIN_TABLE                 0
 899 #define R_PDE_CLASS_0                       0x300
 900 #define R_PDE_CLASS_1                       0x302
 901 #define R_PDE_CLASS_2                       0x304
 902 #define R_PDE_CLASS_3                       0x306
 903
 904 #define R_MSG_TX_THRESHOLD                  0x308
 905
 906 #define R_GMAC_JFR0_BUCKET_SIZE              0x320
 907 #define R_GMAC_RFR0_BUCKET_SIZE              0x321
 908 #define R_GMAC_TX0_BUCKET_SIZE              0x322
 909 #define R_GMAC_TX1_BUCKET_SIZE              0x323
 910 #define R_GMAC_TX2_BUCKET_SIZE              0x324
 911 #define R_GMAC_TX3_BUCKET_SIZE              0x325
 912 #define R_GMAC_JFR1_BUCKET_SIZE              0x326
 913 #define R_GMAC_RFR1_BUCKET_SIZE              0x327
 914
 915 #define R_XGS_TX0_BUCKET_SIZE               0x320
 916 #define R_XGS_TX1_BUCKET_SIZE               0x321
 917 #define R_XGS_TX2_BUCKET_SIZE               0x322
 918 #define R_XGS_TX3_BUCKET_SIZE               0x323
 919 #define R_XGS_TX4_BUCKET_SIZE               0x324
 920 #define R_XGS_TX5_BUCKET_SIZE               0x325
 921 #define R_XGS_TX6_BUCKET_SIZE               0x326
 922 #define R_XGS_TX7_BUCKET_SIZE               0x327
 923 #define R_XGS_TX8_BUCKET_SIZE               0x328
 924 #define R_XGS_TX9_BUCKET_SIZE               0x329
 925 #define R_XGS_TX10_BUCKET_SIZE              0x32A
 926 #define R_XGS_TX11_BUCKET_SIZE              0x32B
 927 #define R_XGS_TX12_BUCKET_SIZE              0x32C
 928 #define R_XGS_TX13_BUCKET_SIZE              0x32D
 929 #define R_XGS_TX14_BUCKET_SIZE              0x32E
 930 #define R_XGS_TX15_BUCKET_SIZE              0x32F
 931 #define R_XGS_JFR_BUCKET_SIZE               0x330
 932 #define R_XGS_RFR_BUCKET_SIZE               0x331
 933
 934 #define R_CC_CPU0_0                         0x380
 935 #define R_CC_CPU1_0                         0x388
 936 #define R_CC_CPU2_0                         0x390
 937 #define R_CC_CPU3_0                         0x398
 938 #define R_CC_CPU4_0                         0x3a0
 939 #define R_CC_CPU5_0                         0x3a8
 940 #define R_CC_CPU6_0                         0x3b0
 941 #define R_CC_CPU7_0                         0x3b8
 942
 943 typedef enum {
 944         xlr_mac_speed_10, xlr_mac_speed_100,
 945         xlr_mac_speed_1000, xlr_mac_speed_rsvd
 946 }    xlr_mac_speed_t;
 947
 948 typedef enum {
 949         xlr_mac_duplex_auto, xlr_mac_duplex_half,
 950         xlr_mac_duplex_full
 951 }    xlr_mac_duplex_t;
 952
 953 typedef enum {
 954         xlr_mac_link_down,
 955         xlr_mac_link_up,
 956 }    xlr_mac_link_t;
 957
 958 typedef enum {
 959         xlr_mac_fc_auto, xlr_mac_fc_disabled, xlr_mac_fc_frame,
 960         xlr_mac_fc_collision, xlr_mac_fc_carrier
 961 }    xlr_mac_fc_t;
 962
 963 /* static int mac_frin_to_be_sent_thr[8]; */
 964
 965 enum {
 966         PORT_TX,
 967         PORT_TX_COMPLETE,
 968         PORT_STARTQ,
 969         PORT_STOPQ,
 970         PORT_START_DEV_STATE,
 971         PORT_STOP_DEV_STATE,
 972 };
 973
 974 struct rge_softc_stats {
 975         unsigned long rx_frames;
 976         unsigned long tx_frames;
 977         unsigned long rx_packets;
 978         unsigned long rx_bytes;
 979         unsigned long tx_packets;
 980         unsigned long tx_bytes;
 981 };
 982
 983 struct driver_data {
 984
 985         /*
 986          * Let these be the first fields in this structure the structure is
 987          * cacheline aligned when allocated in init_etherdev
 988          */
 989         struct fr_desc *frin_spill;
 990         struct fr_desc *frout_spill;
 991         union rx_tx_desc *class_0_spill;
 992         union rx_tx_desc *class_1_spill;
 993         union rx_tx_desc *class_2_spill;
 994         union rx_tx_desc *class_3_spill;
 995         int spill_configured;
 996
 997         struct rge_softc *sc;   /* pointer to freebsd device soft-pointer */
 998         struct rge_softc_stats stats;
 999         struct mtx lock;
1000
1001         xlr_reg_t *mmio;
1002         xlr_reg_t *mii_mmio;
1003         xlr_reg_t *pcs_mmio;
1004         xlr_reg_t *serdes_mmio;
1005
1006         int txbucket;
1007         int rfrbucket;
1008
1009         int phy_oldbmsr;
1010         int phy_oldanlpar;
1011         int phy_oldk1stsr;
1012         int phy_oldlinkstat;
1013         unsigned char phys_addr[2];
1014
1015         xlr_mac_speed_t speed;  /* current speed */
1016         xlr_mac_duplex_t duplex;/* current duplex */
1017         xlr_mac_link_t link;    /* current link */
1018         xlr_mac_fc_t flow_ctrl; /* current flow control setting */
1019         int advertising;
1020
1021         int id;
1022         int type;
1023         int mode;
1024         int instance;
1025         int phy_addr;
1026         int frin_to_be_sent[8];
1027         int init_frin_desc;
1028 };
1029
1030 struct rge_softc {
1031         int unit;
1032         int irq;
1033         unsigned char dev_addr[6];
1034         unsigned long base_addr;
1035         unsigned long mem_end;
1036         struct ifnet *rge_ifp;  /* interface info */
1037         device_t rge_dev;
1038         int mtu;
1039         int flags;
1040         struct driver_data priv;
1041         struct mtx rge_mtx;
1042         device_t rge_miibus;
1043         struct mii_data rge_mii;/* MII/media information */
1044         bus_space_handle_t rge_bhandle;
1045         bus_space_tag_t rge_btag;
1046         void *rge_intrhand;
1047         struct resource rge_irq;
1048         struct resource *rge_res;
1049         struct ifmedia rge_ifmedia;     /* TBI media info */
1050         int rge_if_flags;
1051         int rge_link;           /* link state */
1052         int rge_link_evt;       /* pending link event */
1053         struct callout rge_stat_ch;
1054         void (*xmit) (struct ifnet *);
1055         void (*stop) (struct rge_softc *);
1056         int (*ioctl) (struct ifnet *, u_long, caddr_t);
1057         struct rge_softc_stats *(*get_stats) (struct rge_softc *);
1058         int active;
1059         int link_up;
1060 };
1061
1062 struct size_1_desc {
1063         uint64_t entry0;
1064 };
1065
1066 struct size_2_desc {
1067         uint64_t entry0;
1068         uint64_t entry1;
1069 };
1070
1071 struct size_3_desc {
1072         uint64_t entry0;
1073         uint64_t entry1;
1074         uint64_t entry2;
1075 };
1076
1077 struct size_4_desc {
1078         uint64_t entry0;
1079         uint64_t entry1;
1080         uint64_t entry2;
1081         uint64_t entry3;
1082 };
1083
1084 struct fr_desc {
1085         struct size_1_desc d1;
1086 };
1087
1088 union rx_tx_desc {
1089         struct size_2_desc d2;
1090         /* struct size_3_desc d3; */
1091         /* struct size_4_desc d4; */
1092 };
1093
1094
1095 extern unsigned char xlr_base_mac_addr[];
1096
1097 #endif