2 * Copyright (c) 2015 Stanislav Galabov.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
7 * 1. Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * This is based on the pci allocator code from sys/dev/arm/mv/:
27 * Copyright (c) 2008 MARVELL INTERNATIONAL LTD.
28 * Copyright (c) 2010 The FreeBSD Foundation
29 * Copyright (c) 2010-2012 Semihalf
30 * All rights reserved.
32 * Developed by Semihalf.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include <sys/param.h>
38 #include <sys/systm.h>
41 #include <sys/interrupt.h>
42 #include <sys/malloc.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
47 #include <sys/mutex.h>
48 #include <sys/endian.h>
52 #include <vm/vm_extern.h>
54 #include <machine/bus.h>
55 #include <machine/cpu.h>
56 #include <machine/intr_machdep.h>
58 #include <dev/pci/pcivar.h>
59 #include <dev/pci/pcireg.h>
61 #include <dev/pci/pcib_private.h>
64 #include <mips/rt305x/rt305xreg.h>
65 #include <mips/rt305x/rt305x_pcireg.h>
66 #include <mips/rt305x/rt305x_sysctlvar.h>
68 struct mtx rt305x_pci_mtx;
69 MTX_SYSINIT(rt305x_pci_mtx, &rt305x_pci_mtx, "rt305x PCI/PCIe mutex", MTX_SPIN);
71 struct rt305x_pci_softc {
74 bus_space_tag_t sc_bst;
75 bus_space_handle_t sc_bsh;
79 struct rman sc_mem_rman;
80 struct rman sc_io_rman;
81 struct rman sc_irq_rman;
83 bus_addr_t sc_mem_base;
84 bus_addr_t sc_mem_size;
85 uint32_t sc_mem_map[(256*1024*1024) /
86 (PCI_MIN_MEM_ALLOC * BITS_PER_UINT32)];
88 bus_addr_t sc_io_base;
89 bus_addr_t sc_io_size;
90 uint32_t sc_io_map[(16*1024*1024) /
91 (PCI_MIN_IO_ALLOC * BITS_PER_UINT32)];
93 struct intr_event *sc_eventstab[RT305X_PCI_NIRQS];
94 mips_intrcnt_t sc_intr_counter[RT305X_PCI_NIRQS];
99 static void rt305x_pci_phy_init(device_t);
100 static void rt305x_pci_init(device_t);
101 static int rt305x_pcib_init(device_t, int, int);
102 static int rt305x_pci_intr(void *);
104 static void rt305x_pci_dump_regs(device_t);
106 static struct rt305x_pci_softc *rt_sc = NULL;
109 rt305x_pci_probe(device_t dev)
112 return (BUS_PROBE_NOWILDCARD);
116 rt305x_pci_attach(device_t dev)
118 struct rt305x_pci_softc *sc = device_get_softc(dev);
123 sc->sc_mem_base = PCIE_MEM_BASE;
124 sc->sc_mem_size = 0x10000000;
125 sc->sc_io_base = PCIE_IO_BASE;
126 sc->sc_io_size = 0x10000;
128 sc->sc_bsh = MIPS_PHYS_TO_KSEG1(PCIE_BASE);
129 sc->sc_bst = mips_bus_space_generic;
131 sc->sc_mem_rman.rm_type = RMAN_ARRAY;
132 sc->sc_mem_rman.rm_descr = "rt305x pci memory window";
133 if (rman_init(&sc->sc_mem_rman) != 0 ||
134 rman_manage_region(&sc->sc_mem_rman, sc->sc_mem_base,
135 sc->sc_mem_base + sc->sc_mem_size - 1) != 0) {
136 panic("%s: failed to set up memory rman", __FUNCTION__);
139 sc->sc_io_rman.rm_type = RMAN_ARRAY;
140 sc->sc_io_rman.rm_descr = "rt305x pci io window";
141 if (rman_init(&sc->sc_io_rman) != 0 ||
142 rman_manage_region(&sc->sc_io_rman, sc->sc_io_base,
143 sc->sc_io_base + sc->sc_io_size - 1) != 0) {
144 panic("%s: failed to set up io rman", __FUNCTION__);
147 sc->sc_irq_rman.rm_type = RMAN_ARRAY;
148 sc->sc_irq_rman.rm_descr = "rt305x pci irqs";
149 if (rman_init(&sc->sc_irq_rman) != 0 ||
150 rman_manage_region(&sc->sc_irq_rman, RT305X_PCIE0_IRQ,
151 RT305X_PCIE0_IRQ) != 0) {
152 panic("%s: failed to set up irq rman", __FUNCTION__);
155 cpu_establish_hardintr("pci", rt305x_pci_intr, NULL, sc,
156 RT305X_PCI_INTR_PIN, INTR_TYPE_MISC | INTR_EXCL, NULL);
158 rt305x_pci_phy_init(dev);
160 rt305x_pci_init(dev);
162 rt305x_pci_dump_regs(dev);
164 rt305x_pcib_init(dev, 0, PCI_SLOTMAX);
166 device_add_child(dev, "pci", -1);
168 return (bus_generic_attach(dev));
172 rt305x_pci_read_ivar(device_t dev, device_t child, int which,
175 struct rt305x_pci_softc *sc = device_get_softc(dev);
178 case PCIB_IVAR_DOMAIN:
179 *result = device_get_unit(dev);
182 *result = sc->sc_busno;
190 rt305x_pci_write_ivar(device_t dev, device_t child, int which,
193 struct rt305x_pci_softc *sc = device_get_softc(dev);
197 sc->sc_busno = result;
204 static struct resource *
205 rt305x_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
206 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
208 struct rt305x_pci_softc *sc = device_get_softc(bus);
215 rm = &sc->sc_irq_rman;
218 rm = &sc->sc_io_rman;
221 rm = &sc->sc_mem_rman;
227 rv = rman_reserve_resource(rm, start, end, count, flags, child);
232 rman_set_rid(rv, *rid);
234 if (type != SYS_RES_IRQ) {
235 if (type == SYS_RES_MEMORY) {
236 va = (vm_offset_t)pmap_mapdev(start, count);
237 } else if (type == SYS_RES_IOPORT){
238 va = (vm_offset_t)MIPS_PHYS_TO_KSEG1(start);
240 rman_set_bushandle(rv, va);
241 rman_set_virtual(rv, (void *)va);
242 rman_set_bustag(rv, mips_bus_space_generic);
245 if (flags & RF_ACTIVE) {
246 if (bus_activate_resource(child, type, *rid, rv)) {
247 rman_release_resource(rv);
256 rt305x_pci_activate_resource(device_t bus, device_t child, int type, int rid,
260 return rman_activate_resource(r);
264 rt305x_idx_to_irq(int idx)
267 return ((idx == 0) ? RT305X_PCIE0_IRQ :
268 (idx == 1) ? RT305X_PCIE1_IRQ :
269 (idx == 2) ? RT305X_PCIE2_IRQ : -1);
273 rt305x_irq_to_idx(int irq)
276 return ((irq == RT305X_PCIE0_IRQ) ? 0 :
277 (irq == RT305X_PCIE1_IRQ) ? 1 :
278 (irq == RT305X_PCIE2_IRQ) ? 2 : -1);
282 rt305x_pci_mask_irq(void *source)
285 RT_WRITE32(rt_sc, RT305X_PCI_PCIENA,
286 RT_READ32(rt_sc, RT305X_PCI_PCIENA) & ~(1<<((int)source)));
290 rt305x_pci_unmask_irq(void *source)
293 RT_WRITE32(rt_sc, RT305X_PCI_PCIENA,
294 RT_READ32(rt_sc, RT305X_PCI_PCIENA) | (1<<((int)source)));
298 rt305x_pci_setup_intr(device_t bus, device_t child, struct resource *ires,
299 int flags, driver_filter_t *filt, driver_intr_t *handler,
300 void *arg, void **cookiep)
302 struct rt305x_pci_softc *sc = device_get_softc(bus);
303 struct intr_event *event;
304 int irq, error, irqidx;
306 irq = rman_get_start(ires);
308 if ((irqidx = rt305x_irq_to_idx(irq)) == -1)
309 panic("%s: bad irq %d", __FUNCTION__, irq);
311 event = sc->sc_eventstab[irqidx];
313 error = intr_event_create(&event, (void *)irq, 0, irq,
314 rt305x_pci_mask_irq, rt305x_pci_unmask_irq, NULL, NULL,
318 sc->sc_eventstab[irqidx] = event;
319 sc->sc_intr_counter[irqidx] =
320 mips_intrcnt_create(event->ie_name);
326 intr_event_add_handler(event, device_get_nameunit(child), filt,
327 handler, arg, intr_priority(flags), flags, cookiep);
329 mips_intrcnt_setname(sc->sc_intr_counter[irqidx], event->ie_fullname);
331 rt305x_pci_unmask_irq((void*)irq);
337 rt305x_pci_teardown_intr(device_t dev, device_t child, struct resource *ires,
340 struct rt305x_pci_softc *sc = device_get_softc(dev);
341 int irq, result, irqidx;
343 irq = rman_get_start(ires);
344 if ((irqidx = rt305x_irq_to_idx(irq)) == -1)
345 panic("%s: bad irq %d", __FUNCTION__, irq);
347 if (sc->sc_eventstab[irqidx] == NULL)
348 panic("Trying to teardown unoccupied IRQ");
350 rt305x_pci_mask_irq((void*)irq);
352 result = intr_event_remove_handler(cookie);
354 sc->sc_eventstab[irqidx] = NULL;
359 static inline uint32_t
360 rt305x_pci_make_addr(int bus, int slot, int func, int reg)
364 addr = (((reg & 0xf00) >> 8) << 24) | (bus << 16) | (slot << 11) |
365 (func << 8) | (reg & 0xfc) | (1 << 31);
371 rt305x_pci_maxslots(device_t dev)
374 return (PCI_SLOTMAX);
378 rt305x_pci_read_config(device_t dev, u_int bus, u_int slot, u_int func,
379 u_int reg, int bytes)
381 struct rt305x_pci_softc *sc = device_get_softc(dev);
382 uint32_t addr = 0, data = 0;
384 if (bus == 0 && (sc->pcie_link_status & (1<<slot)) == 0)
387 mtx_lock_spin(&rt305x_pci_mtx);
388 addr = rt305x_pci_make_addr(bus, slot, func, (reg & ~3));
389 RT_WRITE32(sc, RT305X_PCI_CFGADDR, addr);
392 data = RT_READ32(sc, RT305X_PCI_CFGDATA);
395 data = RT_READ8(sc, RT305X_PCI_CFGDATA + (reg & 0x3));
398 data = RT_READ16(sc, RT305X_PCI_CFGDATA + (reg & 0x3));
401 panic("%s(): Wrong number of bytes (%d) requested!\n",
402 __FUNCTION__, bytes % 4);
404 mtx_unlock_spin(&rt305x_pci_mtx);
410 rt305x_pci_write_config(device_t dev, u_int bus, u_int slot, u_int func,
411 u_int reg, uint32_t val, int bytes)
413 struct rt305x_pci_softc *sc = device_get_softc(dev);
414 uint32_t addr = 0, data = val;
416 if (bus == 0 && (sc->pcie_link_status & (1<<slot)) == 0)
419 mtx_lock_spin(&rt305x_pci_mtx);
420 addr = rt305x_pci_make_addr(bus, slot, func, (reg & ~3));
421 RT_WRITE32(sc, RT305X_PCI_CFGADDR, addr);
424 RT_WRITE32(sc, RT305X_PCI_CFGDATA, data);
427 RT_WRITE8(sc, RT305X_PCI_CFGDATA + (reg & 0x3), data);
430 RT_WRITE16(sc, RT305X_PCI_CFGDATA + (reg & 0x3), data);
433 panic("%s(): Wrong number of bytes (%d) requested!\n",
434 __FUNCTION__, bytes % 4);
436 mtx_unlock_spin(&rt305x_pci_mtx);
440 rt305x_pci_route_interrupt(device_t pcib, device_t device, int pin)
442 //struct rt305x_pci_softc *sc = device_get_softc(pcib);
445 bus = pci_get_bus(device);
446 sl = pci_get_slot(device);
449 panic("Unexpected bus number %d\n", bus);
451 //printf("%s: not done yet.\n", __FUNCTION__);
454 case 0: return RT305X_PCIE0_IRQ;
455 default: return (-1);
461 static device_method_t rt305x_pci_methods[] = {
462 /* Device interface */
463 DEVMETHOD(device_probe, rt305x_pci_probe),
464 DEVMETHOD(device_attach, rt305x_pci_attach),
465 DEVMETHOD(device_shutdown, bus_generic_shutdown),
466 DEVMETHOD(device_suspend, bus_generic_suspend),
467 DEVMETHOD(device_resume, bus_generic_resume),
470 DEVMETHOD(bus_read_ivar, rt305x_pci_read_ivar),
471 DEVMETHOD(bus_write_ivar, rt305x_pci_write_ivar),
472 DEVMETHOD(bus_alloc_resource, rt305x_pci_alloc_resource),
473 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
474 DEVMETHOD(bus_activate_resource, rt305x_pci_activate_resource),
475 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
476 DEVMETHOD(bus_setup_intr, rt305x_pci_setup_intr),
477 DEVMETHOD(bus_teardown_intr, rt305x_pci_teardown_intr),
480 DEVMETHOD(pcib_maxslots, rt305x_pci_maxslots),
481 DEVMETHOD(pcib_read_config, rt305x_pci_read_config),
482 DEVMETHOD(pcib_write_config, rt305x_pci_write_config),
483 DEVMETHOD(pcib_route_interrupt, rt305x_pci_route_interrupt),
484 DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
489 static driver_t rt305x_pci_driver = {
492 sizeof(struct rt305x_pci_softc),
495 static devclass_t rt305x_pci_devclass;
497 DRIVER_MODULE(rt305x_pci, nexus, rt305x_pci_driver, rt305x_pci_devclass, 0, 0);
500 rt305x_pci_dump_regs(device_t dev)
503 struct rt305x_pci_softc *sc = device_get_softc(dev);
507 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
510 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
513 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
516 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
519 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
522 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
525 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
528 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
531 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
534 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
537 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
540 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
543 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
546 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
549 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
552 printf("0x%04x: 0x%08x\n", reg, RT_READ32(sc, reg));
557 rt305x_pci_init(device_t dev)
559 struct rt305x_pci_softc *sc = device_get_softc(dev);
562 rt305x_sysctl_set(SYSCTL_SYSCFG1,
563 rt305x_sysctl_get(SYSCTL_SYSCFG1) | (1 << 8));
565 rt305x_sysctl_set(SYSCTL_GPIOMODE,
566 rt305x_sysctl_get(SYSCTL_GPIOMODE) & ~(0x3 << 16));
567 rt305x_sysctl_set(SYSCTL_RSTCTRL,
568 rt305x_sysctl_get(SYSCTL_RSTCTRL) & ~(1<<26));
569 rt305x_sysctl_set(SYSCTL_CLKCFG1,
570 rt305x_sysctl_get(SYSCTL_CLKCFG1) | (1<<26));
572 tmp = rt305x_sysctl_get(SYSCTL_PPLL_CFG1);
573 if ((tmp & (1<<23)) == 0) {
574 device_printf(dev, "PPLL not locked\n");
578 tmp = rt305x_sysctl_get(SYSCTL_PPLL_DRV);
580 rt305x_sysctl_set(SYSCTL_PPLL_DRV, tmp);
582 rt305x_sysctl_set(SYSCTL_PPLL_DRV, tmp);
584 rt305x_sysctl_set(SYSCTL_PPLL_DRV, tmp);
586 rt305x_sysctl_set(SYSCTL_PPLL_DRV, tmp);
588 RT_WRITE32(sc, RT305X_PCI_MEMBASE, sc->sc_mem_base);
589 RT_WRITE32(sc, RT305X_PCI_IOBASE, sc->sc_io_base);
591 RT_WRITE32(sc, RT305X_PCI_PCICFG, RT_READ32(sc, 0) & ~(1<<1));
593 if ((RT_READ32(sc, RT305X_PCI_PCIE0_STATUS) & 0x1) == 1)
594 sc->pcie_link_status = 1;
596 sc->pcie_link_status = 0;
598 RT_WRITE32(sc, RT305X_PCI_PCIE0_BAR0SETUP, 0x7FFF0001);
599 RT_WRITE32(sc, RT305X_PCI_PCIE0_BAR1SETUP, 0x00000000);
600 RT_WRITE32(sc, RT305X_PCI_PCIE0_IMBASEBAR0, 0x00000000);
601 RT_WRITE32(sc, RT305X_PCI_PCIE0_CLASS, 0x06040001);
603 tmp = rt305x_pci_read_config(dev, 0, 0, 0, 4, 4);
604 rt305x_pci_write_config(dev, 0, 0, 0, 4, tmp | 0x7, 4);
605 tmp = rt305x_pci_read_config(dev, 0, 0, 0, 0x70c, 4);
608 rt305x_pci_write_config(dev, 0, 0, 0, 0x70c, tmp, 4);
609 tmp = rt305x_pci_read_config(dev, 0, 0, 0, 0x70c, 4);
611 rt305x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0), 0, 4);
614 static inline uint32_t
615 pcib_bit_get(uint32_t *map, uint32_t bit)
617 uint32_t n = bit / BITS_PER_UINT32;
619 bit = bit % BITS_PER_UINT32;
620 return (map[n] & (1 << bit));
624 pcib_bit_set(uint32_t *map, uint32_t bit)
626 uint32_t n = bit / BITS_PER_UINT32;
628 bit = bit % BITS_PER_UINT32;
629 map[n] |= (1 << bit);
632 static inline uint32_t
633 pcib_map_check(uint32_t *map, uint32_t start, uint32_t bits)
637 for (i = start; i < start + bits; i++)
638 if (pcib_bit_get(map, i))
645 pcib_map_set(uint32_t *map, uint32_t start, uint32_t bits)
649 for (i = start; i < start + bits; i++)
650 pcib_bit_set(map, i);
654 pcib_alloc(device_t dev, uint32_t smask)
656 struct rt305x_pci_softc *sc = device_get_softc(dev);
657 uint32_t bits, bits_limit, i, *map, min_alloc, size;
662 base = sc->sc_io_base;
663 min_alloc = PCI_MIN_IO_ALLOC;
664 bits_limit = sc->sc_io_size / min_alloc;
668 base = sc->sc_mem_base;
669 min_alloc = PCI_MIN_MEM_ALLOC;
670 bits_limit = sc->sc_mem_size / min_alloc;
671 map = sc->sc_mem_map;
676 bits = size / min_alloc;
678 for (i = 0; i + bits <= bits_limit; i+= bits)
679 if (pcib_map_check(map, i, bits)) {
680 pcib_map_set(map, i, bits);
681 addr = base + (i * min_alloc);
689 rt305x_pcib_init_bar(device_t dev, int bus, int slot, int func, int barno)
694 reg = PCIR_BAR(barno);
696 rt305x_pci_write_config(dev, bus, slot, func, reg, ~0, 4);
697 bar = rt305x_pci_read_config(dev, bus, slot, func, reg, 4);
701 /* Calculate BAR size: 64 or 32 bit (in 32-bit units) */
702 width = ((bar & 7) == 4) ? 2 : 1;
704 addr = pcib_alloc(dev, bar);
709 printf("PCI %u:%u:%u: reg %x: smask=%08x: addr=%08x\n",
710 bus, slot, func, reg, bar, addr);
712 rt305x_pci_write_config(dev, bus, slot, func, reg, addr, 4);
714 rt305x_pci_write_config(dev, bus, slot, func, reg + 4, 0, 4);
720 rt305x_pcib_init_all_bars(device_t dev, int bus, int slot, int func,
725 maxbar = (hdrtype & PCIM_HDRTYPE) ? 0 : 6;
728 while (bar < maxbar) {
729 i = rt305x_pcib_init_bar(dev, bus, slot, func, bar);
732 device_printf(dev, "PCI IO/Memory space exhausted\n");
741 rt305x_pci_slot_has_link(device_t dev, int slot)
743 struct rt305x_pci_softc *sc = device_get_softc(dev);
745 return !!(sc->pcie_link_status & (1<<slot));
748 static int cur_secbus = 0;
751 rt305x_pcib_init_bridge(device_t dev, int bus, int slot, int func)
753 struct rt305x_pci_softc *sc = device_get_softc(dev);
754 bus_addr_t io_base, mem_base;
755 uint32_t io_limit, mem_limit;
758 if (bus == 0 && !rt305x_pci_slot_has_link(dev, slot)) {
759 device_printf(dev, "Skip bus %d due to no link\n",++cur_secbus);
763 io_base = sc->sc_io_base;
764 io_limit = io_base + sc->sc_io_size - 1;
765 mem_base = sc->sc_mem_base;
766 mem_limit = mem_base + sc->sc_mem_size - 1;
768 rt305x_pci_write_config(dev, bus, slot, func, PCIR_IOBASEL_1,
770 rt305x_pci_write_config(dev, bus, slot, func, PCIR_IOBASEH_1,
772 rt305x_pci_write_config(dev, bus, slot, func, PCIR_IOLIMITL_1,
774 rt305x_pci_write_config(dev, bus, slot, func, PCIR_IOLIMITH_1,
777 rt305x_pci_write_config(dev, bus, slot, func, PCIR_MEMBASE_1,
779 rt305x_pci_write_config(dev, bus, slot, func, PCIR_MEMLIMIT_1,
782 rt305x_pci_write_config(dev, bus, slot, func, PCIR_PMBASEL_1,
784 rt305x_pci_write_config(dev, bus, slot, func, PCIR_PMBASEH_1,
786 rt305x_pci_write_config(dev, bus, slot, func, PCIR_PMLIMITL_1,
788 rt305x_pci_write_config(dev, bus, slot, func, PCIR_PMLIMITH_1,
791 secbus = rt305x_pci_read_config(dev, bus, slot, func, PCIR_SECBUS_1, 1);
794 rt305x_pci_write_config(dev, bus, slot, func, PCIR_SECBUS_1,
796 rt305x_pci_write_config(dev, bus, slot, func, PCIR_SUBBUS_1,
801 rt305x_pcib_init(dev, secbus, PCI_SLOTMAX);
805 rt305x_pcib_init(device_t dev, int bus, int maxslot)
807 int slot, func, maxfunc, error;
808 uint8_t hdrtype, command, class, subclass;
810 for (slot = 0; slot <= maxslot; slot++) {
812 for (func = 0; func <= maxfunc; func++) {
813 hdrtype = rt305x_pci_read_config(dev, bus, slot, func,
816 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
819 if (func == 0 && (hdrtype & PCIM_MFDEV))
820 maxfunc = PCI_FUNCMAX;
822 command = rt305x_pci_read_config(dev, bus, slot, func,
824 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN);
825 rt305x_pci_write_config(dev, bus, slot, func,
826 PCIR_COMMAND, command, 1);
828 error = rt305x_pcib_init_all_bars(dev, bus, slot, func,
834 command |= PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN |
836 rt305x_pci_write_config(dev, bus, slot, func,
837 PCIR_COMMAND, command, 1);
839 rt305x_pci_write_config(dev, bus, slot, func,
840 PCIR_CACHELNSZ, 16, 1);
842 class = rt305x_pci_read_config(dev, bus, slot, func,
844 subclass = rt305x_pci_read_config(dev, bus, slot, func,
847 if (class != PCIC_BRIDGE || subclass != PCIS_BRIDGE_PCI)
850 rt305x_pcib_init_bridge(dev, bus, slot, func);
857 #define BUSY 0x80000000
858 #define WAITRETRY_MAX 10
859 #define WRITE_MODE (1<<23)
864 rt305x_wait_pci_phy_busy(struct rt305x_pci_softc *sc)
866 uint32_t reg_value = 0x0, retry = 0;
869 reg_value = RT_READ32(sc, RT305X_PCI_PHY0_CFG);
870 if (reg_value & BUSY)
874 if (retry++ > WAITRETRY_MAX) {
875 printf("PHY retry failed\n");
883 rt305x_pci_phy(struct rt305x_pci_softc *sc, char rwmode, uint32_t addr,
886 uint32_t reg_value = 0x0;
888 rt305x_wait_pci_phy_busy(sc);
890 reg_value |= WRITE_MODE;
891 reg_value |= (val) << DATA_SHIFT;
893 reg_value |= (addr) << ADDR_SHIFT;
895 RT_WRITE32(sc, RT305X_PCI_PHY0_CFG, reg_value);
898 rt305x_wait_pci_phy_busy(sc);
901 reg_value = RT_READ32(sc, RT305X_PCI_PHY0_CFG);
909 rt305x_pci_phy_init(device_t dev)
911 struct rt305x_pci_softc *sc = device_get_softc(dev);
914 rt305x_pci_phy(sc, 'w', 0x00, 0x80);
915 rt305x_pci_phy(sc, 'w', 0x01, 0x04);
916 rt305x_pci_phy(sc, 'w', 0x68, 0x84);
918 rt305x_sysctl_set(SYSCTL_RSTCTRL,
919 rt305x_sysctl_get(SYSCTL_RSTCTRL) | (1<<26));
920 rt305x_sysctl_set(SYSCTL_CLKCFG1,
921 rt305x_sysctl_get(SYSCTL_CLKCFG1) & ~(1<<26));
923 tmp = rt305x_sysctl_get(SYSCTL_PPLL_CFG1);
925 rt305x_sysctl_set(SYSCTL_PPLL_CFG1, tmp);
927 rt305x_sysctl_set(SYSCTL_PPLL_CFG1, tmp);
931 rt305x_pci_intr(void *arg)
933 struct rt305x_pci_softc *sc = arg;
934 struct intr_event *event;
935 uint32_t reg, irq, irqidx;
937 reg = RT_READ32(sc, RT305X_PCI_PCIINT);
939 for (irqidx = 0; irqidx < RT305X_PCI_NIRQS; irqidx++) {
940 irq = rt305x_idx_to_irq(irqidx);
941 if (reg & (1<<irq)) {
942 event = sc->sc_eventstab[irqidx];
943 if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
945 printf("Stray PCI IRQ %d\n", irq);
949 intr_event_handle(event, NULL);
950 mips_intrcnt_inc(sc->sc_intr_counter[irqidx]);
954 return (FILTER_HANDLED);